JPS59139462A - Error detecting device - Google Patents

Abstract

PURPOSE:To enable limitation of a task that generated an error and enable time out check in a state of waiting in addition to acting state by providing a counter for each task and setting a value to the counter at the time of starting the task. CONSTITUTION:When each task starts processing, an operation system OS sets (1x-)2 to the counter of corresponding task. After completion of processing (F20) of the task, (00...)2 is set to the counter of corresponding task, i.e. it is cleared. By such a counter, it becomes possible to check time out in a waiting state in addition to the state of action. When a select signal 51 is supposed as 1, as selectors (SEL) 11, 12 select 1 side, a memory 10 can be accessed making the number (TN) 52 of started or completed task an address. When write pulse is put in the memory 10, set value 53 is set to the memory 10 as write data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a program process detection device.

[Prior art]

There are various methods for detecting program errors and preventing malfunctions and destruction of other programs, such as protection checks and invalid instruction checks, and one of them is a check using a watchdog timer.

This check is to detect all errors, such as program loops, that at first glance seem to indicate that the computer is operating normally, and is generally performed as follows.

First, the computer has a counter for the watchdog timer, and the hardware subtracts this counter at regular intervals. When the value of this counter reaches a certain value, for example, 0", an error is generated. To avoid errors, In order to do this, it is necessary to programmatically reset the value within a certain period of time, and this process usually has the lowest priority level.
It is configured as a task (hereinafter abbreviated as WDT task) that is activated periodically. Therefore, if the program of a task with a high priority level continues to run in a loop,
During this time, the WDT task cannot be processed, that is, the value cannot be reset to the counter, and an error is output after a certain period of time.

However, this checking method has the following problems.

(1) You cannot know which task caused the error unless you stop the computer and analyze it.

(Reason) Even if the program of a certain task is in a loop state, tasks with higher priority and level than that task can operate. Therefore, the task that was running at the time the error occurred is not necessarily the cause of the error.

(2) It is not possible to detect an error in which a task enters an event waiting state and the event does not occur.

(Reason) In order to achieve synchronization, a task enters a state in which it has received the occurrence of a certain event (hereinafter referred to as WAIT state), and since the event does not occur for some reason, the task is in the WAIT state. There may be errors such as not being able to move on to the next process until the next step. However, even if the task is in the WAIT state, it is not running, so the WDT task cannot run.
Therefore this error cannot be detected.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an error detection device that solves the above problems.

[Summary of the invention]

A feature of the present invention is that a counter is provided for each task, a value is set in the counter at the start of the task, and the value of the counter is updated by hardware at a fixed period. When the value of the counter reaches a specific value, The task is to designate it as work 2-.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a hardware configuration diagram of an embodiment of the present invention.

Here, a counter for each task is realized by the memory 10. One word of memory 1o is allocated for each task,
The entire configuration is shown in Figure 2. This word consists of 16 bits. Bit 0 indicates whether the task is running, waiting (when the value is "1"), or not activated (when the value is "0").
The remaining 1s bit constitutes a binary color scheme. FIG. 3 is a diagram showing the movement of each task. When each task starts processing (F20), O8 sets the counter of the corresponding task to (1 thick, old, . . . X)z k (FIO). (K...xLO value is at least a value larger than the processing time of the task in question during normal operation (converted to the cycle at which the counter is updated).Then, the task processing (F20) After finishing, set (OO...0)z in the corresponding task's counter, that is, clear it.With such a counter, it is possible to check the timeout while in the waiting state as well as during the operation. Become.

Hereinafter, referring back to FIG. 1, the operation of the hardware will be explained.

First, the operation of setting the redemption amount in the counter by the memory 10 will be explained.

When the select signal 51e is "l", each selector (SE
L) Since 11.12 selects the 11" side, the memory 10 can be accessed as the entire address of the task number (TN) 52 to be started or ended, and if it is stored in the entire Reithals memory 10, 7 and the set value 53 will be the write data. memory 10
is set to

Next, an explanation will be given of the operation when the counter is updated at a constant period by the memory 10.

If the select signal 51 is all ``0'', each 8EI.

11.12 selects the “O” sidetone, so the task number (T
N) 54 can access the memory 10.

Note that the access interval of the memory 10 in the same TN54 is a constant cycle, and all task numbers are accessed in order. The counter 1 value successively outputted from the memory 1o is inputted to the subtracter 13, and when the value is "0", it is output as is, and when the value is other than "0", it is output after being subtracted by "1". The "0" check circuit 14 and the selector (SEL) 15 perform these switches. And the subtracted counter value is S ELI 2=
After a certain period of time, the color value is written into the memory 10 via i, and the counter value is updated in this way.

The operation when an error is output at the end will be explained.

Counter total task number (T N) 54 by memory 10
During the update, the output of the subtracter 13 is checked by the circuit engineer 5 to check that it is "0", and the bit 0 of the counter is "1" in o#.
” (task is in operation or waiting state), an error signal 55 is output. Therefore, at the time the error signal 55 is output, the memory l.

It can be seen that an error has occurred in the task with task number (TN) 54 that is being accessed completely.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to limit the task that caused the error, and it is also possible to perform a timeout check while in the waiting state as well as during operation.

[Brief explanation of the drawing]

FIG. 1 is a hardware configuration diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of a memory counter, and FIG. 3 is a diagram showing the movement amount of each task. 10...Memo 1c 13...Subtractor, 16..."
0" check circuit. Funeral 1 diagram ERRσR

Claims (1)

[Claims] 1. In a computer system, each task has a counter, a mechanism for setting a value in the counter, and a mechanism for updating the counter at a constant cycle, and when the counter reaches a specific value, the task is marked as an error. An error detection device characterized by: