JPS59138353A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS59138353A
JPS59138353A JP58012262A JP1226283A JPS59138353A JP S59138353 A JPS59138353 A JP S59138353A JP 58012262 A JP58012262 A JP 58012262A JP 1226283 A JP1226283 A JP 1226283A JP S59138353 A JPS59138353 A JP S59138353A
Authority
JP
Japan
Prior art keywords
wire
pads
pad
chip
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58012262A
Other languages
Japanese (ja)
Inventor
Hideto Iwama
岩間　秀人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP58012262A priority Critical patent/JPS59138353A/en
Publication of JPS59138353A publication Critical patent/JPS59138353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase the degree of freedom of IC design without restricting the selection of pad position by a method wherein at least of a point or more of the wire junctions for wire bonding which connect pads in a chip to lead frames of a package are provided in a bed or the semiconductor chip in the package of an IC device. CONSTITUTION:The semiconductor chip 12 is fixed on the bed 16 which constitutes the IC device, and a plurality of pads 13a and 13b, etc. provided thereto are connected to the lead frames 11a and 11b adjacent to the chip 12 by using bonding wires 14, respectively. In this constitution, when the pad 13b is connected to the frame 11b after connecting the pad 13a to the frame 11a by means of the wire 14, this wire 14 may pass over the pervious wire 14, resulting in contact. Therefore, junction pads, the junctions of the wires 14, are kept provided in a required number at the marginal region of the bed 16, and then any wire 14 is made to detour.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は集積回路装置に関し、更に詳しくは半導体チッ
プと集積回路装置の外部端子との電気的接続をワイヤボ
ンディング法によって成された集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device in which a semiconductor chip and an external terminal of the integrated circuit device are electrically connected by a wire bonding method.

〔従来技術〕[Prior art]

従来、集積回路装置を作製する場合は、半導体チップ内
の入出力用電極（以下パッドと称する）と集積回路装置
の外部の入出力端子（以下リードフレームと称する）と
を細い金属線を用いて、即ちワイヤボンディング法によ
って接続することが行なわれている。しかし、ワイヤボ
ンディング法によって配線同士が干渉し合うことなく、
或はワイヤとパッドが干渉し合うことなく配線を行なう
為には、集積回路の設計時点からパッドとリードフレー
ムの位置関係を考慮して集積回路を設計し、パッドの位
置決めをすることが必要であった。その為、集積回路の
設計は各パッドやリードフレームの配置によって著しく
その設計の自由度を制限されている。又、チップ内のパ
ッドに応じてリードフレームの位置を変更することは、
同じ動作をする集積回路同士の互換性をも損うこととな
り非常に都合の恕いものである。Conventionally, when manufacturing integrated circuit devices, thin metal wires are used to connect input/output electrodes (hereinafter referred to as pads) inside a semiconductor chip and input/output terminals (hereinafter referred to as lead frames) outside the integrated circuit device. That is, connection is performed by a wire bonding method. However, the wire bonding method prevents the wiring from interfering with each other.
Alternatively, in order to conduct wiring without interference between wires and pads, it is necessary to design the integrated circuit and position the pads by considering the positional relationship between the pads and the lead frame from the time of designing the integrated circuit. there were. Therefore, the degree of freedom in designing integrated circuits is significantly limited by the arrangement of pads and lead frames. Also, changing the position of the lead frame according to the pads within the chip is
This is extremely inconvenient since it also impairs compatibility between integrated circuits that operate in the same way.

〔目　白り〕[white eyes]

本発明は接続線であるワイヤ同士、或はチップ内のパッ
ドとワイヤの不必要な接触が生じない様な構成を持った
集積回路装置を提供することを目的とする０又、本発明
鉱、集積回路の設計に自由度を与え、ワイヤボンディン
グ法を容易ならしめることを目的とする。An object of the present invention is to provide an integrated circuit device having a structure that prevents unnecessary contact between wires serving as connection lines or between wires and pads within a chip. The purpose is to provide flexibility in the design of integrated circuits and to facilitate the wire bonding method.

本発明の集積回路装置社、集積回路装置のパッケージ内
のベッド或は半導体チップ中に、チップ内のパッドとリ
ードフレームとを接続するワイヤボンディングのワイヤ
の中継点が少なくとも１箇所以上設けられていることを
特徴とする。According to the integrated circuit device company of the present invention, at least one relay point for wire bonding that connects pads in the chip and lead frames is provided in the bed or semiconductor chip in the package of the integrated circuit device. It is characterized by

本発明によれば、チップ内のパッドの位置を任意の所に
配置してもワイヤボンディングが行なえるので、集積回
路の設計に自由度が増す。According to the present invention, wire bonding can be performed even if the pads within the chip are placed at arbitrary positions, thereby increasing the degree of freedom in designing integrated circuits.

〔実施例〕〔Example〕

以下、本発明を図を用いて説明する。 Hereinafter, the present invention will be explained using figures.

第１図は、本発明の好適な１つの実施例を説明する為の
模式的説明図で、ｌｌａ、１１ｂはリードフレーム、１
２は半導体チップ、１３ａ、１３ｂはチップ内のパッド
、１４は接続配線用ワイヤ、１５はワイヤ１４の中継点
である中継バッド、１６はチップを固定する基板である
ベッドである。FIG. 1 is a schematic explanatory diagram for explaining one preferred embodiment of the present invention, in which lla and 11b are lead frames;
2 is a semiconductor chip, 13a and 13b are pads inside the chip, 14 is a connection wiring wire, 15 is a relay pad that is a relay point for the wire 14, and 16 is a bed that is a substrate for fixing the chip.

第１図に示でれる様に、ワイヤ１４は直線的に各パッド
とリードフレームを接続スる。パッド１３ｂに対応する
リードフレーム１１ｂに配線を行なう場合、ワイヤ１４
は第１図中に破線で示される様に接続されている。しか
し、この場合け、パッド１３ｂとリードフレーム１１ｂ
を結ぶワイヤがパッド１３ａ上を通過する為、前記ワイ
ヤとパッド１３ａとが接触してしまい正確な配線がな式
れなくなる。As shown in FIG. 1, wires 14 connect each pad to the lead frame in a straight line. When wiring the lead frame 11b corresponding to the pad 13b, the wire 14
are connected as shown by broken lines in FIG. However, in this case, the pad 13b and the lead frame 11b
Since the wire connecting the pads 13a passes over the pads 13a, the wires come into contact with the pads 13a, making accurate wiring impossible.

そこで、本発明で社、チップを固定する基板であるパッ
ケージのベッド１６内に例えば金などを用いてエツチン
グや埋め込みによって形成された中継ベッド１５が設け
られた。第１図に示される様に、他の配線に接触するこ
となく、且つ、パッド１３ｂから中継パッド１５まで厘
線で結んだワイヤがパッド１３ａ及びその他のパッド、
又は他のワイヤ１４に触れることのない位置に中継パッ
ド１５が設けられた。更に、中継パッド１５の位置は、
中継パッド１５とリードフレーム１１ｂとを＠線で結ん
だワイヤ１４が他のリードフレームやワイヤと触れるこ
とのない位置にもなっている。Therefore, in the present invention, a relay bed 15 formed by etching or embedding using, for example, gold is provided in the bed 16 of the package, which is the substrate on which the chip is fixed. As shown in FIG. 1, the wire connected from pad 13b to relay pad 15 with a loop wire without contacting other wiring connects pad 13a and other pads.
Alternatively, the relay pad 15 is provided at a position where it does not touch other wires 14. Furthermore, the position of the relay pad 15 is
The wire 14 connecting the relay pad 15 and the lead frame 11b with the @ wire is also located at a position where it does not come into contact with other lead frames or wires.

この様に、パッド１３ｂとリードフレームｌｌｂとをワ
イヤ１４で接続するにあたってパッド１３ａを迂回する
様に中継パッド１５を設けることによって、集積回路装
置の回路等の手直しを行なうこトナく、チップ内のバ謔
ドと外部端子とナル！Ｊ　−ドフレームとを接続するこ
とが出来た０第２図は、本発明の別の実施例を説明する
為の説明図で、２１ａ乃至２１１）はリードフレーム、
２２は半導体チップ、２３はバツケ〜ジのベッド、２４
はチップ内に配されたパッド、２５はワイヤ、２６は中
継パッドである０ 第２図に示される様に、本実施例に於いてもパッド２４
とリードフレームとを直線的にワイヤで接続できる時は
中継パッド２６を介さずに接続し、他のパッドやワイヤ
ー等圧影響されて接続不能の時Ｌ、中継パッド２６を用
いて接続された。In this way, by providing the relay pad 15 so as to bypass the pad 13a when connecting the pad 13b and the lead frame llb with the wire 14, it is possible to avoid modifying the circuits of the integrated circuit device. Bar code, external terminal and null! 2 is an explanatory diagram for explaining another embodiment of the present invention, in which 21a to 211) are connected to a lead frame,
22 is a semiconductor chip, 23 is a bucket bed, 24
2 is a pad arranged inside the chip, 25 is a wire, and 26 is a relay pad.0 As shown in FIG.
When it was possible to connect the lead frame and the lead frame linearly with a wire, the connection was made without using the relay pad 26, and when the connection was impossible due to the influence of the equal pressure of other pads or wires, the connection was made using the relay pad 26.

これＫよって、本実施例でもチップ内のパッドの配置を
変えることなく所定の位置のリードフレームとチップ内
のパッドを接続することができた。Therefore, in this embodiment as well, the lead frame at a predetermined position and the pads in the chip could be connected without changing the arrangement of the pads in the chip.

〔効　果〕〔effect〕

以上説明した様に、パッケージのリードフレームとそれ
に対応するチップの各パッドをワイヤボンディングする
場合、パッケージのベッドに設けられた中継パッドを介
してワイヤを接続する事によって、例えば実施例の様な
パッドの配置であってもワイヤの接続を行なえる様にな
る。これは従来の様にパッドの位置の制約が非常に少な
くなる為、即ち中継パッドの位置の自由度が増す為、中
継パッドは任意の位置に配置可能になり、集積回路の設
計も容易になる。As explained above, when wire-bonding the package lead frame and each pad of the corresponding chip, for example, by connecting the wires through the relay pad provided on the package bed, Wire connections can be made even in this arrangement. This is because there are far fewer restrictions on the position of the pads than in the past, meaning there is more freedom in the position of the relay pads, allowing the relay pads to be placed in any position, making it easier to design integrated circuits. .

中継パッドは多数設置して端子数の多いパッケージに用
いると更に有効であり、又、集積回路装置の開発段階即
ち、試作段階の集積回路装置に用いても有効である。It is more effective when a large number of relay pads are installed and used in a package with a large number of terminals, and it is also effective when used in an integrated circuit device in the development stage of an integrated circuit device, that is, in the prototype stage.

尚、中継パッドは本実施例の様にパッケージのベッド内
に設けなくとも半導体チップの中に設けられても良いも
のである。又、中継パッドは、中空セラミック・パッケ
ージ等にももちろん用いることができる。Note that the relay pads do not have to be provided in the bed of the package as in this embodiment, but may be provided in the semiconductor chip. Also, the relay pad can of course be used for hollow ceramic packages and the like.

中継パッドの高さは一定である必要はなく、上下に差を
つけてワイヤをくぐらせることも必要に応じて行なうこ
とが可能である０又、ワイヤはパラドとリードフレーム
の間を２個以上の中継パッドを用いて接続されても全く
かまわない０The height of the relay pad does not need to be constant, and it is possible to pass the wire through it with a difference in the top and bottom as necessary.Also, two or more wires can be passed between the pad and the lead frame. It does not matter at all if it is connected using a relay pad of 0

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は夫々本発明の詳細な説明するための
説明図で第１図は模式的平面部分図、第２図は模式的平
面図である。 １１ａ、１１ｂ、２１ａ乃至２１ｐ−・−リードフレー
ム１２．２２＠・・半導体チップ １３ａ、１３ｂ、２４−−−パッド １４．２５・・・ワイヤ １５．２６・・・中継パッド １６．２３・ｅ・ベッド 出願人　キャノン株式会社1 and 2 are explanatory diagrams for explaining the present invention in detail, respectively. FIG. 1 is a schematic partial plan view, and FIG. 2 is a schematic plan view. 11a, 11b, 21a to 21p--Lead frame 12.22@...Semiconductor chip 13a, 13b, 24--Pad 14.25...Wire 15.26...Relay pad 16.23.e. Bed applicant Canon Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 集積回路装置のパッケージ内のベッド或は半導体チップ
中に、チップ内のパッドとパッケージのリードフレーム
とを接続するワイヤボンディングのワイヤの中継点が少
なくとも１箇所以上設けられていることを特徴とする集
積回路装置。An integrated circuit device characterized in that a bed in a package of an integrated circuit device or a semiconductor chip is provided with at least one relay point for wire bonding that connects pads in the chip and a lead frame of the package. circuit device.
JP58012262A 1983-01-27 1983-01-27 Integrated circuit device Pending JPS59138353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58012262A JPS59138353A (en) 1983-01-27 1983-01-27 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58012262A JPS59138353A (en) 1983-01-27 1983-01-27 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS59138353A true JPS59138353A (en) 1984-08-08

Family

ID=11800452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58012262A Pending JPS59138353A (en) 1983-01-27 1983-01-27 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59138353A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0289329A (en) * 1988-09-27 1990-03-29 Seiko Epson Corp Connection of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0289329A (en) * 1988-09-27 1990-03-29 Seiko Epson Corp Connection of semiconductor device

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