JPS59137994A - External memory device for electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an external memory device that is detachably attached to the main body of an electronic musical instrument.

BACKGROUND OF THE INVENTION Electronic musical instruments are sometimes provided with a removable external memory device so that settings of panel operators such as tone switches and effect switches or performance processes can be recorded. Examples of external memory devices include magnetic cards, magnetic tape, and magnetic bubble memos! J, DI3FR
Although OM and the like are known, CMOS battery backup memory (hereinafter abbreviated as CMOS memory) is particularly known as having a simpler peripheral circuit and being cheaper than other memories.

@Figure 1 and Figure 2 are diagrams showing the external appearance and internal configuration of a conventional CMOS memory 1. In Figure 1, 2 is a power pin, 3 is a chip enable pin, and 4 is an address pin and a data pin. These pins 2 to 4 are each inserted into a connector on the main body of the electronic musical instrument. Also, the second
In the figure, 5 is 0MO8-BAM, and this 0MO
8-RAM terminals Tv and Tom are a power supply terminal and a chip enable terminal, respectively. In addition, this 0MO8-
Of course, the RAM is also provided with data terminals and address terminals, but they are not shown here. This 0MO8-
几AM5 is in the enabled state, that is, when the voltage Van of ・Ll (0■) is supplied to the terminal Tom,
It becomes readable/writable, and on the other hand, 'H'L/to/
If voltage Vom is supplied to L/ (2 to 5 V), it will be in a disabled state (read/write impossible state)
becomes. 6 is a backup battery for output voltage VB, 7-
8 is a diode, 9 is a resistor, and 10 is a capacitor for stabilizing the power supply voltage. Reference numerals 11 and 12 temporarily indicate the connection states between pins 2 and 3 and the connector of the main body of the electronic musical instrument using switches.

When this 0MO8 memory 1 is inserted into the connector of the main body of the electronic musical instrument, the power supply voltage Vp (Vr>Va) output from the power supply section in the electronic musical instrument is applied via the switch 11, pin 2, and diode 8 to the 0MO8- The chip enable signal CE supplied to the terminal Tv of the AM 5 (voltage Voo) and output from the control section within the electronic musical instrument is applied to the switch 12,
is supplied via pin 3 to the terminal Tom (voltage Van
). On the other hand, when this 0MO8 memory 1 is unplugged from the connector of the electronic musical instrument, both switches 11 and 12 are turned off, and the output voltage Vss of the battery 6 is changed to the voltage Vss via the diode 7.
oo to the terminal Tma, and the voltage Woo
is supplied to the terminal ROM through the resistor 9. In addition,
As is well known, 0MO8-BAM5 is connected to the power supply voltage Voo supplied to the terminal Tv when performing read/write processing.
must be 4.5 .mu. or more, and on the other hand, if no read/write processing is performed, data can be retained with a power supply voltage Voo of approximately 2 .mu. Therefore, the voltages Vp, V
5, OV, 2,2 v are usually used as i+.

By the way, when playing an electronic musical instrument, the above-mentioned 0MO
There may be cases in which it is desired to previously store data regarding the setting states of panel operators in the 8 memory 1, insert the 0M08 memory 1 into the connector during a performance, and use the data therein immediately.

In such a case, in order to use the data in 0MO8 memory 1 in the shortest time, set the chip enable signal CE to #L in advance.
It is desirable to keep it at # level.

However, in the case of the CMOFi memory 1 described above, if the chip enable signal CF) is set to the L level in advance, the data in 0MO8-RAMS may be destroyed. The reason for this will be explained below. First, 0MO8-RA
The following characteristics are known as the characteristics of Ms.

■ When inserting 0M08 memory 1 into the connector, the specified time (
For example, the voltage Vow must be held at the 1H'' level for more than 200nse.If the voltage Vow is set to the -L# level at the same time as the voltage Voo reaches 4.5V,
Internal data will be destroyed.

■ When the voltage Voo is less than 4.5V, change the voltage Vow to #
Must be held at H level. If this condition is violated, the internal data will also be destroyed.

On the other hand, FIG. 3 shows the power supply voltage v00 (
FIG. 12 is a diagram showing changes in the actual temperature and the chip enable voltage Van (dashed line). In this case, at time 11
is the time when the switch 11 shown in FIG. 2 is turned on, and the power supply voltage Vo.

At time t, the value gradually increases due to the action of the capacitor 10, reaching 4.5■ at time t, and finally reaches 5.
v・Note that the voltage drop across the diode 8 is ignored. On the other hand, the switch 12 is turned on at time t, when a predetermined time T1 has elapsed after the switch 11 was turned on, and at this time t, the voltage Vow becomes 9L level.Here, the time T is shown in FIG. This is the time difference caused by the difference in length between pins 2 and 3 shown in Figure 2. If the CMOS memory 1 is inserted into the connector quickly, the time T will be small, and if it is inserted slowly, the time TI will be large. Become.

Therefore, 0MO8-BAM when inserted.

In order to prevent the data in 5 from being destroyed, please follow the steps described in ■ and ■.
As is clear from the characteristics of time t, time 1. later than, and at time 1. The time difference T between and 1m is 200
Must be greater than n5ee, but 0
If MO8 memory 1 is inserted into the connector rapidly, or if MO8 memory 1 is not inserted properly and is inserted and removed several times within a short period of time, the above conditions will not be satisfied. A case occurs, in this case, 0MO8
-The data in the RAMs will be destroyed. -The time t4 is the time when the switch 12 is turned off, and the time tlft
This is the time when the switch 11 is turned off, and in this case (that is, when removing the CMO8 memory l), the power supply voltage W
When oo is below 4.5V, does the voltage vol always sing? level and therefore the data will not be destroyed.

In this way, the conventional 0M08 shown in FIGS. 1 and 2
If the memory l holds the signal OB at the q level, there is a risk that the data in 0MO8-ordinary person M5 will be destroyed at the time of insertion. Therefore, when plugging in, the terminal Tom of 0MO8-AMs should be
It is possible to insert a capacitor between the ground and ground.However, if this capacitor is inserted, the rise of the rolled rolling force VOI at the time of extraction will be delayed, and as a result, when the power supply voltage Voo becomes 4.5V or less, the voltage There are cases where the VOI is at the red L# level, and in this case, the data is destroyed.As mentioned above, in the conventional CMOS memory 1, one signal CL is held at the 1L# level in advance. Therefore, the following measures are generally used.

(1) Normally, the signal CB is held at the 1H# level, and only when performing read/write processing of 0MO8-RAM5, the signal CI is set to the 1L# level using a manual switch9 (1) QMO8 memory 1 is inserted Put a lid on the area where the
Further, a switch 14 (see Figure 4) is provided which is turned on when the lid is open and turned off when it is closed. Then, as shown in Figure @4, the signal Ck1 is configured to be at the 1H'' level when the lid is in the open state, and the signal C13 is at the tL* level when the lid is in the closed state. By doing this, 0MO8 memory 1
The signal CE becomes 1 only when the connector is inserted into the connector and the lid is closed.
Therefore, data destruction can be prevented.

However, according to the means (:) or (■) described above, some operation is required after inserting the 0MO8 memory 1, and therefore the data cannot be used at the same time as the insertion. The circuit for controlling the signal CE becomes complicated, leading to an increase in cost.

In view of the above circumstances, the present invention has been devised as an external memory device for an electronic musical instrument, which allows the internal data to be used immediately by simply plugging it into the connector of the electronic musical instrument body, and which does not require any control of the chip enable signal Cg. It provides
Storage means (for example, 0MO8-RAM5 in FIG.
) is provided inside the memory device with a control means for disabling the storage means until a certain period of time has elapsed from the time when the power supply voltage supplied to the memory device reaches a specified voltage (4.5V in FIG. 2).・The following is a diagram showing the configuration of a memory 20 (external memory device) according to an embodiment of the present invention with reference to the drawings.
Components corresponding to those in the figure are given the same reference numerals.

In FIG. 5, voltage Vp is a power supply voltage output from one source of the electronic musical instrument body, and this voltage VP is C
Voltage higher than the rated power supply voltage 5V of A408-RAM5 (
For example, 12v) is used. This voltage VP is supplied to the power supply pin 2 via the switch 11. A series circuit of a capacitor 21 and a resistor 22, 23 is inserted between the 0 pin 2 and the ground. Connected to one end. The other end of the resistor 24 has a Zener voltage of 5V.
The anode of the Zener diode 25 is grounded, and the cathode of the diode 8 is connected to the cathode of the Zener diode 25 and the anode of the diode 8.
- Connected to the power supply terminal T of RAM5. Also, 0
The collector of the transistor 27 is connected to the chip enable terminal Tom of MO8-RAM5, and the transistor 27
The emitter of the transistor 22 and the base of the resistor 22 and 23 are grounded, and the resistance values of the resistors 22 and 23 are set so that the transistor 27 is turned on when the voltage at the pin 2 reaches approximately 11cm. Note that the connections of the battery 6, diode 7, and resistor 9 are the same as in FIG.

Next, the operation of the above-mentioned CMOS memory 20 when inserted into and removed from the connector will be explained with reference to the waveform factor shown as the sixth factor. Note that, contrary to the following explanation, the diode 7.
8 voltage drop shall be ignored. Each of the curves shown in FIG.
Cathode voltage VD, voltage Voo applied to the power supply terminal Tv of ICMO8-RAM5, CMO8=RAM
5 (showing the change in the voltage Voi+ applied to the Of-z enable terminal Tom) First, when the 0M08 memory 20 is removed from the connector of the main body of the electronic musical instrument, the voltage Vo.

becomes voltage 2.2■ of battery 6, and transistor 2
7 is in the off state, the voltage Vow is also 2.2
It becomes V (-H" level).

Next, at time t shown in the figure, the 0MO8 memory 20
is inserted into the connector of the main body of the electronic musical instrument, and therefore, when the switch 11 is turned on, the voltage Vm gradually rises from Ov due to the action of the capacitor 21, and accordingly, the voltage VD also gradually rises. Then, when the voltage Vn exceeds 2.2■, the diode 7 is reverse biased, so that the voltage Woo becomes the same as the voltage Vn from now on. When the voltage (2) further increases and reaches 5 (5), voltages Vn and Voo are both maintained at 5 (5) by the action of the Zener diode 25. Furthermore, at this point, the transistor 27 is still in the off state, so the voltage Vow is also 5. When the voltage (2) further increases and reaches 11V (time ts), the transistor 27 is turned on. As a result, the voltage Vow becomes 0■, and henceforth CMO8-几AM
5 can be read/written.

The above is the operation of the 0MO8 memory 20 at the time of insertion. In the above operation, if the time when the voltage Woo reaches 4.5■ is 11 (Fig. 6), then before this time t, that is, when the voltage Voo is 4.5■ or less, the voltage V
ow is maintained at 1H level. Also, at this time 1. The time T from t to the time t when the voltage Vow becomes Ov is the time from 4.5V to 11V. In other words, this 0MO8 memory 20 satisfies both conditions (1) and (2) for not destroying the data in the 0MO8-RAM 5 when inserted.

Next, the operation at the time of extraction will be explained. Now, at time t4 shown in FIG. 6, the 0MO8 memory 20 is removed from the connector, and the switch 11 is turned off. From then on, the voltage 7 gradually decreases to Ov due to the action of the capacitor 21. From time t4 Time slightly later 1. When the voltage Vm becomes 11V or less, the transistor 27 is cut off. At this time, the voltage Voo is still at 5V, so the magnetic pressure Van becomes 5V ("H" level) due to the cut-off of the transistor 27. When the voltage Voo further decreases and reaches 5V, the voltage VD , V
oo, Voi+ The pressure VA is lowered along with the bottom. Then, when the voltage reaches 2.2V, the diode 7 becomes forward biased, and thereafter the voltage Voo.

Vow are both held at 2.2v, and the voltage VA
.

VD further falls and reaches ov.

The above is the operation during extraction. In the above operation, when the voltage Voo becomes 4.5V or less (after time t6 shown in FIG. 6), the voltage vol is at the song level, and therefore the data in 0MO8-RAM5 is destroyed. There's no fear at all.

In this way, the 0MO8 memory 2° shown in FIG. 5 can set the chip enable voltage Vow to ov just by plugging it into the connector of the main body of the electronic musical instrument.
As soon as it is inserted, data in 0MO8-AM5 can be used. Furthermore, as is clear from the fact that the chip enable signal CE in FIG. 2 is not used,
There is no need to control the chip enable signal 1 on the electronic musical instrument side. Furthermore, when inserting or removing the
There is no risk that the data in MO8-B and AMS will be destroyed.In addition, in the above-mentioned embodiment, 0MO is used as the storage means.
Although an 8-liter AM5 is used, this invention is applicable to other types of RAs.
Of course, it is also possible to use M.

Furthermore, if the address terminals (not shown) of the 0MO8-RAM5 in the above-described embodiment become open, the internal data is not guaranteed.

As for the power, the address terminals of 0MO8-RAM5 are 0M.
It is necessary to ground the O8 memory 20H via a resistor.

Next, FIG. 7 is a block diagram showing an example of an electronic musical instrument using the 0MO8 memory 20 described above.

In this case, the key switch circuit 30 detects the on/off state of each key on the keyboard (path shown) based on the output of the key switch provided corresponding to each key, and detects the on/off state of the key that is currently in the on state. Key code KC to easy f (No. 1 formation [3
1 and the performance recording/playback control circuit 32. The panel setting unit 33 is a circuit that outputs channel data FD corresponding to the operation status of each operation switch (tone setting switch, effect setting switch, etc.) on the operation panel surface, and outputs 1
．． The generated panel data PD is supplied to the musical tone signal forming section 31 and the preset control circuit 34. Musical tone signal forming section 31
forms a musical tone signal having a pitch corresponding to the key code KC and a musical tone mode (timbre, effect, etc.) corresponding to the panel data PD, and outputs it to the sound system 35. Further, when the preset switch on the operation panel is operated, a musical tone signal having a musical tone mode corresponding to the preset data P8D output from the preset l1iQ control circuit 34 is formed and output.

On the other hand, when the C'M08 memory 20 is inserted into the connector, the connector circuit 36 detects this and outputs a signal P to the external memory R, /W (read/write) control circuit 37. External memory/W fllJ #Circuit 37 is
Upon receiving this signal P, it outputs a signal Q to the preset control circuit 34. The preset control circuit 34 receives this signal Q, reads out the panel data in the 0MO8-RAM5 of the CMOS memory 20, and outputs it to the tone signal forming section 31 as preset data P8D. Thereby, the musical tone signal forming section 31 forms and outputs a musical tone signal based on the panel data in CM08-RAMS. The performance recording/playback control circuit 32 sequentially records the key codes KC output from the key switch circuit 30 in the internal AM, and sequentially records the recorded key codes KC as musical tones based on instructions from the operation switches on the operation panel. Output to signal forming section 31 Also, under the control of external memo 9Ey'W control circuit 37, the key codes recorded in 0MO8-RAMS are successively outputted to tone signal forming section 31.

In this case, the musical tone signal forming section 31 forms and outputs a musical tone signal based on the key code output from the performance recording/playback control circuit 32. Note that the output of the panel data read from the 0MO8-RAM5 to the musical tone signal forming section 31 may be controlled by a separately provided switch.

As explained above, according to the present invention, the storage means is disabled for a certain period of time after the power supply voltage supplied to the storage means (for example, 0MO8-RAM) exceeds the specified voltage. Since a control means (for example, a circuit consisting of transistor 27, resistor 22, 23, and capacitor 21 in FIG. 5) is provided inside the memory device, the external memory device according to the present invention can be easily inserted into the connector of the main body of the electronic musical instrument. This has the advantage that internal data can be used immediately, and there is also the advantage that there is no need to provide a control circuit for controlling the voltage of the chip enable terminal in the main body of the electronic musical instrument.

[Brief explanation of the drawing]

Figures 1 and 2 are an external view and internal configuration of a conventional 0M08 memory, respectively, Figure 3 is a waveform diagram for explaining the characteristics of the CM08 memory, and Figure 4 is a waveform diagram for explaining the characteristics of the CM08 memory. FIG. 5 is a circuit diagram showing an example of a circuit for controlling the applied voltage. FIG. 5 is a circuit diagram showing the configuration of an embodiment of the invention. FIG. 6 is a waveform diagram for explaining the operation of the embodiment. , @7 is a block diagram showing an example of the configuration of an electronic musical instrument in which the CMOS memory according to the same embodiment is used.・
...0MO8-RAM (storage means), 6...
Backup battery, 7, 8...diode,
21... Capacitor, 9.22, 23, 24.
...Resistor, 25 ... Zener diode,
27...Transistor. Applicant: Nippon Musical Instruments Manufacturing Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 v Figure 5 0-

Claims (1)

[Claims] An external memory device configured to be detachably attached to the main body of an electronic musical instrument, which is driven by a storage means, a backup battery, a power input terminal, and a power supply supplied from the electronic musical instrument main body to the power input terminal, and has a time constant. a power supply circuit having a circuit; when the output voltage of the power supply circuit is below a predetermined value, the output voltage of the backup battery is supplied to the storage means; when the output voltage of the power supply circuit is below a predetermined value, the output voltage of the power supply circuit is supplied to the storage means; The switching means supplied to the storage means and the storage means are disabled for a period of time from the time when the 1 m source voltage supplied to the storage means gradually increases and reaches a specified voltage until a certain period of time has elapsed. An external memory device for an electronic musical instrument, comprising a control means.