JPH08240748A - Memory circuit for optical connector - Google Patents

Abstract

PURPOSE: To provide the memory for an optical connector capable of reducing the number of components at a management side without incurring inconvenience of an error, etc., even an EEPROM is used. CONSTITUTION: This circuit constitutes a rectifier circuit, when a signal synthesized so that the voltage of a baseline coincides with the voltage of a VCC signal and the voltage of a top line coincides with the sum voltage between the voltage of the VCC signal and the voltage of the top line of an SCL signal is inputted from a T1 terminal to the circuit, the VCC voltage and the SCL voltage are separated and exracted from this signal to be respectively supplied to the VCC terminal and the SCL terminal of a memory IDM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit built in an optical connector at the end of an optical cable, and particularly to an EEPR.
The present invention relates to a memory circuit for an optical connector using an OM.

[0002]

2. Description of the Related Art As a real-time communication equipment management system for optical fiber networks, a memory storing equipment information such as fiber type, accommodating unit number, cable number, etc. relating to an optical cable which is a line equipment is provided in an optical connector at the end of each optical cable. In addition to being installed, a track construction system in which a monitoring device is installed at each base to which each end of these optical cables is connected
An advanced support system for maintenance has been proposed.

According to this type of system, the monitoring device of each site accesses the memory of each optical connector connected to the site, so that the facility information of each optical fiber laid via the site can be obtained. Read out. Then, the read equipment information is transferred into the station via a dedicated communication line, and the line equipment is managed and maintained in the station.

Here, a schematic structure of the peripheral portion of the optical connector will be described with reference to FIG. In this figure, 1
Is a printed circuit board, and a large number of adapters 1a, 1a, ... Are provided on the front and back surfaces. Here, each adapter 1a provided on the front surface is connected to the adapter provided on the back surface at the same position as this, and each optical connector 2a of the two optical cables 2 is connected to each of the pair of front and back adapters. By doing so, the connection between the two optical cables is made.

Further, jacks J, J, ... Are provided near each adapter 1a on the printed circuit board 1.
When the optical connector 2a is connected to the adapter 1a, the input / output lead terminals (not shown) of the memory circuit IDM mounted on the optical connector 2a are connected to the jacks J, J, of the adapter 1a.
It is designed to be connected to ... The memory IDM
As a method of mounting the optical connector, a method of adhering to the housing of the optical connector or a method of incorporating the housing of the optical connector 2a into the housing so that the housing is sufficiently large is adopted.

An access control circuit 3 accesses the memory IDM of the optical connector 2a connected to each adapter 1a of the printed board 1 through the wiring formed on the printed board 1 and the jacks J, J, .... . 4 is a CPU (central processing unit) that controls the entire monitoring device
Under the control of the host computer in the maintenance station, the above optical connectors 2a are accessed via the access control circuit 3.
The memory IDM installed in the optical disk 2 is accessed to supply equipment information regarding each optical cable 2 to a host computer (not shown).

As described above, the optical connectors 2a at the ends of the optical cables 2 are respectively equipped with the memory IDMs, and these memory IDMs contain information necessary for managing and maintaining the line facilities ( The identification information of the optical cable 2 corresponding to each is stored. As these memory IDMs, those using a resistor array / fuse parallel circuit have been conventionally known.

In the resistor array / fuse parallel circuit,
FIG. 11 shows a circuit corresponding to 1-bit information. The circuit shown in this figure is composed of a resistor to which a predetermined voltage V is applied and a fuse connected in parallel to this resistor. Depending on the state of the fuse (“connected” or “broken”), 1-bit information is stored. Hold. A resistor array / fuse parallel circuit is provided with a plurality of such circuits. Usually, about 10 of the above circuits are provided. This is because the optical fiber memory used for the connection device on the subscriber side usually requires the ability to discriminate the number of hearts of about 2 ¹⁰ (that is, 4096).

[0009]

By the way, since the memory IDM composed of the resistance array / fuse parallel circuit requires the configuration shown in FIG. 11 for each bit, it is difficult to increase the memory capacity, and each optical fiber 2 can be formed. It is difficult to add new functions other than identification. By the way, in the resistance array / fuse parallel circuit, the fuse state (“connection”)
Alternatively, if the fuse that holds the information corresponding to the "cut" is held and the fuse holding the information to be changed is in the "connected" state, the held information can be changed by blowing the fuse. . However, it is difficult to perform this fusing without removing the optical connector 2a from the substrate 1. That is, there is a problem in that the optical cable 2 in which the fuse is blown is temporarily disconnected from the communication network. Further, there is a drawback in that the held information cannot be changed to arbitrary information because the fuse once cut cannot be put in the “connected” state.

From the above, as the memory IDM,
It has become common to use EEPROM (electrically erasable programmable read-only memory). However, when using the EEPROM, memory control terminals (VCC, SCL (synchronization clock), SDA
Since (serial data) and GND) have four or more terminals, there is a problem that the number of parts of the access control circuit 3 (see FIG. 10) increases. The present invention has been made in view of the above-mentioned circumstances, and even if an EEPROM is used, it is possible to reduce the number of parts on the management system side without incurring inconvenience such as an error and the like. The purpose is to provide.

[0011]

An optical connector memory circuit according to claim 1 is an optical connector memory circuit mounted on an optical connector at an end of an optical cable, and stores information unique to the optical cable. Power supply terminal to which power supply voltage signal is input, ground terminal to which ground voltage signal is input, clock terminal to which synchronization pulse signal is input, and read / write
A memory having a data input / output terminal for inputting / outputting information for a write operation, and the power supply terminal and the clock terminal are connected, and a composite signal of the power supply voltage signal and the synchronizing pulse signal is input. A second terminal connected to the first terminal and the ground terminal for receiving the ground voltage signal
And a third terminal connected to the data input / output terminal for inputting / outputting information for the read / write operation, and the power supply voltage signal from the combined signal input to the first terminal. It is characterized by further comprising: a separation / extraction means for separating and extracting the synchronizing pulse signal and inputting to the power supply terminal and the clock terminal, respectively.

An optical connector memory circuit according to a second aspect of the present invention is the optical connector memory circuit according to the first aspect, wherein the synthesized signal has a baseline voltage that matches the voltage of the power supply voltage signal, and The top line voltage is generated so as to match the sum voltage of the power supply voltage signal and the top line voltage of the synchronizing pulse signal, and the separation and extraction means is a rectifier circuit using a diode. It has a feature.

An optical connector memory circuit according to a third aspect of the present invention is the optical connector memory circuit according to the second aspect, wherein the separation and extraction means is based on the combined signal and the ground voltage signal. A three-terminal regulator, a comparator that outputs a synchronizing pulse signal based on the combined signal, the power supply voltage signal, and the ground voltage signal, and one end connected to the output end of the three-terminal regulator and the other end. Is provided with a capacitor to which a ground voltage signal is applied, and the three-terminal regulator and the comparator are each composed of an IC chip. An optical connector memory circuit according to a fourth aspect is the optical connector memory circuit according to the third aspect, characterized in that the three-terminal regulator and the comparator are composed of a resistor, a transistor, and a diode.

An optical connector memory circuit according to a fifth aspect of the present invention is the optical connector memory circuit according to the first aspect, wherein the synthesized signal has a baseline voltage that matches the voltage of the ground voltage signal, and The top line voltage is generated so as to match the sum voltage of the top line voltage of the power supply voltage signal and the top line voltage of the synchronizing pulse signal, and the separation and extraction means includes a diode and a capacitor. It has a feature.

[0015]

According to the above construction, when the composite signal of the power supply voltage signal and the synchronizing pulse signal is input from the first terminal, the separation / extracting means extracts the power supply voltage signal and the synchronizing pulse signal from the composite signal. Separate and extract, and input each to the power supply terminal and clock terminal of the memory. A ground voltage signal from the second terminal and information for read / write operation from the third terminal are input (output) to the ground terminal and the input / output terminal of the memory, respectively.
That is, the memory operates based on signals (information) input from the first to third terminals (three terminals).

[0016]

Embodiments of the present invention will be described below with reference to the drawings. As will be described later, the embodiment of the present invention is divided into first to fourth embodiments, but the basic items common to the memory circuits according to the embodiments are the VCC terminal (power supply terminal) and the SCL terminal (clock terminal). , SDA terminal (data input / output terminal), and VSS terminal (ground terminal)
Using an EEPROM (electrically erasable programmable read-only memory) as a memory,
One of the points is that the VCC terminal and the SCL terminal of the EEPROM are combined so that the entire memory circuit has three terminals.

First, a first embodiment of the present invention made on the basis of the above basic matters will be described with reference to FIG. 1 is a circuit diagram showing a configuration of an optical connector memory circuit according to a first embodiment of the present invention. As shown in FIG. 1, the optical connector memory circuit according to the present embodiment has a VC
EE having four terminals of C, SCL, SDA, and VSS
It has a PROM (eg, XICOR X24C00) as a memory IDM. This memory IDM has three terminals T1 to T3 (first to first) through a circuit having the illustrated configuration.
Third terminal).

In the optical connector memory circuit according to the present embodiment, the baseline voltage is the VCC signal (power supply voltage signal).
Of the VCC signal and the sum of the voltage of the VCC signal and the voltage of the SCL signal (pulse signal for synchronization) on the top line, and a combined signal is generated. It is premised on inputting via T1. This also applies to the second and third embodiments described later.

The terminals T2 and T3 are connected to the VS of the memory IDM via the ground line L4 and the data line L3, respectively.
It is directly connected to the S terminal and the SDA terminal. Also,
The terminal T1 is connected through a power line L1 to which the collector and emitter of the npn-type transistor TR1 are connected,
The capacitor C1 (0.01 μF) and the resistor R4 (1 kΩ) are connected to the VCC terminal of the memory IDM.
S of the memory IDM via the clock line L2 provided with
It is connected to the CL terminal.

In the clock line L2, the latter stage of the capacitor C1 and the resistor R4 (that is, the memory IDM).
Connection points P1 and P2 are provided on the SCL terminal side of each of the terminals) and are respectively connected to the ground line L4 via the diode D2 and the resistor R (470 kΩ) in the reverse direction. Further, connection points P3 and P4 are sequentially provided on the ground line L4 toward the VSS terminal side of the memory IDM, and these connection points P3 and P4 are respectively connected to the forward voltage regulator diode D3 (reverse breakdown voltage). Is connected to the power supply line L1 via a resistor R5 (2 kΩ). However, the cathode of the constant voltage diode D3 is connected to the base of the transistor TR1 so that the power line L
Connected to 1. A resistor R17 (270Ω) is connected in parallel between the collector and the base of the transistor TR1.

In the above configuration, when a signal obtained by combining the VCC signal and the SCL signal to the terminal T1 and a VSS signal (also referred to as a GND signal) are applied to the terminal T1 from the outside (for example, the access control circuit 3 in FIG. 10), the memory IDM
VCC signal to the VCC terminal and SCL to the SCL terminal
The signal and the VSS signal are supplied to the VSS terminal, and the memory IDM becomes operable. In this state, the terminal T3
SD consisting of address data and actual data via
When the A signal (information for read / write operation) is input, data is read from an address corresponding to the address data of the memory IDM, or actual data is written to the same address.

FIG. 2 shows the memory IDMs VCC, SCL,
It is a figure which shows the input signal waveform to a VSS terminal, and the input / output signal waveform in terminal SDA. The waveform shown in this figure was obtained by experiment. As shown in this figure, the VCC signal and the SCL signal are properly separated and input to the VCC and SCL terminals, respectively. In this figure (the same applies to FIGS. 4, 5, 7, and 9), the minimum scale unit in the time axis direction is 100 μs.

As described above, since the proper VCC signal and SCL signal are obtained, the first half FA of the SDA signal is obtained.
The address selection is normally performed, and the actual data represented by the latter half portion BA is normally written / read. The pulse rise time tR of the SCL signal is 9
It was 8 ns, and the fall time tF was 308 ns. However, the pulse rise time tR and the pulse fall time tF can be improved by making the parameters of the circuit components more appropriate. Further, the separated VCC signal has a ripple of about 0.2 V, and the maximum current consumption is 29.2 mA.
Met.

As described above, according to the optical connector memory circuit of the first embodiment of the present invention, the three terminals T are provided.
The memory IDM composed of the EEPROM can be driven only by 1 to T3. That is, it is possible to reduce the number of components outside the optical connector memory circuit. Further, the above-mentioned optical circuit for the optical connector can be configured by seven circuit elements except the memory IDM. That is, the circuit configuration can be simplified.

Next, the second embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 3 is a circuit diagram showing a configuration of an optical connector memory circuit according to a second embodiment of the present invention,
In this figure, parts that are the same as those in FIG. 1 are assigned the same reference numerals and explanations thereof are omitted. The optical connector memory circuit shown in this figure is largely different from the optical connector memory circuit shown in FIG. 1 in that a VCC signal and an SCL signal are separated by using a three-terminal regulator RG and a comparator CP. is there. These three-terminal regulator RG and comparator CP are composed of a commercially available IC chip.

In the optical connector memory circuit shown in FIG. 3,
The terminal T1 is connected to the VCC terminal of the memory IDM via a power supply line L1 to which a three-terminal regulator RG is connected, and a clock line L2 in which a resistor R7 (39 kΩ) and a comparator CP are inserted. Is connected to the SCL terminal of the memory IDM. The GND terminal of the three-terminal regulator RG is connected to the ground line L4, and the signal (VCC signal and S signal supplied from the terminal T1 side is supplied.
(Combined signal with CL signal) and GN applied to GND terminal
A signal of constant voltage (VCC signal) is output based on the potential difference of the D signal. The comparator CP has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal is on the terminal T1 side, and the output terminal is the SC of the memory IDM.
It is inserted in the clock line L2 so as to be on the L terminal side.

Further, in the clock line L2, the resistor R7
At a connection point P5 provided in the subsequent stage and in the previous stage of the comparator CP, a ground line L4 is provided via a resistor R8 (24 kΩ).
Is connected. Further, a connection point P6 provided in the latter stage of the three-terminal regulator RG in the power supply line L1 is connected to the ground line L4 via a resistor R9 (8.2 kΩ) and a resistor R10 (24 kΩ). The resistor R9,
The connection point P7 between R10 is connected to the inverting input terminal of the comparator CP. Further, a connection point P8 is provided between the output terminal of the comparator CP and the SCL terminal of the memory IDM.
Is provided, and a connection point P9 between this connection point P8 and the power supply line L1
(After the connection point P6) is a resistor R11 (2.7 kΩ)
Connected through.

The waveform obtained at each terminal of the memory IDM with such a configuration will be described with reference to FIG. FIG. 4 is obtained by an experiment using the memory circuit for an optical connector according to this embodiment. As shown in this figure, the VCC signal and the SCL signal are separated and input to the VCC and SCL terminals, respectively. In addition, SC
The pulse rise time tR of the L signal was 330 ns and the fall time tF was 30 ns. However,
By making the parameters of the circuit components more appropriate, it is possible to improve the pulse rise time tR and the pulse fall time tF. The maximum current consumption was 5 mA.

By the way, as is clear from the figure, noise is generated in the separated VCC signal. this is,
The comparator CP normally compares constant (non-pulse) signals, and is a phenomenon that occurs because its response characteristic is too good. That is, the comparator CP
However, the transient response to the voltage change of the pulse signal does not occur, resulting in noise such as ripples. Therefore, a normal operation (here, a read operation) is not performed, an SDA error occurs, and as shown in FIG.
The latter half BA of the signal may become an invalid signal.

In order to remove the above noise, in FIG. 3, a point on the power supply line L1 which is a subsequent stage of the three-terminal regulator RG and a previous stage of the connection point P6 and a ground line L4 are connected to a capacitor C2 (0.1 μF). The circuit may be configured to be connected via. In this case, the response characteristic of the comparator CP was deteriorated, and a signal waveform as shown in FIG. 5, that is, a signal waveform from which noise was removed was obtained.

As described above, according to the optical connector memory circuit of the second embodiment of the present invention, the memory IDM can be driven by only the three terminals T1 to T3, as in the first embodiment. The circuit can be configured with a simple configuration. Furthermore, according to the present embodiment, it is possible to completely remove the ripple of the VCC signal that was slightly present in the first embodiment. Moreover, the maximum current consumption can be made extremely small.

Next, the third embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 6 is a circuit diagram showing a configuration of an optical connector memory circuit according to a third embodiment of the present invention.
In this figure, parts that are the same as those in FIG. 3 are assigned the same reference numerals and explanations thereof are omitted. The optical connector memory circuit shown in this figure is greatly different from the optical connector memory circuit shown in FIG. 3 in that the three-terminal regulator RG and the comparator CP are not composed of an IC chip, but a capacitor,
This is a point that it is configured by using a resistor, a transistor, and a constant voltage diode.

In the optical connector memory circuit shown in FIG.
An npn-type transistor TR2, whose collector is on the terminal T1 side and whose emitter is on the VCC terminal side of the memory IDM, is inserted on the power supply line L1. This transistor TR2
The base of is connected to the ground line L4 through a reverse voltage regulator diode D5 (reverse breakdown voltage is 5.6V). A resistor R16 (270Ω) is connected in parallel between the collector and the base of the transistor TR2.

Further, in the power supply line L1, the connection point P10 provided in the preceding stage of the transistor TR2 has a resistor R12.
(39 kΩ) and resistor R13 (24 kΩ)
It is connected to the ground line L4. The resistor R12 is a circuit element inserted in the clock line L2, and is connected to the clock line L2.
An npn-type transistor TR3 and a pnp-type transistor TR5 are inserted in 2 after the resistor R12. The resistor R12 is connected to the base of the transistor TR3, and the collector of the transistor TR3 is connected to the base of the transistor TR5. And
The collector of the transistor TR5 is the SC of the memory IDM.
It is connected to the L terminal.

The collector of the transistor TR3 is connected to the connection point P11 of the power line L1 via the resistor R14 (1 kΩ).
It is connected to (after the transistor TR2). On the other hand, the emitter of the transistor TR3 is the resistor R15.
It is connected to the ground line L4 via (3.3 kΩ). Np provided to face the transistor TR3
The collector of the n-type transistor TR4 has a connection point P11.
It is connected to a connection point P12 provided in the subsequent stage, and the emitter is connected to the ground line L4 via the resistor R15.

The base of the transistor TR4 has a reverse voltage regulator diode D4 (reverse breakdown voltage of 3.9).
V) and the resistance R
It is connected to the connection point P19 provided in the subsequent stage of the connection point P12 in the power supply line L1 via 18 (270Ω). Further, the emitter of the transistor TR5 has a connection point P provided at a subsequent stage of the connection point P19 in the power supply line L1.
20 is connected to the collector of the resistor R6 (1.
8 kΩ) and is also connected to the ground line L4.

Waveforms obtained at each terminal of the memory IDM with such a configuration will be described with reference to FIG. FIG. 7 is obtained by an experiment using the memory circuit for an optical connector according to this embodiment. As shown in this figure, the VCC signal and the SCL signal are properly separated,
They are input to the VCC terminal and the SCL terminal, respectively.
As described above, since the proper VCC signal and SCL signal are obtained, the address selection by the first half FA of the SDA signal is normally performed, and the writing / reading of the actual data represented by the latter half BA is normally performed. Be seen. In addition, S
The pulse rise time tR of the CL signal was 90 ns and the fall time tF was 119 ns. Also,
The separated VCC signal had a ripple of about 0.2 V, and the maximum current consumption was 36.2 mA.

As described above, according to the memory circuit for an optical connector of the third embodiment of the present invention, the memory IDM can be driven only by the three terminals T1 to T3, as in the first and second embodiments. Is. Furthermore, according to the optical connector memory circuit of this embodiment, the pulse rise time t
The F and pulse fall times tR can be shortened as compared with those in the first and second embodiments.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 8 is a circuit diagram showing the configuration of an optical connector memory circuit according to the fourth embodiment of the present invention.
In this figure, parts that are the same as those in FIG. 3 are assigned the same reference numerals and explanations thereof are omitted. In the memory circuit for optical connector shown in this figure, the voltage of the baseline matches the voltage of the VSS signal, and the voltage of the top line is the sum voltage of the top line voltage of the VCC signal and the top line voltage of the SCL signal. It is premised that a combined signal is generated so as to match with, and this combined signal is input from the terminal T1, and a diode and a smoothing capacitor are used to separate the combined signal supplied from the terminal T1 into a VCC signal and an SCL signal. I am trying to do it.

In the memory circuit for optical connector shown in FIG.
A diode D1 whose anode is on the terminal T1 side and a three-terminal regulator RG connected to the cathode side of this diode D1 are interposed on the power supply line L1. Also,
The power supply line L1 on the anode side of the diode D1 is connected in series with a resistor R3 (6.8 kΩ) and a resistor R2 (4.7 kΩ).
kΩ) to the ground line L4.

Further, the power source line L1 on the cathode side of the diode D1 is connected to the ground line L4 via a capacitor C3 (1 μF) that operates as a smoothing capacitor. In addition, in the power supply line L1, the three-terminal regulator R
Connection point P20 between G and the VCC terminal of the memory IDM
Is connected to the ground line L via the capacitor C4 (0.1 μF).
4 is connected.

Further, the optical connector memory circuit according to the present embodiment has a CMOS (complementary metal oxide se).
AND gate G by logic IC such as miconductor)
T is provided, one input terminal of the AND gate GT is at a connection point P21 between the connection point P20 and the capacitor C2, and the other input terminal is at a resistance R3 and a resistance R.
At the connection point P22 between the output terminal and the memory IDM
Is connected to the SCL terminal. The data line L3 and the ground line L4 are connected via a resistor R1 (100 kΩ).

An AND gate G using a logic IC
T is inserted because the voltage of the input signal is "H" level when the voltage is equal to or higher than a predetermined threshold value, and "L" level when the voltage is less than the threshold value.
This is because the pulse fall time tR can be greatly shortened. Also, CMOS is used for other TT
This is because power consumption can be suppressed as compared with L, ECL, and the like.

Waveforms obtained at each terminal of the memory IDM with such a configuration will be described with reference to FIG. FIG. 9 is obtained by an experiment using the optical connector memory circuit according to the present embodiment. As shown in this figure, the VCC signal and the SCL signal are properly separated,
They are input to the VCC terminal and the SCL terminal, respectively.
As described above, since the proper VCC signal and SCL signal are obtained, the address selection by the first half FA of the SDA signal is normally performed, and the writing / reading of the actual data represented by the latter half BA is normally performed. . In addition, SCL
The pulse rise time tR of the signal is 10 ns or less, the fall time tF is 10 ns or less, and the maximum current consumption is 4 mA.
Met.

As described above, according to the memory circuit for an optical connector according to the fourth embodiment of the present invention, as in the first to third embodiments, the memory ID is formed only by the three terminals T1 to T3.
M can be driven. In addition, the circuit can have a simple structure. Further, no ripple occurs in the VCC signal. Also, the pulse rise time tF,
The pulse fall time tR can be shortened significantly. Furthermore, the maximum current consumption can be made extremely small.

[0046]

As described above, according to the present invention,
When the composite signal of the power supply voltage signal and the synchronizing pulse signal is input from the first terminal, the separating / extracting means separates and extracts the power supply voltage signal and the synchronizing pulse signal from the composite signal, and respectively extracts the power supply of the memory. Input to pin and clock pin. A ground voltage signal from the second terminal and information for read / write operation from the third terminal are input to the ground terminal and the input / output terminal of the memory, respectively. That is, the memory operates based on signals / information input from the first to third terminals (three terminals). Therefore, even if an EEPROM having at least four terminals is used as a memory, the terminals to which a signal is input from the outside are the first to third terminals (three terminals), so that inconveniences such as errors are caused. There is an effect that the number of parts of the external management system can be reduced without being invited.

Further, the effect can be obtained with a simple structure (claims 2, 3 and 5). Furthermore, the circuit can be configured with only basic circuit elements (claim 2,
4). Further, no ripple occurs in the power supply voltage signal separated and extracted from the combined signal (claims 3 and 5). Further, the pulse rise time tF and the pulse fall time tR can be greatly shortened (claim 5).

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an optical connector memory circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a waveform obtained by the same circuit.

FIG. 3 is a circuit diagram showing a configuration of an optical connector memory circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of a waveform obtained by the same circuit.

FIG. 5 is a diagram showing an example of a waveform obtained when a capacitor C2 is added to the same circuit.

FIG. 6 is a circuit diagram showing a configuration of an optical connector memory circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram showing an example of a waveform obtained by the same circuit.

FIG. 8 is a circuit diagram showing a configuration of an optical connector memory circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing an example of a waveform obtained by the same circuit.

FIG. 10 is an optical connector 2a in a general monitoring device.
It is a figure which shows schematic structure of a periphery.

FIG. 11 is a circuit diagram showing a partial configuration of a memory using a resistor array / fuse parallel.

[Explanation of symbols]

C1 to C3 ... Capacitor, CP ... Comparator, D
1, D2 ... Diode, D3 to D5 ... Constant voltage diode, IDM ... Memory, L1 ... Power line, L2 ... Clock line, L3 ... Data line, L4 ... Ground line, P1
P22 ... connection point, R, R1 to R17 ... resistance, RG ...
... 3-terminal regulator, T1 to T3 ... terminals (first to third terminals), TR1 to TR5 ... transistors

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuya Yamashita 1-1-6, Saiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. A memory circuit for an optical connector mounted on an optical connector at an end of an optical cable, wherein information specific to the optical cable is stored and a power supply terminal to which a power supply voltage signal is input and a ground voltage signal are input. A memory having a ground terminal, a clock terminal to which a synchronizing pulse signal is input, and a data input / output terminal to / from which information for read / write operation is input / output; and a memory connected to the power supply terminal and the clock terminal, A first terminal to which a composite signal of a power supply voltage signal and the synchronizing pulse signal is input, a second terminal connected to the ground terminal and to which the ground voltage signal is input, and the data input / output terminal A third terminal connected to input / output information for the read / write operation; and the power supply voltage signal from the composite signal input to the first terminal And a pulse signal period separates and extracts, respectively the power supply terminal and said optical connector for memory circuits, characterized by comprising a separation extraction means to be input to the clock terminal. 2. The combined signal has a baseline voltage that matches the voltage of the power supply voltage signal, and a top line voltage that is the voltage of the power supply voltage signal and a voltage of the top line of the synchronization pulse signal. 2. The memory circuit for an optical connector according to claim 1, wherein the separation / extraction means is a rectifier circuit using a diode. 3. The three-terminal regulator that outputs the power supply voltage signal based on the combined signal and the ground voltage signal; and the separation and extraction means, based on the combined signal, the power supply voltage signal, and the ground voltage signal. A comparator for outputting a synchronizing pulse signal, and a capacitor having one end connected to the output terminal of the three-terminal regulator and a ground voltage signal applied to the other end, wherein the three-terminal regulator and the comparator include 3. The optical connector memory circuit according to claim 2, wherein each of them is composed of an IC chip. 4. The memory circuit for an optical connector according to claim 3, wherein the three-terminal regulator and the comparator are composed of a resistor, a transistor, and a diode. 5. The combined signal has a baseline voltage that matches the voltage of the ground voltage signal, and a top line voltage that is the top line voltage of the power supply voltage signal and a top line of the synchronization pulse signal. 2. The memory circuit for an optical connector according to claim 1, wherein the separation / extraction means is formed so as to match a sum voltage of the voltage and the voltage.