JPS59136949A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS59136949A
JPS59136949A JP58011793A JP1179383A JPS59136949A JP S59136949 A JPS59136949 A JP S59136949A JP 58011793 A JP58011793 A JP 58011793A JP 1179383 A JP1179383 A JP 1179383A JP S59136949 A JPS59136949 A JP S59136949A
Authority
JP
Japan
Prior art keywords
bumps
strength
bump
areas
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58011793A
Other languages
Japanese (ja)
Inventor
Sadasumi Uchiyama
内山　貞住
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58011793A priority Critical patent/JPS59136949A/en
Publication of JPS59136949A publication Critical patent/JPS59136949A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To reduce pitches among bumps, and to obtain an IC with bumps having strength by forming bumps in rectangles, which have short sides in the direction of arrangement of bumps and long sides in the rectangular direction thereof. CONSTITUTION:Bumps 2 form rectangles with short sides in the direction of arrangement of bumps. Consequently, the strength of bumps is increased because the areas of connection among bumps and an IC proper are widened even when pitches among bumps are reduced. Since adhesive areas with the inner lead of a substrate are widened, bonding strength is also increased, and reliability for a prolonged term to external stress is also improved. An advantage which is difficult to be crushed is available because the areas of bumps subject to load on bonding are made wide.

Description

【発明の詳細な説明】 本発明は半導体集積回路ｃ以下ＩＣという）に関するも
のである、 従来ギヤングボンディング用ＩＣのバンプは。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit (hereinafter referred to as IC). Conventional bumps on an IC for gigantic bonding are as follows.

第２図のように設計の容易さ、見た目の良はより正方形
のものが多い。一方、第６図のように長方形のものもあ
るが、これは回路基鈑のインナーリ１−”３トバンプ２
２との位置ズレの許容ｉｋ広げるのが主な目的であるた
め、バンプの並び方向に長辺を有し７ている。しかしガ
がら工Ｃの集渉度が上がって多ピン化が進むと、バンプ
間のピッチが細（なり、それによってパップの大きさも
卦のずと制約されてし甘ら、特にパップ製造の関係から
バンプ間のギャップの下限（約４０μｍ）があるため、
ビ゛／チを小さくするとバンプのサイズのみ小フ〈シな
ければ々らで、バンプ強度の低下を招きボンディング時
にとれてし甘うようになる。As shown in Figure 2, square shapes tend to be easier to design and have a better appearance. On the other hand, there is also a rectangular one as shown in Figure 6, but this is the inner 1-"3 bump 2 of the circuit board.
Since the main purpose is to widen the permissible positional deviation with respect to bumps 2, the bumps have long sides in the direction in which the bumps are arranged. However, as the concentration of Gagara C increases and the number of pins increases, the pitch between the bumps becomes narrower, which naturally limits the size of the bumps, especially when it comes to bump manufacturing. Since there is a lower limit of the gap between bumps (approximately 40 μm),
If the beach/chip is made smaller, only the size of the bump must be made smaller, which reduces the strength of the bump and makes it more difficult to come off during bonding.

そこで本発明はかかる欠点を除去したもので。Therefore, the present invention eliminates this drawback.

パップ間ピ゛・千を小ば（して、しかも強度を持つバン
プを有するＩＣを与えるものである。The present invention provides an IC having bumps with small pitches between bumps and high strength.

ｘ　ｉ　図ハ木発明の工Ｃを示したもので、バンプ２ば
その並び方向に対して短辺を有する長方形をしているの
が特徴である、このようにするとバンプ■１のピッチを
小さくしても、バンプと工Ｃ本体との接続面積が広（な
るためバンプ強度が増す。x i Figure C shows the process C of the wooden invention, which is characterized by the fact that bumps 2 are rectangular with shorter sides in the direction in which they are lined up.By doing this, the pitch of bumps 1 can be made smaller. However, the connection area between the bump and the main body of the workpiece is wide (this increases the strength of the bump).

また基板のインナーリート°との接層面積も広くなるの
でボンディング強度も増し、外部応力に対する長期信頼
性も向上する。づらにバンプサイズが小さくなるとボン
ディング時につぶれて隣りと短絡しやすくなるが、＊発
明の工Ｃの場合ボンディング時の荷重を受けるバンプの
面積が広いことによりつぶれにぐいという利点もある。Furthermore, since the contact area with the inner reed of the substrate is increased, bonding strength is increased, and long-term reliability against external stress is also improved. On the other hand, if the bump size becomes smaller, it is more likely to be crushed during bonding and short-circuited with the adjacent bump, but in the case of process C of the invention, there is an advantage that it is resistant to crushing due to the large area of the bump that receives the load during bonding.

−力木発明の工Ｃの場合、高密度化によって小型化した
にもかかわらずバンプサイズが大きいためｒＣ工Ｃサイ
ズが太き（々ってし庇うという懸念がちるが、実際には
正方形のバンプ季・２つ並べた長方形にするだけで充分
九効果があるため、工Ｃサイズとしてはそれほど犬き（
なら十、他の利点を考えた場合非常に有効な方法である
、 本発明の工Ｃは、多ピン化が必Ｖ々各麺液晶駆動用ＩＣ
等に有効で、特にそのバンプ間ピッ手が１５０μｍ以下
のものに対し大微な効果全発揮する、- In the case of the strength C of the strength wood invention, the bump size is large even though it has been miniaturized by increasing the density. Bump season: Just making two rectangles side by side has a sufficient effect, so it is not so big for the engineering C size (
This is a very effective method when other advantages are taken into consideration.The method C of the present invention requires a large number of pins for each noodle liquid crystal drive IC.
It is particularly effective for bump-to-bump pitch of 150 μm or less, and exhibits its full effect to a large extent.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に基ず（長方形のバンブ？有するＩＣの
平面図、第２図は従来の正方形のバンプを有するＩＣの
平面図、第６図は従来の長方形のバンプを有する工Ｃと
基板のインナーリードとのボンディング状態を示す平面
図である、１　・・・　ＸＣ ２・・・長方形バンプ １２・・・正方形バンプ ２２・・・従来の長方形バンプ ３・・・インナーリード 以上 出願人　株式会社　諏訪精工舎Figure 1 is a plan view of an IC with rectangular bumps based on the present invention, Figure 2 is a plan view of an IC with conventional square bumps, and Figure 6 is a plan view of an IC with conventional rectangular bumps. 1... XC 2... Rectangular bump 12... Square bump 22... Conventional rectangular bump 3... Inner lead and above Applicant Stock Company Suwa Seikosha

Claims (1)

【特許請求の範囲】[Claims] キャングボンデイング用のバンプｆその周囲に多数有す
る半導体集積回路において、前Ｆバンプはその並び方向
に短辺を、その直角方向に長辺を有する長方形をしてい
ることを特徴とする半導体集積回路。A semiconductor integrated circuit having a large number of bumps f for camp bonding around the front F bumps, wherein the front F bumps have a rectangular shape with short sides in the direction in which they are arranged and long sides in a direction perpendicular to the front F bumps. .
JP58011793A 1983-01-27 1983-01-27 Semiconductor integrated circuit Pending JPS59136949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58011793A JPS59136949A (en) 1983-01-27 1983-01-27 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58011793A JPS59136949A (en) 1983-01-27 1983-01-27 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS59136949A true JPS59136949A (en) 1984-08-06

Family

ID=11787785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58011793A Pending JPS59136949A (en) 1983-01-27 1983-01-27 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS59136949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184581B1 (en) * 1997-11-24 2001-02-06 Delco Electronics Corporation Solder bump input/output pad for a surface mount circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5362471A (en) * 1976-11-16 1978-06-03 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5362471A (en) * 1976-11-16 1978-06-03 Matsushita Electric Ind Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184581B1 (en) * 1997-11-24 2001-02-06 Delco Electronics Corporation Solder bump input/output pad for a surface mount circuit device

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