JPS59135929A - Signal selecting circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to improve the performance by converting once an input signal current to a base-emitter voltage of a transistor (TR) and extracting the result to bring a switching voltage to a low level. CONSTITUTION:Resistors 431-44n are connected respectively to emitters of a pair of TRs 411-42n of switch circuits SW1-SWn extracting an input signal from input signal sources 401-40n to operate a pair of TRs 411-42n differentially. Further, TRs 461-46n and TRs 471-47n are connected between the collector of the TRs 411-44n and a power supply terminal +Vcc and a signal current is converted into the base-emitter voltage. Moreover, the base of TRs 481-48n whose emitters are connected in cmmon is connected between the TRs 411-42n and the TRs 361-36n, and similarly the base of the TRs 491-49n is connected to the emitter of the TRs 471-47n. Then, the switching voltage is brought into a low level to simplify the constitution of a signal selecting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal selection circuit that selectively extracts a desired signal from among a plurality of input signals.

BACKGROUND ART AND PROBLEMS Conventionally, circuits as shown in FIGS. 1 and 2 have been proposed as signal selection circuits for selectively extracting one signal from a plurality of input signals. The circuits shown in FIGS. 1 and 2 are examples of selecting and extracting one of two input signals.

In FIG. 1, (1) and (2) are the signal sources of the first and second input signals, and the signal S from the first signal source (the signal S from the first signal source) and the signal S having the opposite phase thereto are in a differential configuration. The signal S2 from the second signal source (2) and the signal i having the opposite phase thereto are supplied to a pair of transistors Q9 in a differential configuration. and to) respectively. The collectors of each of the transistors α■ and (C) of the pair of transistors are connected to each other,
The connection point connects to the common load resistor → via the power supply terminal +■
Connected to CC and output terminal (9) from this connection point
is derived. In addition, the collectors of the other transistors (b) and (a) of the pair of transistors are connected in common, and the connection point is connected to the power supply terminal +vc through the resistor Qf1.
o and an output terminal (8) is led out from this connection point. Also, a pair of transistors α and (6)
A resistor α→ and (L4) are connected in series between the emitters of , and a resistor (c) is connected in series between a pair of transistors and the emitters of (a).
The connection point of and α is the collector of transistor (3),
The connection points of resistors) and (c) are connected to the collector of transistor (4), respectively. These transistors (3)
The emitters of (4) and (4) are commonly connected, and their connection point is grounded via a constant current source (5). A DC power supply (6) is connected to the pace of the transistor (3), and a signal selection signal SE is supplied to the pace of the transistor (4) through the terminal (7). 4) is differentially switched.

That is, when the signal selection signal sg has a voltage value higher than the voltage of the DC power supply (6), the transistor (4) is turned on and the transistor (3) is turned off. Therefore, the differential amplifier consisting of the transistor Q and the main circuit operates, and the second input signal S2 is taken out at the output terminals (8) and (9) in the same phase and in opposite phase. Also, terminal (7)
When the signal selection signal SE supplied to the transistor is lower than the value of the DC power supply (6), the transistor (3) is turned on and the transistor (4) is turned off. Then, the transistor (
The differential amplifier consisting of 11) and (6) operates, whereby the first input signal Sl is taken out to the output terminals (8) and (9) in the same phase and in opposite phase.

In this way, the input signal S1 and the input signal S2 are selectively taken out by the signal selection signal SE supplied to the terminal (7).

Next, in the case of the circuit example shown in Fig. 1, transistors 0→ and 04 are provided whose collectors and emitters are connected in common, respectively, and the connection point of these transistors and the collectors of (b) is connected to the power supply terminal +Vcc. , on the other hand, the connection point of the commonly connected emitters is grounded via a constant current source (to), and an output terminal (c) is led out. And the pace of the transistor 0''!I is the first through the input terminal 0.
An input signal S1 is supplied to the transistor 04, and a second input signal S2 through the input terminal 0 is supplied to the pace of the transistor 04. The pace of the transistor 0→ is grounded through the collector-emitter of the switching transistor OQ, and the pace of the transistor (b) is grounded through the collector-emitter of the switching transistor Of). And these transistors O
Q and 0's pace are respectively supplied with a switching signal through terminal 0→ and country.

In the case of the example shown in Fig. 2, when the signal S1 is obtained at the output terminal 0, a low level signal is supplied to the terminal (c), and a high level signal is supplied to the terminal (to). A signal is supplied. Then, the transistor ring is turned off, the transistor Of) is turned on, the second input signal S2 is muted through the transistor 071, and the first input signal s1 is taken out from the output terminal otJ. Conversely, in order to obtain the second signal s2 from the output terminal,
This is achieved by supplying a high level signal to the terminal (b) and a low level signal to the terminal (2) to turn on the switching transistor OQ and turn on the main transistor.

However, the signal selection circuits shown in FIGS. 1 and 2 have the following drawbacks.

First, in the case of the circuit shown in Figure 1, the transistor α power (b).

A drawback is that a large amount of signal leaks due to the stray capacitance between the collector paces (Qρ and H), and the leakage characteristics are very poor. This is because the signal is taken out from the collector side, so the output impedance is very high and leakage is large.

Furthermore, in the case of the circuit shown in FIG. 2, the transistor (g) or transistor (b) must be sufficiently saturated for switching. Therefore, the switching speed is slow,
Furthermore, the switching signal must be at a level that allows sufficient switching for the amplitude of the input signal. This is because the transistors OQ and Of) operate to mute the signal, and therefore the amplitude of this input signal must be taken into account when switching.

Furthermore, although the circuit examples in FIGS. 1 and 2 are for selecting one input signal from two input signals, this can be extended to select one input signal from a large number of input signals. In this case, the disadvantage is that it becomes a very complicated circuit.

OBJECT OF THE INVENTION In view of the above points, it is an object of the present invention to provide a signal selection circuit with good performance and free from the above-mentioned drawbacks.

Summary of the Invention This invention provides a pair of signal current sources from which a signal current is obtained differentially, and a pair of signal current sources provided between each of the pair of signal current sources and one end of a power supply terminal to convert the signal current into a pace-emitter voltage. V
A circuit consisting of third and fourth transistors for switching, the number of which is connected between the pace and the collector, is provided in parallel with the first terminal for converting into □. The emitters of each third transistor of the plurality of circuits are connected in common and supplied to the pace of one of the transistors constituting the differential amplifier, and similarly the emitters of each of the fourth transistors of the plurality of circuits are connected in common. the third and fourth transistors through the first and second transistors; The third and fourth transistors are controlled in switching by being supplied with a signal for switching, and the output terminals derived from the differential amplifier are connected to the input terminals of the circuit in which the third and fourth transistors are turned on. It is an object of the present invention to provide a signal selection circuit capable of obtaining a signal, thereby realizing a signal selection circuit with good performance without the drawbacks of the conventional ones.

EXAMPLE Hereinafter, an example of the present invention will be explained with reference to FIG.

The example shown in FIG. 3 is an example in which one input signal is selectively taken out as an output signal from n input signals.

That is, in the figure, sW, , sw, . . . so-called □ are input signal sources (401), (402), . . . (4On
) from the first. These switch circuits SWI p SW, . , only the switch circuit product rl for the first input signal source (4(h) will be explained, and for the other switch circuits SW2 to S'wn, the same number will be assigned to the corresponding one, but the number will be changed to each circuit S.
A suffix of 2 to n of WiM- will be added.

A signal Sl from an input signal source (401) and a signal element having an opposite phase thereto are supplied to the transistors (411) and (42t). These transistors (41z),
Resistance (431) between the emitters of (42t) and (44t
) are connected in series, and these resistors (431), (
A current source (44t) with a current value Il is connected between the connection point of
51) are connected, and transistors (411) and (42
1) is made to operate differentially. That is, the current flowing to the collector side is caused by the input signal source (401), and in the case of the present invention, the signal current i is caused by the pace of the transistor.
The data is transmitted as a change in the emitter voltage VBE, and therefore a transistor (461) is connected between the collector of the transistor (411) and the power supply terminal "CC" to convert this pace-emitter voltage VBIC. The collector-emitter of the VBE converting transistor (47,) is connected between the collector of the transistor (421) and the power supply terminal +Vcc.

The connection point between the emitter of the transistor (461) and the collector of the transistor (41t) is connected to the pace of the switching transistor (481).
The collector of the unzister (481) is connected to the power supply terminal +vCC. On the other hand, the connection point between the emitter of the transistor (471) and the collector of the transistor (42s) is connected to the pace of the switching transistor (491), and the collector of this transistor (491) is connected to the power supply terminal +
■Connected to 0°. The switch circuit configured as above is connected to n input signal sources (401) to (40n).
However, the emitters of the switching transistors (481), (48□)...(48n) of each switch circuit SWi1 vortex-swn are connected in common, and the It is connected to the pace of one transistor (51) constituting the dynamic amplifier (G), and each switch circuit SW1. SW, , -8Wn other switching transistor (49□), (49
□)...(49n) are commonly connected, and the connection point is connected to the pace of the other transistor (52) constituting the differential amplifier diagram. In this case, the current value of the current source (45,) (45,, )...<45n) of each switch circuit Sw1 r SWz...swn is 11+I2...In, respectively.

And a transistor (51) that constitutes a differential amplifier ring.
and (52), and a current source (53) with a current value IO is connected between the connection point and the ground. Further, a current source (54) Ai of current value I is connected between the pace of the transistor (51) and the ground, and a current source (55) of the same current value is connected between the pace of the transistor (52) and the ground. Ru. Furthermore, the collectors 7 of transistors (51) and (52)! (5)
An output terminal (58) is connected to the power supply terminal VCC through terminals 6) and (57), and is located at the connection point between the collectors of the transistors (51) and (52) and the resistors (56) and (57).
and (59) force; is derived.

Then, each switch circuit sw1. S'w2...swn
transistors (481) (491), (482)
Switching of (492), . . . (48n) (49n) is performed as follows.

That is, DC voltage sources (61) and (62) connected in series.
is provided. The DC voltage source (61) has a voltage value Vd, and the DC voltage source (62) has a voltage value V. DC voltage source (
The negative terminal of 62) is grounded. DC voltage source (61)
The positive end of is connected to the movable terminal (63o) of the switch (63). This switch (63) has fixed terminals corresponding to the number of input signal sources, each fixed terminal (631),
(632)...(63n) are the transistors (4) of the corresponding switch circuits SWI, SW2...SWn, respectively.
61) , (471) , (462) , (472)
...Connected to the paces of (46n) and (47n). The fixed terminals (631), (63z) and -(63n) are also resistors (64t) and (642)...(
64n) to a connection point between the negative end of the DC power source (61) and the positive end of the DC power source (61). Transistor (481) (49t), (482) (4h)
... (48n) (49n) are transistors (461) (47t), (462) respectively at the husband's pace
(472), ... (46n) (47n) According to the switching of the switch (63), only the one to which the voltage v+■d is supplied is turned on, and the others are turned off. , by appropriately selecting the voltage Vd.

That is, the transistors (48, i) of each switch circuit sw, ~swn are connected via the resistors (641) to (64n).
Voltage V from the power supply (62) is applied to the bases (49t) to (48n) (49n), regardless of the switching of the switch (63). Then, according to the switching of the switch (63), the transistor pairs (48□) (4'J1) to (48
The pace voltage of only one pair of (49n) is Vd, and only the pair of transistors to which this is supplied is turned on by Vd of (49n), and all others are turned off. For example, when the switch (63) is connected to the fixed terminal (631) as shown in the figure, the switch circuit S
A voltage of V+V, 1 is applied to the pace of the transistors (46t) (471) of Wl, and this is applied to the transistor (48ri (49t)) via these transistors (461) (47t). These transistors (481) and (491,) are turned on.Then, the signal current transistor pace -
The first transmission method using BE conversion is the emitter voltage.
The input signal Sl of is now led out to the output terminals (58) and (59).

Similarly, by switching the switch (63), the second
Third...n-th input signals S2+ 83...Sn are derived to output terminals (58) and (59).

Next, we will discuss the transmission of signal current by vBE conversion.
I will clarify. This ■. The conversion transmission method is that after the input signal 'current is converted to ■BIi, in this example, it is reversed in the differential amplifier wheel. The signal is converted back to the original signal and taken out to output terminals (58) and (59). This will be explained quantitatively below.

Now, explanation will be given by taking as an example the case where the switch (63) is switched to the state shown in the figure, so the switch circuit history l is turned on and the first input signal is derived to the output terminals (58) (59). . In this case, when the voltage at the connection point side of the emitters of the transistors (51) and (52) on the differential amplifier axis is v8, the switch circuit S
Since V+vd is applied to the paces of the transistors (461) and (471) of W1, this voltage 8 is the voltage between the pace and emitter of the transistor (461) and the pace-emitter of the transistor (481), which is higher than V+Vd. voltage between the emitters and the pace of the transistor (51) - the voltage between the emitters or the pace of the transistor (471)
The voltage is lower by the emitter voltage, the pace-emitter voltage of the transistor (491), and the pace-emitter voltage of the transistor (52). The transistors (46□) and (47,) are connected to the input signal source (401), respectively.
), and the input signal current il is converted into a voltage vBEVr. The above can be expressed as follows if the output signal current is I6.

VB =V+Vd VBE(46t) -vBE(4
81) −vBE(51)=V+Vd−VBz (4
7t) VB E (49t) ”B E (52)
Therefore, from the above equation, the output signal current i. is the input signal current 1
1 is obtained by multiplying it by a constant consisting of the ratio of the current value 11 of the current source (451) and the current value ■o of the current source (53) of the differential amplifier wheel.

In this way, the input signal current 71 is connected to the transistor (46t)
.

After converting vB and i by (471), the differential amplifier ■
The inverse VBF is converted by the output terminal (58) and (
59), output signal currents corresponding to the input signal are obtained which are in phase and in phase with the input signal.

Current source (451) for each switch circuit from the above equation.

(452)...(45n) current value 11. I2...
By appropriately selecting the value of I, it is possible to change the gain of the output signal for each input signal.

As described above, according to the present invention, a single signal can be selectively extracted from a plurality of input signals.

In this case, the input signal current is so-called vBff
Since the transmission is performed using the i-conversion transmission method, the switching transistors (481) (491) to (4)
8n) (49n) switching voltage may be at a small level.

Furthermore, since low voltage operation is possible, it is suitable for IC implementation.

Furthermore, a selection circuit with an arbitrary number of inputs can be realized with a simple configuration as shown in FIG. Furthermore, switching transistors (48t) (49t) to (48n) (4
Even if there is a stray resistance between the pace and the emitter of the switching transistor (48t) ('49t) to (48n) (49n), when it is on, it becomes an emitter follower, so its output impedance is low; Therefore, leakage from other switching transistors that are off is very small.

In addition, in the case of the example shown in FIG. 3, regardless of the switching of the switch (63), the voltage V is applied, so the transistor (
481) There is no risk that (49t) to (48n) (49n) will operate abnormally when turned off.

Although the signal input section of each switch circuit, ~SWn, has a simple differential amplifier configuration in the example shown in Figure 3, it is not limited to this, and in short, the signal current can be obtained differentially. Good to have.

In addition, switching transistors (481) to (48n) and (49
If a diode is connected in series to the emitters of t) to (49n), the output signal can be shifted to direct current.

Effects of the Invention As described above, in this invention, instead of transmitting the large sword signal current as it is to extract it as an output signal current, it is first converted into the transistor's pace-emitter voltage vBE and then reversed. Since the voltage is extracted by conversion, the switching voltage may be at a low level. Also, switching transistor (481) (4
9t), (48z)(492)...(48n)(
Even if there is a stray resistance between the base and emitter of 49n), when this switching transistor is in operation, this is the so-called emitter follower t1.
Since it operates as a ft component, its output impedance is low and signal leakage is extremely small. In addition, by adopting the vllK transmission method, the switching speed is fast and low voltage operation is possible.Furthermore, the switching voltage can be determined by considering the signal when converted to vBK, which is very small, so switching can be performed at low voltage. It has the advantage of being easy to integrate into an IC.

Furthermore, as is clear from Figure 3, the same number of simple switch circuits can be used for any number of inputs, so even if the number of inputs is large, it can be implemented with a relatively simple circuit configuration. There is also this effect.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing examples of conventional signal selection circuits, and FIG. 3 is a circuit diagram of an example of a signal selection circuit according to the present invention. SW! , SW2. ... swn is a switch circuit for each input signal, (40i) (40g) and (40n) are input signal sources, (411X421). (412) (42*)...(41n) (42n
) are a pair of transistors that constitute a differential amplifier that constitutes a differential signal current source, (461) and (462), respectively.
-(46n) and (47t), (47g) -(4
7n) is a transistor for vBffi conversion, (48t)
, (482)...(48n) and (491) , (
49z)...-(49n) is a switching transistor, the ring is a differential amplifier for inverse V□ conversion, (58)
and (59) are output terminals.

Claims (1)

[Claims] A pair of signal current sources from which a signal current is obtained differentially;
A pair of signals t' are provided between each of the current sources and one end of the power supply terminal to convert the signal current to the base-emitter voltage VBE F
A base-collector connection is made between the first and second transistors for C conversion, the connection point between the first and second transistors and the pair of signal current sources, and one end of the power supply terminal. A circuit consisting of third and fourth transistors for switching is provided in parallel as far as the input signal is concerned, and the emitters of the third transistors of these plurality of circuits are connected with a common number to form a differential amplifier. Similarly, the emitters of each of the fourth transistors of the plurality of circuits are connected in common and are supplied to the base of the other transistor forming the differential amplifier. Alternatively, one of the circuits is supplied with a signal for switching the third and fourth transistors through the first and second transistors, thereby causing the third and fourth transistors to switch. The signal selection circuit is controlled so that an input signal of the circuit in which the third and fourth transistors are turned on is obtained from an output terminal derived from the differential amplifier.