JPS62245810A - Dc level stabilizing circuit - Google Patents

Abstract

PURPOSE:To keep the DC potential of an output constant even with the AGC control by providing a constant current branch circuit receiving a constant current not given to the 1st and 2nd loads, branching the constant current by a half and adding it respectively to the 1st and 2nd loads. CONSTITUTION:The constant current branching circuit 33 receiving a current from the 2nd and 3rd differential pair circuits 31,32 not outputted to the 1st and 2nd loads 10,11 is provided. The constant current branching circuit 33 has two output current sources each branching the inputted current into a half and giving it as the output and the output of the two output current sources is given respectively to the lst and 2nd loads 10,11. The output DC potential is made constant even with the AGC control and the input dynamic range is expanded.

Description

[Detailed Description of the Invention] [Summary] In a DC level stabilization circuit, a constant current shunt circuit that receives constant current that is not output from the second and third differential pair amplifier circuits to the first and second loads is provided. By converting this constant current into (2 constant current) x 2 and applying it to the first and second loads respectively, the output DC potential can be kept constant even when AGC control is performed. At the same time, the input dynamic range is expanded.

[Industrial application field]

The present invention relates to an improvement in a DC level stabilizing circuit, particularly a DC level stabilizing circuit used in a variable gain amplifier using a differential pair.

In recent years, the level of signals input and output to integrated circuits is T
TL level (Transistor-Transis
It is required to be able to operate with a TTL type RC power supply voltage as well as to be able to operate with a TTL type RC power supply voltage.

Therefore, it is necessary to make it possible to input a signal with a larger amplitude when this circuit is operated at the required power supply voltage7, that is, to expand the input dynamic range.

[Conventional technology]

3 is a circuit diagram of a conventional example, FIG. 4 is a waveform diagram of FIG. 3, and FIG. 5 is a gain characteristic diagram of FIG. 3. Note that the numbers on the left side of FIG. 4 indicate the waveforms of the portions with the same numbers in FIG.

In Figures 3 and 4, transistor 1 (hereinafter 01
The first input signal (hereinafter referred to as 51g-
Assume that a sine wave voltage is applied to the base of 02 (hereinafter abbreviated as 51g-2) and a DC voltage is applied to the base of 02 as a second input δ (hereinafter abbreviated as 51g-2).

At this time, I, is Q'7. Power jL of the constant current source composed of Q6 If 12 is the collector current of 01 + 13 is the collector current of 02, (as is well known, 13=Iz=It /2, (When the voltage of 2151g-1 is higher than the voltage of 51g4, it > I, (:J) When the voltage of 51g-1 is lower than the voltage of 51g-2, r, < 1. (See Figure 4 - ■, ■).

Next, Q5. Looking at the movement of mouth 6, (]) 2
When the voltages of the two automatic gain control signals (hereinafter abbreviated as A and B) are equal, the collector current of Q6 is I÷=I5/2・I+/4, as shown in Figure 4-■, so the output voltage is I Now RL=(Iu/2)RL, and if (21A-!>8), the gain of Q6 becomes sufficiently bright compared to mouth 5 and becomes 14'
#IS becomes +14 RL#Iy RL.

(If 31A<B, the gain of 06 is almost 0, so I
+RLζO.

Figure 5 is Q5. Q6. With the gain characteristics of the part composed of RL and Is, the output voltage of 06 when A=8 is 1
When A > B, it is larger than 1, so it is on the + side, and when A < B, it is smaller than 1, so this is an example.

Next, the DC potential Vout of the output of this circuit is determined.

(1) When Δ=B, T4=I3/2=Ir=I6=rv, so l@= Iy
+Ii=Ig.

Fork, Vou L=Vcc - (RL/2) (B (
Q9's Vbe) -RL, (Is/2)・Vcc
RwIs - (Vbe of Q9) (2) When A black, as above, t4=rri=■U・T,, I,・I6
・■ et al. Since it becomes 0, Vout=Vcc-(Q 9
Vbe) RLI:S, and even if A and B are changed, the value of Vout does not change. Here, Vbe represents the voltage between the base and emitter of the transistor, and RLIRL/2 represents the resistance value of the resistors 11 and 12.

(Problems to be Solved by the Invention) In the case of the configuration shown in FIG. 3, the voltage required for biasing the transistor is Vcc -4Vbe-1.

However, 4Vbe is Q9.06. Q2. It is the sum of Vbe of Q7, and Vbe is about 0.8V when 1mA of collector current flows, and about 0.8V when the temperature changes by 50°C.
Since it changes by 1V, the total becomes 0.9V.叉、R・IKΩ
, error = 1mA.

Now, in order to match the power supply voltage to the TTL type IC,
If v, then from the above formula 5-4 Xo, 9-1 = 0.4
Most of the 5V is the bias voltage (and the rest is only 0.4VL). Therefore, if the peak value of the input signal amplitude is 0.4V or more, it will be saturated and the specified operation will not be performed. It turns out.

Therefore, if Q9 and resistor 12 are removed and connected directly to the power supply Vcc as shown by the dotted line in Figure 3, the voltage peak value of the input signal will increase by the voltage drop here, but the AG
The output DC voltage changes due to the C operation, and the DC bias voltage of the next stage changes, making the circuit design difficult. for example,
When A=8, Vout=Vcc - (Ii/2)RL,
8〉B, Vout=Vcc -h RL (
I5/2) I? Only L changes.

Therefore, there is a problem that the output DC potential does not change even if the AGC operation is performed, and the input dynamic range must be expanded.

[Means for solving problems]

As shown in FIG.
A constant current shunt circuit 33 which inputs the current from 32 is provided, and the constant current shunt circuit has two output current sources that shunt the input current into two and output the two, and the output of the two output current sources is solved by the DC level stabilization circuit of the present invention, which connects to the first and second loads 10.11, respectively.

[Effect]

The present invention is the first. A constant current shunt circuit 33 is provided which inputs the constant current from the second and third differential pair amplifier circuits 31 and 32 that is not output to the second load 10.11, and the constant current inputted by this circuit is (% constant current) I2, and each of the above 1. I made it flow to the second load.

As a result, even if 09 in FIG. 3 and resistor 12 are removed, the same operating state as before is maintained, so the input dynamic range can be expanded by the voltage drop that occurs in these parts.

〔Example〕

FIG. 2 shows an embodiment of the present invention, and the same symbols represent the same objects throughout the figures.

In addition, Q1 in the figure. Q2. Q, 7. Mouth 8, Q 3.
[14, mouth 5゜06 and Q 13-Q17. Resistor 18
20 are the first differential pair amplifier circuit 30 of FIG. 1, respectively.
Second differential pair amplifier circuit 31, third differential pair amplifier circuit 32
and the constituent parts of the constant current shunt circuit 33.

Hereinafter, the operation will be explained with reference to the drawings, using the same symbols as in the conventional example for the current flowing through each transistor.

First, Q in the constant current shunt circuit 16. Q17 is Q4
．． From the point where the collectors of and 05 are connected to each other, a constant current I
8 and outputs the same constant current I8 from the collector of Q17. And the constant current I6 from Q17 is Q1
5 through the mouth 13. Q14 is converted to (%1B)I2 and connected to the load 10.11 of 03.06 respectively.

In addition, the resistance value 2R1 of the emitter resistor 18 and 19 of the 0131 port 14 is the resistance value R1 of the emitter resistor 20 of Q15.
It's twice as much.

Next, the value of Vout when A and B are changed as described above is determined.

(When 11A=Ill, 14□ (13/2)=Ir=16=Iy, so Ir=
It becomes I5.

Also, the current flowing through the load RL of Q6 is I4. + (Ie
+/2) Therefore, Vout= Vcc -q14+(I
F/2)) R4=Vcc -IBRL (2) When 8〉B, 14=Is, Ir=I6□O, so l5=OV
out=Vcc-14RL=Vcc-15RL.

That is, even if A and B are changed, Vout does not change,
Furthermore, Vout=Vcc −15R1−−Vbe of the conventional example
Since Vout is higher by Vbe than Vbe, the input range is expanded by Vbe.

〔Effect of the invention〕

As described in detail above, according to the present invention, the DC potential difference remains constant even with GC control, and the input range is expanded by Vbe.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention, Figure 3 is a circuit diagram of a conventional example, Figure 4 is the waveform diagram of Figure 3, FIG. 5 shows the gain characteristic diagram of FIG. 3. In the figure, 10 and 11 are loads, 30 is a first differential pair amplifier circuit; 31 is a second differential pair amplifier circuit; 32 is a third differential pair amplifier circuit; 33 indicates a constant current shunt circuit. Kidobori Exit R1n Rin 哘block diagram Figure 1 Juzohaku 1n circuit diagram 3rd shoe scholar Figure 3/7-wave rib chart Figure 4 ＋　　　　　　-A-8 5th Kokushiri 41! +Special 1・'L diagram Figure 5

Claims (1)

[Claims] Having a current difference corresponding to the difference between the first and second input signals,
A first differential pair amplifier circuit (30) outputting two currents with a constant sum, and dividing the respective output currents of the first differential pair amplifier circuit by a difference corresponding to an automatic gain control signal. Gain control is performed to direct one current to the first and second loads (
10, 11), the second and third differential pair amplifier circuits (31, 32) output to the first and second loads. A constant current shunt circuit (33) is provided which inputs the current from the differential pair amplifier circuit (31, 32), and the constant current shunt circuit divides the input current into 1/2 and outputs the divided current. has an output current source, and outputs the outputs of the two output current sources to the first and second loads (10, 11), respectively.
A DC level stabilization circuit characterized by being connected to.