JPS59134812A - Ceramic circuit board containing condenser - Google Patents

Ceramic circuit board containing condenser

Info

Publication number
JPS59134812A
JPS59134812A JP844383A JP844383A JPS59134812A JP S59134812 A JPS59134812 A JP S59134812A JP 844383 A JP844383 A JP 844383A JP 844383 A JP844383 A JP 844383A JP S59134812 A JPS59134812 A JP S59134812A
Authority
JP
Japan
Prior art keywords
capacitor
circuit board
wiring
alumina
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP844383A
Other languages
Japanese (ja)
Inventor
治 牧野
徹 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP844383A priority Critical patent/JPS59134812A/en
Publication of JPS59134812A publication Critical patent/JPS59134812A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は高密度実装を必要とする電気回路に用近年の半
導体材料の著しい発達は、機器の小組化に対し非常に大
きなインパクトを与えた。これに伴い、機器の構成要素
である回路部品や回路基板などは小型化という面で特に
大きな変革を求められていた。その結果、抵抗やコンデ
ンサなどの受動素子はチップ化や基板への厚膜焼付けに
ょるハイブリッド化々どによる高密度で実装コストの安
い実装形態へと変ってきた。まだ、電気回路の相互配線
のだめの配線基板は、配線のファインライン化や多層化
による高密度配線によって小型化を図ってきた。しかし
、さらに機器の小型化を図ろうとしだ時、これまでのよ
うに回路部品や回路基板を個別に小型化するだけでは限
界があり、回路部や回路基板を含めた全体的な小型化を
図らなければならない。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to electrical circuits requiring high-density packaging.The remarkable development of semiconductor materials in recent years has had a great impact on the miniaturization of equipment. Along with this, major changes were required, especially in terms of miniaturization of the circuit components and circuit boards that constitute the components of devices. As a result, passive elements such as resistors and capacitors have changed to high-density, low-cost mounting formats, such as chips and hybridization by thick-film printing on substrates. However, wiring boards, which are used for interconnecting electrical circuits, have been miniaturized through fine-line wiring and high-density wiring through multilayer wiring. However, when trying to further miniaturize devices, there are limits to simply miniaturizing individual circuit components and circuit boards as has been done in the past. We must aim for this.

高密度配線基板の代表的なものにアルミナ配線基板があ
げられる。この配線基板は、配線導体材料としてタング
ステン(W)やモリブデン(MO)などのような高融点
金属を用いているだめ、基板材料であるアルミナ(A1
2o、+)と同時に還元雰囲気中で焼結させる事ができ
る。このだめ、アルミナ生シート上にアルミナ絶縁層と
配線導体層とを単にくシ返し設けて同時焼成するだけで
、多層配線基板が容易に得られる。加えて、アルミナ焼
結体の熱的9機械的、電気的性質は回路基板として最も
優れている。このような特徴を生かし、アルミナ配線基
板は、IC,LSIなどの高密度配線基板として広く用
いられ、特に高速信号を取扱い、その配線数が多いディ
ジタルICの配線基板としてその威力を発揮している。
A typical high-density wiring board is an alumina wiring board. This wiring board uses high-melting point metals such as tungsten (W) and molybdenum (MO) as the wiring conductor material, but the board material is alumina (A1).
2o, +) can be simultaneously sintered in a reducing atmosphere. Instead, a multilayer wiring board can be easily obtained by simply providing an alumina insulating layer and a wiring conductor layer on a raw alumina sheet and firing them simultaneously. In addition, the thermal, mechanical, and electrical properties of the alumina sintered body are the best for use as a circuit board. Taking advantage of these characteristics, alumina wiring boards are widely used as high-density wiring boards for ICs, LSIs, etc., and are especially effective as wiring boards for digital ICs that handle high-speed signals and have a large number of wires. .

しかし、この様な゛大きな特徴を有するアルミナ配線基
板ではあるが、どうしても克服できない欠点が一つあっ
た。上記配線基板は、配線の高密度化だけにその特徴が
あり、アナログ回路のように抵抗やコンデンサを数多く
重要とする回路では基板全体の高密度化という面で大き
な効果が得られない。つまり、ディジタル回路とは異な
りアナログ回路では単に配線の高密度だけでは不充分で
あり、多くの抵抗やコンデンサを含めた回路基板全体の
高密度化が重要となるからである。ところが、アルミナ
配線基板に用いられる導体材料は酸化されやすい卑金属
であるだめ、例えば基板の焼結後に抵抗やコンデンサを
厚膜として焼付けて形成しようとした時、その雰囲気は
還元、性でなければならない。最近、抵抗材料として還
元性雰囲気で焼付可能な硅化物−ガラス系のグレーズ抵
抗体が実用に供されつつあるが、コンデンサ材料に関し
ては皆無であった。このため、空気中で焼結されたチッ
プ状のコンデンサ部&を焼結された配線基板上にあとで
マウントするなど非常に繁雑でしかも高密度実装とは言
えない方法をとらざるをえなかった。まだ、別の方法と
して、導体層間のアルミナ絶縁層をコンデンサとして利
用することも考えられる。ところが、アルミナ焼結体の
比誘電率はせいぜい8〜1o程度であるだめ、絶縁層の
厚みを30μmとすれば対向電極間に得られる1−あた
りの容量はわずか3pF前後しかない。このため、大容
量のコンデンサを得るには、電極面積を大きくしたり、
絶縁層厚みをさらに薄くしたり、あるいは積層数を増す
などしなければならない。
However, although the alumina wiring board has such great features, there is one drawback that cannot be overcome. The above-mentioned wiring board is characterized only by the high density of the wiring, and in circuits such as analog circuits that require a large number of resistors and capacitors, a large effect cannot be obtained in terms of high density of the entire board. In other words, unlike digital circuits, in analog circuits it is not sufficient to simply have high wiring density, and it is important to increase the density of the entire circuit board, including many resistors and capacitors. However, the conductive material used in alumina wiring boards is a base metal that is easily oxidized, so when, for example, a resistor or capacitor is baked into a thick film after sintering the board, the atmosphere must be reducing and conductive. . Recently, silicide-glass based glazed resistors that can be baked in a reducing atmosphere have been put into practical use as resistance materials, but none have been used as capacitor materials. For this reason, we had to use a very complicated method that could not be called high-density mounting, such as mounting a chip-shaped capacitor part & that was sintered in the air on a sintered wiring board later. . Still, another method is to use an alumina insulating layer between conductor layers as a capacitor. However, the dielectric constant of the alumina sintered body is at most about 8 to 1o, so if the thickness of the insulating layer is 30 μm, the capacitance per 1 obtained between the opposing electrodes is only about 3 pF. Therefore, in order to obtain a large capacity capacitor, the electrode area must be increased,
It is necessary to further reduce the thickness of the insulating layer or increase the number of laminated layers.

このような方法は、コスト、工程面から考えて決して得
策であるとは言えない。
Such a method cannot be said to be a good idea in terms of cost and process.

以上説明してきたように、タングステンあるいはモリブ
デンを導体配線とした従来のアルミナ配線基板において
は、配線の高密度化されるが大容量のコンデンサを形成
できないため基板全体としての高密度実装化が難しく、
このだめ、その利用範囲が著しく限定されているのが実
情であった。
As explained above, in conventional alumina wiring boards with tungsten or molybdenum conductor wiring, the wiring density can be increased, but large capacitance capacitors cannot be formed, making it difficult to implement high-density packaging as a whole board.
Unfortunately, the reality is that its scope of use is extremely limited.

発明の目的 本発明の目的は、焼結と同時に大容量のコンデンサを形
成した高密度実装を可能とするセラミック回路基板を提
供することにある。
OBJECTS OF THE INVENTION An object of the present invention is to provide a ceramic circuit board that enables high-density packaging in which a large capacitor is formed simultaneously with sintering.

発明の構成 本発明のセラミック回路基板は、セラミック絶縁性基板
と、配線材料としてタングステンあるいはモリブデンか
らなる導体層とアルミニウム酸セリウム(CeA103
)からなるコンデンサ層とで構成されることを特徴とし
ている。
Structure of the Invention The ceramic circuit board of the present invention comprises a ceramic insulating substrate, a conductor layer made of tungsten or molybdenum as a wiring material, and cerium aluminate (CeA103).
) and a capacitor layer.

実施例の説明 本発明の一実施例について図面を参照しながら説明する
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

図面は本発明の一実施例におけるコンデンサを含むセラ
ミック回路基板の断面図を示すものである。同図におい
て、1はセラミック基板、2および4はタングステンあ
るいはモリブデンからなる導体層、3はCeAlO3か
らなるコンデンサ層を示す。
The drawing shows a cross-sectional view of a ceramic circuit board including a capacitor in one embodiment of the present invention. In the figure, 1 is a ceramic substrate, 2 and 4 are conductor layers made of tungsten or molybdenum, and 3 is a capacitor layer made of CeAlO3.

CeA103の粉体に10wt% のエチル−4/レロ
ースを溶解したテレピン油を、加えよく練り、コンデン
サ・ペーストとしだ。セラミック絶縁性基板として、酸
化アツベニウム(Aβ203)を主成分とした無機組成
物にポリ・ビニ−ノー・フ゛ナラール樹脂を結合剤とし
て加え、厚さ1 mmのアルミナ生・ンートの小片1を
用意した。この生シート小片\片の片面に、粒径が1μ
m前後のタングステンあるいはモリブデンからなる導体
ペーストを印刷し、導体層2を設けた。この導体層2の
上に前記コンデンサ・ペーストを印刷し、コンデンサ層
3を設け、さらに前記導体ペーストを重ねて印刷し導体
層4を設けた。この印刷された生シート小片を、水素と
窒素の混合ガスに僅かな水蒸気を含む還元性の雰囲気で
、1400〜1600℃の高温にて焼成した。焼結後の
一ンデンサ層の厚みは30μmで、導体層2,4間の対
向面積は2s7であった。
Turpentine oil containing 10 wt% ethyl-4/reulose dissolved in CeA103 powder was added and kneaded well to form a capacitor paste. As a ceramic insulating substrate, a small piece 1 of raw alumina with a thickness of 1 mm was prepared by adding poly vinyl no final resin as a binder to an inorganic composition containing atubenium oxide (Aβ203) as a main component. A small piece of this raw sheet has a grain size of 1μ on one side of the piece.
A conductive layer 2 was formed by printing a conductive paste made of tungsten or molybdenum of approximately m thickness. The capacitor paste was printed on the conductor layer 2 to form a capacitor layer 3, and the conductor paste was further printed to form a conductor layer 4. The printed raw sheet pieces were fired at a high temperature of 1400 to 1600° C. in a reducing atmosphere containing a mixed gas of hydrogen and nitrogen and a small amount of water vapor. The thickness of one indenser layer after sintering was 30 μm, and the opposing area between conductor layers 2 and 4 was 2s7.

下表に本実施例で得られた回路基板のコンデンサの代表
的な特性を示す。表から、本実施例の回路基板は優れた
コンデンサ特性を有する大容量のコンデンサを備えた回
路基板であることがわかる。
The table below shows typical characteristics of the circuit board capacitor obtained in this example. From the table, it can be seen that the circuit board of this example is a circuit board equipped with a large capacitor having excellent capacitor characteristics.

また、導体層材料の違いによるコンデンサ特性の違いも
認められない。
Furthermore, no differences in capacitor characteristics due to differences in conductor layer materials were observed.

これは、本実症例のコンデンサ部0ceAlo3自身の
誘電率が高く、且つ還元性雰囲気の高温度でも安定なペ
ロブスカイト型構造の化合物であるためであると考えら
れる。
This is considered to be because the capacitor portion 0ceAlo3 itself in this actual case has a high dielectric constant and is a compound with a perovskite structure that is stable even at high temperatures in a reducing atmosphere.

なお、実施例ではセラミック基板として酸化アルミニウ
ムを主成分とするいわゆるアルミナ基板を用いだが、こ
れに限らず、焼結後に絶縁性基板として満足できるもの
であればよい。また、実施例ではコンデンサ層を基板上
の片面に一層のみ設けだが、印刷時にコンデンサ層と導
体層とを交互に繰り返し積層化してコンデンサの容量値
を増加でき乙。
In the embodiment, a so-called alumina substrate containing aluminum oxide as a main component is used as the ceramic substrate, but the present invention is not limited to this, and any material that can be used satisfactorily as an insulating substrate after sintering may be used. In addition, in the example, only one capacitor layer is provided on one side of the substrate, but the capacitance value of the capacitor can be increased by alternately and repeatedly laminating the capacitor layer and the conductor layer during printing.

さらに、コンデンサ層は、Cehlos誂結層で構成さ
れているが、コンデンサ特性を向上させるため、弛め添
加物を付加させても構わない。
Furthermore, although the capacitor layer is composed of a Cehlos tailored layer, a loosening additive may be added to improve capacitor properties.

発明の効果 以上の説明から明らかのように、本発明はアルミニウム
酸セリウム(CeAlO3)から成るコンデンサ層をセ
ラミック基板に形成させることにより、大容量のコンデ
ンサを含む回路基板を基板の焼結と同時に作製するもの
であり、これにより、従来では配線機能のみが重視され
てきた配線基板に対し、コンデンサ層能を含む、回路構
成上非常に有利な回路基板が提供できる利点があシ、実
用上の価値は極めて高い。
Effects of the Invention As is clear from the above explanation, the present invention enables the fabrication of a circuit board containing a large capacity capacitor at the same time as the sintering of the substrate by forming a capacitor layer made of cerium aluminate (CeAlO3) on a ceramic substrate. This has the advantage of providing a circuit board with extremely advantageous circuit configurations, including capacitor layer function, compared to wiring boards where only the wiring function has been emphasized in the past, and has practical value. is extremely high.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明のアルミナ回路基板の一実施例を示す断面
図である。 1・・・・・・アルミナ基板、2・・・・・・電極、3
・・・・・・コンデンサ層、4・・・・・・電極。
The drawing is a sectional view showing one embodiment of the alumina circuit board of the present invention. 1... Alumina substrate, 2... Electrode, 3
...Capacitor layer, 4... Electrode.

Claims (1)

【特許請求の範囲】[Claims] −f=7ミノク絶縁性基板と、タングステンあるいはモ
リブデンからなる導体配線層と、アツベこラム酸セリウ
ム(ceh、eo3)からなるコンデンサ層を備えてな
るコンデンサを含むセラミック回路基板。
-f=7 A ceramic circuit board including a capacitor comprising a Minoku insulating substrate, a conductor wiring layer made of tungsten or molybdenum, and a capacitor layer made of cerium chlorate (ceh, eo3).
JP844383A 1983-01-20 1983-01-20 Ceramic circuit board containing condenser Pending JPS59134812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP844383A JPS59134812A (en) 1983-01-20 1983-01-20 Ceramic circuit board containing condenser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP844383A JPS59134812A (en) 1983-01-20 1983-01-20 Ceramic circuit board containing condenser

Publications (1)

Publication Number Publication Date
JPS59134812A true JPS59134812A (en) 1984-08-02

Family

ID=11693264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP844383A Pending JPS59134812A (en) 1983-01-20 1983-01-20 Ceramic circuit board containing condenser

Country Status (1)

Country Link
JP (1) JPS59134812A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022230412A1 (en) * 2021-04-28 2022-11-03 パナソニックIpマネジメント株式会社 Dielectric, capacitor, electric circuit, circuit board, and apparatus
WO2023218929A1 (en) * 2022-05-13 2023-11-16 パナソニックIpマネジメント株式会社 Method for manufacturing capacitor member, capacitor, electric circuit, circuit board, equipment, and power storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022230412A1 (en) * 2021-04-28 2022-11-03 パナソニックIpマネジメント株式会社 Dielectric, capacitor, electric circuit, circuit board, and apparatus
WO2023218929A1 (en) * 2022-05-13 2023-11-16 パナソニックIpマネジメント株式会社 Method for manufacturing capacitor member, capacitor, electric circuit, circuit board, equipment, and power storage device

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