JPS59132636A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59132636A JPS59132636A JP58007728A JP772883A JPS59132636A JP S59132636 A JPS59132636 A JP S59132636A JP 58007728 A JP58007728 A JP 58007728A JP 772883 A JP772883 A JP 772883A JP S59132636 A JPS59132636 A JP S59132636A
- Authority
- JP
- Japan
- Prior art keywords
- resin film
- coating resin
- semiconductor device
- active element
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に半導体チップ面をα線
ブロック効果のある樹脂膜で被覆し、α線による誤動作
を防止した半導体装置の改良に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to an improvement of a semiconductor device in which the semiconductor chip surface is coated with a resin film having an α-ray blocking effect to prevent malfunctions caused by α-rays. .
ＩＣやＬＳＩ等の半導体装置は第１図（４）の樹脂封止
・９ツケージあるいは第１図（Ｂ）のセラミックパッケ
ージ等、種々の外囲器にパッケージされた形でプリント
配線板に実装される。第１図（４）（Ｂ）において、１
は半導体ペレット、２はリード、３はポンディングワイ
ヤであり、４は樹脂モールド層、５はセラミック製外囲
器、６はハーメチックシールされた金属製の蓋体である
。なお、セラミックパッケージでは、ポンディングワイ
ヤ３とリード２とを接続するためのメタライズ導体７が
セラミック製外囲器５に設けられているＯ
ところで、上記のような種々のノやッケージ材料中には
機敏のウランやトリウム等、α線源となる放射性物質が
含まれており、これら放射性物質から放射されるα線が
ソフトエラーと呼ばれる誤動作を１き起こすことが知ら
れている。Semiconductor devices such as ICs and LSIs are packaged in various types of envelopes, such as the resin-sealed 9-cage shown in Figure 1 (4) or the ceramic package shown in Figure 1 (B), and mounted on printed wiring boards. Ru. In Figure 1 (4) (B), 1
2 is a semiconductor pellet, 2 is a lead, 3 is a bonding wire, 4 is a resin mold layer, 5 is a ceramic envelope, and 6 is a hermetically sealed metal lid. Note that in the ceramic package, a metallized conductor 7 for connecting the bonding wire 3 and the lead 2 is provided in the ceramic envelope 5. It contains radioactive substances such as uranium and thorium that act as alpha ray sources, and it is known that the alpha rays emitted from these radioactive substances can cause malfunctions called soft errors.
そこで、従来から半導体チップ１の表面をシリコーン樹
脂、ポリイミド樹脂等、・母ツケージ材料よシも上記放
射性物質の含有量が低く、かつα線のブロック効果を有
する樹脂膜でコーティングすることによりソフトエラー
の防止が図られている。Therefore, conventional methods have been used to prevent soft errors by coating the surface of the semiconductor chip 1 with a resin film such as silicone resin, polyimide resin, etc., which has a lower content of radioactive substances than the base material and has an α-ray blocking effect. The prevention of
その具体的な一つの方法として、ワイヤボンディングを
行なった後、半導体チッ７″１の表面にシリコーン樹脂
あるいはポリイミド樹脂等をポツティングする方法が従
来性なわれている。As a specific method, a conventional method is to pot silicone resin, polyimide resin, or the like on the surface of the semiconductor chip 7''1 after wire bonding.
ところが、この場合にはポツティングした樹脂材料がポ
ンディングワイヤ３の部分に廻り込むのを防止できず、
このため第２図に示すようにポンディングワイヤ３の一
部を覆ってコーティング樹脂膜８が形成されてしまう。However, in this case, it is not possible to prevent the potted resin material from getting around the bonding wire 3.
Therefore, as shown in FIG. 2, a coating resin film 8 is formed covering a portion of the bonding wire 3.
同図において９はがンディングパットである。このよう
な状態で第１図（Ｂ）のように樹脂封止を行なうと、樹
脂モールド層（一般にはエポキシ樹脂）４とコーティン
グ樹脂膜８の熱膨張係数が異なるため、熱ストレスが加
わると両者の界面に剪断応力が生じ、第３図（蜀に示す
ようにがンディングワイヤ３が切断される危険性が高い
。また、第１図（Ｂ）のようなノ９ッケージを用いる場
合にも、コーティング樹脂膜８の形成条件管理が不充分
であると、第３図（Ｂ）に示すようにコーティング樹脂
膜８の熱ストレスによる剥離が生じ、がンディングワイ
ヤ３が切断されることに々る。In the figure, numeral 9 is a landing pad. If resin sealing is performed in this state as shown in FIG. 1(B), the thermal expansion coefficients of the resin mold layer (generally epoxy resin) 4 and the coating resin film 8 are different, so if thermal stress is applied, both will There is a high risk that shearing stress will occur at the interface of the bonding wire 3 and the binding wire 3 will be cut as shown in FIG. If the formation conditions of the coating resin film 8 are insufficiently controlled, the coating resin film 8 may peel off due to thermal stress, as shown in FIG. 3(B), and the bonding wire 3 may be cut.
そこで、半導体チップ１を切り出す前のウェハ一工程に
おいて、印刷方式あるいはフォトエツチングによシ各チ
ップ領域の所定領域上を覆うコーティング樹脂膜８を形
成する方法が用いられている。この方法によればコーテ
ィング樹脂膜８を任意の・千ターンに形成できるため、
第４図（Ａ） （Ｂ）に示すようにコーティング樹脂膜
８をビンディングパッド９にかからないように形成でで
き、従って前記ポツティング法の場合のようながンディ
ングワイヤの切断を防止することができる。また、半導
体チッ７°１を切り出す前のウェハー上での処理により
コーテング樹脂膜８を形成できることから、生産性の点
でも優れている。Therefore, in one process of the wafer before cutting out the semiconductor chips 1, a method is used in which a coating resin film 8 is formed covering a predetermined area of each chip area by printing or photoetching. According to this method, the coating resin film 8 can be formed in an arbitrary number of 1,000 turns.
As shown in FIGS. 4(A) and 4(B), the coating resin film 8 can be formed so as not to cover the binding pad 9, thereby preventing the binding wire from being cut as in the case of the potting method. Furthermore, since the coating resin film 8 can be formed by processing on the wafer before cutting out the semiconductor chips 7°1, it is also excellent in terms of productivity.
上述のように、ウニハーニ程においてコーティング樹脂
膜８をパターニングする方法によれば、・母ツケージに
含まれる放射性物質に起因したα線によるソフトエラー
を防止し、かつがンディングワイヤ３の切断をも防止す
ることができる。しかし、この場合にコーティング樹脂
膜８をα線に対して特に敏感なメモリーセルや一部周辺
回路上のみを覆うとか、あるいはポンプイングツ９ツド
上を避けることだけを目的としてパターニングすると、
半導体チップ１内の能動素子上にコーティング樹脂膜８
の端縁が位置する可能性が高くなる。As described above, according to the method of patterning the coating resin film 8 during the sea urchin process, soft errors due to α rays caused by radioactive substances contained in the base cage are prevented, and cutting of the bonding wire 3 is also prevented. can do. However, in this case, if the coating resin film 8 is patterned to cover only the memory cells or some peripheral circuits that are particularly sensitive to alpha rays, or to avoid the pumping tubes 9,
Coating resin film 8 on active elements in semiconductor chip 1
It is more likely that the edge of
このコーティング樹脂膜８の端縁には樹脂の収縮による
応力が集中する。しかも、自然界に存在する放射性元素
に起因するα線のエネルギー分布は４〜５ ｅＶ程度に
ピークを有し、これを有効に防止するためコーティング
樹脂膜８は３０μ以上の膜厚を必要とするため、この収
縮応力はかなり大きくなる。このため、第５図に示すよ
うに図中矢印で示す大きな収縮応力によＱコーティング
樹脂膜８の端縁部分においてその下の半導体チップＪに
クラック１０を生じ、この部分に能動素子が存在すれば
、該素子の破５−
壊により致命不良を生じることになる。なお、第５図に
おいて１１はパッシベーション膜、１２はアルミニウム
配線、１３はダート電極、１４はケゝ−ト酸化膜、１５
はフィールド酸化膜、１６はシリコン基板、１７は不純
物拡散領域である。Stress due to contraction of the resin concentrates on the edges of the coating resin film 8. Moreover, the energy distribution of alpha rays caused by radioactive elements existing in nature has a peak at about 4 to 5 eV, and to effectively prevent this, the coating resin film 8 needs to have a thickness of 30 μ or more. , this shrinkage stress becomes quite large. For this reason, as shown in FIG. 5, a crack 10 is generated in the semiconductor chip J below the edge portion of the Q coating resin film 8 due to the large shrinkage stress indicated by the arrow in the figure, and active elements may be present in this portion. For example, failure of the element may result in a fatal failure. In FIG. 5, 11 is a passivation film, 12 is an aluminum wiring, 13 is a dirt electrode, 14 is a gate oxide film, and 15 is a dirt electrode.
1 is a field oxide film, 16 is a silicon substrate, and 17 is an impurity diffusion region.
また、これを更に第１図（Ａ）のように樹脂モールド層
４で封止することになれば、この樹脂モールド層４によ
る応力が加わることになるから、クラック１００発生に
よる致命不良率は更に大きくなる。Furthermore, if this is further sealed with a resin mold layer 4 as shown in FIG. growing.
本発明は上記事情に鑑みてなされたもので、ノｆッケー
ジに含まれる放射性元素に起因したα線によるソフトエ
ラーを防止する為に半導体チップ表面をα線ブロック効
果金有するコーティング樹脂膜で被覆すると共に、該コ
ーティング樹脂膜をポンプイングツ９ツド上にかからな
いよウニパターニングしてがンディングワイヤの切断を
防止し、更にコーティング樹脂膜の収縮応６−
力によるダメージで生じる致命不良をも回避し得る半導
体装置を提供するものである。The present invention has been made in view of the above circumstances, and in order to prevent soft errors caused by alpha rays caused by radioactive elements contained in the nof cage, the surface of a semiconductor chip is coated with a coating resin film having an alpha ray blocking effect. In addition, a semiconductor device is provided in which the coating resin film is patterned so that it does not cover the pumping wire, thereby preventing the cutting wire from being cut, and further avoiding fatal defects caused by damage caused by shrinkage force of the coating resin film. It provides:
本発明による半導体装置は、半導体チップ表面’Ｉｙｔ
”ンディングパッド上にかからないように・平ターニン
グされたα線に対するブロック効果を有するコーティン
グ樹脂膜で被覆した半導体装置において、前記コーティ
ング樹脂膜をその端縁が下地半導体チップに形成された
能動素子上に位置しないように７２ターニングしたこと
を特徴とするものである。The semiconductor device according to the present invention has a semiconductor chip surface 'Iyt
In a semiconductor device coated with a flat-turned coating resin film that has a blocking effect against alpha rays, the edge of the coating resin film is placed on the active element formed on the underlying semiconductor chip so as not to cover the landing pad. It is characterized by 72 turns so that it is not located.
本発明によれば既述した理由からボンディングワイヤの
切断を防止してα線によるソフトエラーを防止できると
同時に、もしコーティングれていないから、これによっ
て致命不良に至るのを回避することができる。According to the present invention, it is possible to prevent the bonding wire from being cut for the reasons described above, thereby preventing soft errors caused by alpha rays, and at the same time, it is possible to avoid fatal defects caused by uncoated wires.
なお、本発明はダイナミック型ＭＯ８ＲＡＭ、高抵抗負
荷のスタティック型ＭＯ８ＲＡＭ、バイポーラＲＡＭに
適用して特に効果的なものである。Note that the present invention is particularly effective when applied to a dynamic MO8RAM, a static MO8RAM with a high resistance load, and a bipolar RAM.
第６図（Ａ）は本発明の一実施例になる半導体装置の平
面図であり、第６図（Ｂ）はこれを一部拡大して示す断
面図である。これらの図において、第１図〜第５図と同
じ部分には同一の参照番号を付しである。FIG. 6(A) is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 6(B) is a partially enlarged cross-sectional view of the semiconductor device. In these figures, the same parts as in FIGS. 1 to 5 are given the same reference numerals.
第６図（Ａ）において、１８は能動素子エリアである。In FIG. 6(A), 18 is an active element area.
図示のように、この実施例ではポンディングパッド９へ
の配線を除く総ての回路素子をコーティング樹脂膜８の
下に配置し、かつコーティング樹脂膜８の端縁が能動素
子エリア１８の充分外側に配置されている。従って、第
６図（Ｂ）に示すように、コーティング樹脂膜８の端縁
下には能動素子は存在しない。As shown in the figure, in this embodiment, all the circuit elements except the wiring to the bonding pad 9 are arranged under the coating resin film 8, and the edge of the coating resin film 8 is well outside the active element area 18. It is located in Therefore, as shown in FIG. 6(B), no active element exists under the edge of the coating resin film 8.
上記実施例の半導体装置では、コーティング樹脂膜８の
収縮によってその端部下に第５図のようなりラック１０
が発生したとしても、この部分には同等能動素子が存在
しないから、致命不良を回避できる。従って、従来の半
導体装置よりも高い信頼性を得ることができる。In the semiconductor device of the above embodiment, due to the shrinkage of the coating resin film 8, a rack 10 is formed under the end thereof as shown in FIG.
Even if this happens, a fatal failure can be avoided because no equivalent active element exists in this part. Therefore, higher reliability than conventional semiconductor devices can be obtained.
また、これを第１図（Ａ）または（Ｂ）のようにノやッ
ケージングすれば、ポンディングワイヤ３の切断を生じ
ることなくα線によるソフトエラーの発生を防止できる
ことは言うまでも力い。Moreover, it goes without saying that if this is sealed as shown in FIG. 1(A) or (B), the occurrence of soft errors due to alpha rays can be prevented without causing the bonding wire 3 to be cut.
以上詳述したように、本発明によれば半導体チップ表面
をα線ブロック効果を有するコーティング樹脂膜で被覆
することにより、ソフトエラーを防止すると同時にデン
ディングワイヤの切断をも防止し、更に前記コーティン
グ樹脂膜の収縮応力によって半導体チップに生じる致命
不良をも回避できる半導体装置を提供できるものである
。As described in detail above, according to the present invention, by coating the surface of a semiconductor chip with a coating resin film having an α-ray blocking effect, it is possible to prevent soft errors and at the same time to prevent the breaking of the dending wire. It is possible to provide a semiconductor device that can avoid fatal defects caused in semiconductor chips due to shrinkage stress of the resin film.
第１図（Ａ）および（Ｂ）は夫々外囲器にノにツケーソ
ングされた半導体装置の断面図、第２図はポツティング
法によりα線ブロック効果を有するコーティング樹脂膜
で被覆した半導体ペレツ）を示す断面図、第３図（Ａ）
（Ｂ）は夫々第２図のボッチ９−
ィング法における問題点を説明するための拡大断面図、
第４図（Ａ）はパターニング法でコーティング樹脂膜を
形成した従来の半導体チップの平面図であり、第４図（
Ｂ）はその断面図、第５図は第４図（Ａ） （Ｂ）の半
導体チップにおける問題点を説明するだめの拡大断面図
、第６図体）は本発明の一実施例になる半導体チップを
示す平面図であり、第６図（Ｂ）はその拡大断面図であ
る。
１・・・半導体チップ、８・・・コーティング樹脂膜、
９・・・ポンディングパッド、１８・・・能動素子エリ
ア。
出願人代理人 弁理士 鈴 江 武 彦１０−Figures 1 (A) and (B) are cross-sectional views of a semiconductor device mounted on an envelope, respectively, and Figure 2 is a semiconductor pellet coated with a coating resin film having an α-ray blocking effect by the potting method. Cross-sectional view shown in Fig. 3 (A)
(B) is an enlarged sectional view for explaining the problems in the botching method shown in Fig. 2;
FIG. 4(A) is a plan view of a conventional semiconductor chip on which a coating resin film is formed by a patterning method.
B) is a sectional view thereof, FIG. 5 is an enlarged sectional view for explaining the problems in the semiconductor chips of FIGS. 4(A) and (B), and FIG. 6) is a semiconductor chip according to an embodiment of the present invention FIG. 6(B) is an enlarged sectional view thereof. 1... Semiconductor chip, 8... Coating resin film,
9...Ponding pad, 18...Active element area. Applicant's agent Patent attorney Takehiko Suzue 10-
Claims (1)
ようにノそターニングされたα線ブロック効果を有する
コーティング樹脂膜で被覆した半導体装置において、前
記コーティング樹脂膜をその端縁が下地半導体チップに
形成された能動素子上に位置しないように・母ターニン
グしたことを特徴とする半導体装置。In a semiconductor device in which the surface of a semiconductor chip is coated with a coating resin film having an α-ray blocking effect that is turned so as not to cover a bonding pad, the edge of the coating resin film is formed on an active layer formed on a base semiconductor chip. A semiconductor device characterized by being turned so that it is not located on an element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58007728A JPS59132636A (en) | 1983-01-20 | 1983-01-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58007728A JPS59132636A (en) | 1983-01-20 | 1983-01-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59132636A true JPS59132636A (en) | 1984-07-30 |
Family
ID=11673768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58007728A Pending JPS59132636A (en) | 1983-01-20 | 1983-01-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132636A (en) |
-
1983
- 1983-01-20 JP JP58007728A patent/JPS59132636A/en active Pending
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