JPS5913061B2 - external storage controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of an external storage control device in a digital computer system having a main storage device and a plurality of external storage devices.

Generally, a digital computer system has a main memory and a plurality of external storage devices as large-capacity storage devices capable of high-speed data transfer. The programming system (hereinafter abbreviated as 05) is always stored, and whenever it becomes necessary to update 05 in the main memory, initialization of the program can be done by loading 05 from the external storage device. I am doing it.

Furthermore, in order to deal with failures of external storage devices, multiple external storage devices are prepared, and the same OS is stored in at least two external storage devices, so that if one external storage device fails, In this case, the configuration is such that 05 can be loaded from another external storage device. Normally, an external storage control device that controls an external storage device retains a status word (hereinafter referred to as status word SW) that indicates the status of the external storage device, and the central processing unit reads the SW using a program. Although it is configured to be able to detect a failure of the storage device, if it becomes necessary to load the OS due to a factor that makes it impossible to read the SW with a program in advance,
After issuing a loading command for 05 to a specific external storage device, the central processing unit issues the command again to other external storage devices that store 05 even if the external storage device is out of order. This will cause the problem that it will not be possible to do so.

Examples of the above factors include main memory parity errors, program congestion alerts, and automatic restarts. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an external storage device that eliminates the above-mentioned problems.

A detailed explanation will be given below with reference to the drawings.

FIG. 1 is a block diagram showing an outline of a digital computer system to which the present invention is applied, and FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a detailed block diagram of the unit determination circuit FTH. In Figure 1, 10 is the central processing unit (C
11 is a main storage unit (hereinafter referred to as MU), 12 is an external storage unit (hereinafter referred to as BC), 1
3...13 are external storage devices (hereinafter referred to as BU).

In this embodiment, four BUL3s controlled by BCl2 are installed, and each one is differentiated into ≠1-+4, and each one has a unit number "002", "012", "102".
, [112]. Next, as shown in FIG. 2, BCl2 includes a status word storage section SWM2O, a unit number determination circuit FTH2l, a selection circuit ALT22, a matching circuit MTH123, MTH224, a unit number holding section UNT125, UNT226, UNT327, a decoder DCD28, an encoder ECD29, scanning circuit SCN
3O, error detection circuit DTC3l, OR gate 0R32
It is composed of.

In addition, the unit number determination circuit FTH2l is connected to the unit number registration circuit STR4O, the matching circuit M
It is composed of a TH34l, a quaternary counter CNT42, and a unit number registration circuit PST43. Next, above,
The operation of the present invention will be explained with reference to FIGS. 1 to 3.

Let us now assume that the aforementioned OS is stored at the same address (in the case of a magnetic drum device, on the same track and sector) of 1BU and 4I2BU, respectively.

Furthermore, CPUIO is +1B when +1BU is out of order.
Assume that a loading command of 0S is issued to U.
BC is a control word (previously stored in MUll by CPUIO) containing information necessary for data transfer.
(hereinafter abbreviated as CW), and UNT the unit number [002] of +1BU included in this CW.
Hold at l25.

A failure of the bottom 1BU is detected and stored by the fault detection circuit DTC3l. SWM2O is a circuit for storing the above-mentioned status word SW, which is composed of a plurality of bits each having a meaning, is read from CPUIO by a command, and is stored in MUll via the inside of CPUIO. In SWM2O, the lower 2 bits UNT226 indicate the BU unit number for identifying which RU (+1 to Φ4) the status word Sw read from MUll corresponds to, and the upper 4 bits error status word ESW Indicates various types of errors caused by data transfer, etc. The unit number “002” held in UNT125 is the selection circuit ALT.
The signal is inputted to one of the matching circuits MTH and 24 via 22. Also, Φ1 recorded in the error detection circuit DTC3l
A signal indicating a failure of the BU is converted into a signal "002" by the encoder ECD29 and inputted to the other input of the matching circuit MTH224. The matching circuit MTH,24 compares the failed unit number "002" from the encoder ECD29 with the unit number "00," from the UNTI25, and supplies the matching signal to the unit number determining circuit FTH2l. Here, according to FIG. 3, the unit number determination circuit F
The function of TH2l will be explained. FTH2l counter CN
T42 is set to "112" in advance, and the matching circuit MTH
Counting is started by a signal from 224. The output of this counter CNT42 is address "002" or "012"
Or, it is supplied as "10," or "112" to the unit number registration circuit STR4O, and the above OS storage unit number "0," previously stored in this registration circuit STR4O.
02" or "012" is read out and the matching circuit MTH34
sent to l. The final value of the counter CNT42 is stored in the unit number registration PST43. The match circuit MTH34l compares the unit number from the UNT, 25 with the unit number from the unit number registration circuit STR4O, and only when they do not match, sends the read contents of the unit number registration circuit STR4O to the SCN3O and UNT327. advances the count value of the counter CNT42 by one. Assuming that the contents shown in FIG.
The coincidence signal output to the counter CNT42 updates the counter CNT42 and outputs the address "002".

As a result, the content of address “00,” of STR4O is “01,”
” is displayed one after another and sent to the matching MTH 341. Since the match circuit MTH34l cannot match the content "002" of UNTl, the unit number "012" is output to the scanning circuit SCN3O. The scanning circuit SCN3O sends the signal corresponding to the unit number "012" to the encoder ECD.
Send on 29th. Since +2BU is not faulty, the unit number determination circuit FTH2l has already checked the coincidence cycle MTH34.
Since the unit number "012" inputted from the unit number determination circuit FTH2l via the selection circuit ALT22 and the output of the encoder ECD29 match in the matching circuit MTH224, the UN
The unit number "012" held in T327 is updated to the new unit number in decoder DCD28.
It is sent from BCl2 via. As a result, the normal ◆2BU is selected instead of the faulty ◆1BU, and the +2B
0S is loaded from U. At the same time UNT, 27
The content “012” is U which is the lower 2 bits of SWM2O.
It is held in NT,26, and the content of UNT125 is "002"
The matching circuit MTHl23 compares the . However, since the match circuit MTH cannot find a match, it sets, for example, the most significant bit of the error status word ESW to hold that an error has occurred. Each bit of the error data password ESW is set to 0R by a read command from the CPUIO.
The signal is set to 0R by the gate 32 and can be sent to the CPUIO as a signal indicating the presence or absence of an error. CPUIO is +
When the loading of 0S from 2BU is completed, the output of the 0R gate 32 is read, and if an error occurs, the read command of the status word SW is executed again, and the initially specified BU is read from the contents of the error status word ESW and UNT226. It is possible to know that the OS was transferred from a BU different from the BU. When switching between the normal data transfer of the above circuit and the loading of OS as described above, one bit of the control word CW described above has the meaning of switching, while the above bit on BC switches the operation. All you have to do is add a circuit or whatever. As is clear from the above, according to the present invention, it is now possible to switch from a failed external storage device to a normal external storage device, which was previously impossible, only by adding hardware, and furthermore, the external storage device can be duplicated. Effects such as being able to make effective use of the information can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a digital computer to which the present invention is applied, Fig. 2 is a block diagram showing the configuration of an external storage control device of the present invention, and Fig. 3 is a block diagram of the unit number determination circuit of Fig. 2. It is. 10... Central processing unit, 13... External storage device,
21... Unit number determination circuit, 22... Selection circuit, 23, 24, 41... Matching circuit, STR... Unit number registration circuit, 29... Encoder circuit, 28...
...Decoder circuit, 30.. Scanning circuit, 31.. Detection circuit.

Claims (1)

[Claims] 1. In a digital computer system having a plurality of external storage devices, a failure detection means for individually detecting a failure in each of the external storage devices, and a unit number of the external storage device specified by the central processing unit are provided. means for generating a new pre-registered unit number and sending the unit number to the external storage device if the unit number matches the unit number detected as having failed by the failure detecting means; A status code consisting of a code indicating the new unit number sent to the external storage device and an error code indicating that the unit number and the new unit number are different.
An external storage control device comprising: means for storing a word; and means for reading the error code stored in the status word according to a command of the central processing unit.