JPS59130463A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS59130463A JPS59130463A JP58208695A JP20869583A JPS59130463A JP S59130463 A JPS59130463 A JP S59130463A JP 58208695 A JP58208695 A JP 58208695A JP 20869583 A JP20869583 A JP 20869583A JP S59130463 A JPS59130463 A JP S59130463A
- Authority
- JP
- Japan
- Prior art keywords
- holes
- oxide film
- insulating film
- contact
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000011574 phosphorus Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 239000012808 vapor phase Substances 0.000 claims description 7
- 239000002305 electric material Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 101100346156 Caenorhabditis elegans moe-3 gene Proteins 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 244000061508 Eriobotrya japonica Species 0.000 description 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000010187 selection method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、集積回路装置にかがシ、特にリードオンリー
メモリー（Ｒｅａｄ ０ｎ１ｙ Ｍｅｍｏｒｙ 、以下
ＲＯＭと略す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to a read only memory (hereinafter abbreviated as ROM).
ＲＯＭマトリックスの要素としては抵抗、容量、ダイオ
ードなどが使え、初期のディジタル・コンピューターの
時代には簡単なダイオードを用いたＲＯＭが用いられて
いたが、現在ではＭＯ８型トランジスターを用いるのが
普通であシ、マイクロ・コンピューターの普及と共に、
その構成要員の一つであるＲＯＭも数多くのコードが使
用されるようになってきた。Resistors, capacitors, diodes, etc. can be used as elements of the ROM matrix, and in the early days of digital computers, ROMs using simple diodes were used, but now it is common to use MO8 type transistors. With the spread of microcomputers,
Many codes have come to be used for ROM, which is one of its components.
電気的ｊｔｅｇ込みができ、□紫外線照射又は電気的に
消去できるプログラム可能ＲＯＭ（ＦＲＯＭ）を除くと
、一般のＲＯＭはマスクＲＯＭと呼ばれており、コード
の選択は、ＲＯＭマトリックスを構成するＭＯ８型トラ
ンジスターのゲートの有無又はコンタクトの有無などを
ゲートのマスク又はコンタクトのマスクで選択すること
によってなされるが、ＲＯＭコードの受注から出荷まで
の期間を短縮するため、なるべく完成に近い工程で選択
するのが普通であシ、現在では、コンタクトで選択する
のが一般的になっている。Except for programmable ROM (FROM), which can be electrically programmed and erased by ultraviolet irradiation or electrically, general ROM is called mask ROM, and code selection is based on the MO8 type that makes up the ROM matrix. This is done by selecting the presence or absence of a transistor gate or contact, etc. using a gate mask or a contact mask, but in order to shorten the period from receiving an order to shipping a ROM code, it is recommended to select it as close to completion as possible. However, nowadays it is common to use contacts.
まず第１図を用い、従来のコンタクト選択方式によるマ
スクＲＯＭについて説明する。第１図（Ａ）は、シリコ
ン・ゲーｈＭＯ８型ＲＯＭの構造を上からみた平面図で
あシ、第１１１（Ｂ）は第１図（Ａ）のｘ−ｘ’の断面
構造を示すものである。この図でＲＯＭのコードは、コ
ンタクト・マスクによって選択されている。この構造で
は、アルミ配線１４と接触する酸化膜１１の部分はリン
ガラスになっ 。First, a conventional mask ROM using a contact selection method will be explained using FIG. FIG. 1(A) is a top plan view of the structure of a silicon game hMO8 type ROM, and FIG. 111(B) shows a cross-sectional structure taken along line xx' in FIG. 1(A). be. In this figure, the ROM code has been selected by a contact mask. In this structure, the portion of the oxide film 11 that contacts the aluminum wiring 14 becomes phosphorous glass.
ているのが普通である。しかしながらこのようなリンガ
ラス仲、微量の水分の存在によって、Ｐ、Ｏ，＋ ３Ｈ
，Ｏ−＋ ２Ｈ，ＰＯ。It is normal to have However, due to the presence of a small amount of water in the phosphorus glass, P, O, + 3H
, O-+ 2H, PO.
の反応を起こし、リン酸を生じ、これは、アルミ配線を
劣化させてしまうので、この構造では耐湿性が非常に弱
い。This reaction causes phosphoric acid, which deteriorates the aluminum wiring, so this structure has very low moisture resistance.
これを解決する方法として、リンガラスとアルミの間に
気相成長シリコン酸化膜を０．１〜１．０μの厚さに形
成しこのシリコン酸化膜を熱処理して稠密化し、リンガ
ラス層とアルミ配線を直接接触させない方法が考えられ
ている。しかしながらこの場合には、コンタクト部分の
シリコン酸化膜厚が厚くなるため、コンタクトｅエツチ
ングがむづかしくなることと、コンタクト部でのアルミ
の段切れが起こシやすくなるという新たな欠点が発生す
る。To solve this problem, a vapor-grown silicon oxide film with a thickness of 0.1 to 1.0 μm is formed between the phosphorus glass layer and the aluminum, and this silicon oxide film is heat-treated to make it denser. A method is being considered that does not allow direct contact between the wires. However, in this case, the thickness of the silicon oxide film at the contact portion becomes thicker, which causes new drawbacks such as making contact e-etching difficult and making it easier for the aluminum to break at the contact portion.
これを解決するために、該気相成長シリコン酸化膜を形
成する前と後に、同一のコンタク）−マスクを用いてコ
ンタクトの孔あけをすることがなされている。この方式
によれば第１のコンタクトの孔あけの時に、コンタクト
の形状はテーパーをもってあけ←央るため、次に気相成
長シリコン酸化膜を敷いた後のコンタクト孔における酸
化膜の段差が小さくなること、すなわち、酸化膜の急し
ゅんな段差が少なくなシ、コンタクト部でのアルミの段
切れが発生しにくくなるという利点が生ずるが、他方、
コンタクト孔あけ一気相成長シリコン酸化膜形成−コン
タクト孔あけと工程が長くなるために％ ＲＯＭコー
ドを受注してから、出荷するまでの納期が遅くなるとい
う欠点があった。In order to solve this problem, contact holes are formed using the same contact mask before and after forming the vapor phase grown silicon oxide film. According to this method, when drilling the first contact hole, the shape of the contact is opened with a taper ← in the center, so the level difference in the oxide film in the contact hole after the next vapor-phase grown silicon oxide film is laid is reduced. This has the advantage that there are fewer abrupt steps in the oxide film, making it less likely that the aluminum step will break at the contact area.
Since the process of forming a contact hole, forming a silicon oxide film by vapor phase growth, and forming a contact hole is long, there is a disadvantage that the delivery time from receiving an order to shipping the %ROM code is delayed.
本発明は、上記諸々の欠点を解決する有効な半導体装置
、とくに有効なＲＯＭの構造を提供することを目的とす
るものである。It is an object of the present invention to provide an effective semiconductor device, particularly an effective ROM structure, which solves the various drawbacks mentioned above.
本発明の特徴は、半導体基板の一生面に第１の絶縁膜た
とえば表面にリンガラスを形成した酸化膜を設け、この
第１の絶縁膜に基板の一生面に達する複数の穴が設けら
れ、この複数の穴のうちの一群の穴には第２の絶縁膜た
とえば気相成長酸化膜で充填されておハ複数の穴の残シ
の一群には基板の一生面とコンタクトする導電体たとえ
ば配線を形成する金属で充填したことである。The present invention is characterized in that a first insulating film, for example, an oxide film with phosphorus glass formed on the surface, is provided on the entire surface of the semiconductor substrate, and a plurality of holes are provided in the first insulating film that reach the entire surface of the substrate. One group of the plurality of holes is filled with a second insulating film, such as a vapor-grown oxide film, and one group of remaining holes is filled with a conductive material, such as wiring, which contacts the entire surface of the substrate. It is filled with metal that forms the
以下本発明や実施例を第２図によシ説明する。The present invention and embodiments will be explained below with reference to FIG.
第２図を参照すると（５Ｘ１）面をもち、比抵抗４Ω−
Ｏｍのシリコン基板上に通常のプロセスに従ってシリコ
ンゲート２３、ソース、ドレインとなるＮ十領域２２が
形成されている。ここで、第１のコンタクト−マスクを
用いて全てのコンタクト孔２６をあける。次いで、気相
成長シリコン酸化膜２’７をウェハー上全面に０．５μ
形成し、該シリコン酸化膜を稠密化させるため９ｏｏ℃
のスチーム雰囲気中で２０分間熱処理を行う。次いで、
第２のコンタクトｅマスクを用いてＲＯＭコードに従い
希望のコンタクト孔２６′をあけ、アルミ配線２４を形
成すればＲＯＭは完成となる。Referring to Figure 2, it has a (5X1) plane and has a specific resistance of 4Ω-
A silicon gate 23, a source, and a drain N0 region 22 are formed on a silicon substrate of Om according to a normal process. Here, all contact holes 26 are opened using the first contact mask. Next, a vapor phase grown silicon oxide film 2'7 is deposited on the entire surface of the wafer to a thickness of 0.5 μm.
90°C to densify the silicon oxide film.
Heat treatment is performed for 20 minutes in a steam atmosphere. Then,
The ROM is completed by drilling desired contact holes 26' using the second contact e-mask according to the ROM code and forming aluminum wiring 24.
本方式によるＲＯＭは、全コードに共通な第１コンタク
トのマスクで全てのコンタクトを孔あけし、気相成長シ
リコン酸化膜を形成した段階でストックしておけるので
ＲＯＭのコードを受注してからは、コンタクトは１回で
よく受注から出荷までの納期を大巾に短縮できるという
利点、リンガラスとアルミ配線とが直接接融していない
だめに、耐湿性が非常に香木ているという利点、および
ボリシリ配線とアルミ配線との交差部分も、該気相成長
シリコン酸化膜の分だけ厚くなるので、容量が減シ、ポ
リシリ配線の電位とアルミ配線の電位との相互作用、い
わゆるクロス・トークが減り、スピードもアップすると
いう利点などが生まれる。ROMs using this method can be stocked at the stage where all contacts are drilled using the first contact mask common to all codes and a vapor-phase grown silicon oxide film is formed, so after receiving an order for a ROM code, , the advantage is that the contact can be made only once and the delivery time from order to shipment can be greatly shortened, the advantage is that the phosphor glass and aluminum wiring are not directly welded, and the moisture resistance is very good. The intersection between the polysilicon wiring and the aluminum wiring also becomes thicker by the amount of the vapor-grown silicon oxide film, so the capacitance is reduced and the interaction between the potential of the polysilicon wiring and the potential of the aluminum wiring, so-called cross talk, is reduced. , there are advantages such as increased speed.
本発明の実施例をＮ−チャンネル型ＭＯ８ＩＣを例にし
て説明しだが、本発明はＰ−チャンネル型および相補型
Ｍ ＯＥ３ （０ＭＯ８）を用いたＲＯＭにも適用でき
ることは言うまでもない。また気相成長シリコン酸化膜
をリンガラス上に敷いた例で説明しであるが、シリコン
酸化膜はスパッタリング等で成長させたものでもよい。Although the embodiments of the present invention have been described using an N-channel type MO8IC as an example, it goes without saying that the present invention can also be applied to ROMs using P-channel type and complementary type MOE3 (0MO8). Further, although the example in which a vapor-phase grown silicon oxide film is spread on phosphor glass has been described, the silicon oxide film may be grown by sputtering or the like.
シリコン酸化膜の稠密化の為の熱処理は、スチーム雰囲
気で行うのが最も歩留がよいが他にＮ、雰囲気、ドライ
０．雰囲気等でもよい。尚、該シリコン酸化膜の成長温
度が高く成長済の段階ですでに十分に膜が稠密化してい
るような場合には、膜の稠密化のだめの熱処理が不要で
あることは言うまでもない。また、該気相成長のシリコ
ン酸化膜の膜厚は０．５μの例を示したが、デバイスに
よっては、０．１〜１．０μの間の任意の値をとること
が有効である。又、このシリコン酸化膜の稠密化の熱処
理は’７００−１１００℃の範囲が有効である。Heat treatment for densification of the silicon oxide film has the best yield when performed in a steam atmosphere, but it is also possible to perform heat treatment in a steam atmosphere. It could be the atmosphere, etc. It goes without saying that if the growth temperature of the silicon oxide film is high and the film is already sufficiently densified at the stage of growth, no heat treatment is required to densify the film. Furthermore, although the film thickness of the vapor-phase grown silicon oxide film is 0.5 μm, it is effective to take any value between 0.1 μm and 1.0 μm depending on the device. Further, the heat treatment for densifying the silicon oxide film is effective in the range of 700-1100°C.
第１図（Ａ）は、従来技術によるＲＯＭの平面図であシ
、第１図（Ｂ）は第１図（元を切断線ｘ −ｘ’に沿っ
て切断し矢印の方向を視た断面図である。第２図は本発
明の一実施例を示す断面図でちる。
尚、図において、１１．２１１１＠・熱シリコン酸化膜
、１２，２２・・・Ｎ拡散層（ソース・ドレイン領域）
、ｌｓ、２ｓ・・・ポリシリコン（ゲート）、１４，２
４φ・・アルミ配線、１５゜２５働・０ゲート酸化膜、
１６・・−コンタクト孔、２６・・の第１のマスクで圀
けられたコンタクト孔、２６′・・・第２のマスクで開
けられたコンタクトである。
第 １ 杷
（Ａ）FIG. 1(A) is a plan view of a ROM according to the prior art, and FIG. 1(B) is a cross-sectional view of FIG. 2 is a sectional view showing one embodiment of the present invention. In the figure, 11.2111@・thermal silicon oxide film, 12, 22...N diffusion layer (source/drain region) )
, ls, 2s...polysilicon (gate), 14,2
4φ...aluminum wiring, 15°25 working, 0 gate oxide film,
16...contact holes, 26...contact holes opened with the first mask, 26'...contacts opened with the second mask. No. 1 Loquat (A)
Claims (1)
１の絶縁膜上に第２の絶縁膜を設は該第２の絶縁膜上を
延在する導電体の配線層を設け、該第１の絶縁膜に前記
−主面に達する複数の穴を設けた集積回路装置において
、前記複数の穴のうちの一群の穴は前記第１の絶縁膜上
に設けられた第２の絶縁膜で充填されておシ、前記複数
の穴のうち残シの穴は前記導電体で充填されこれによシ
前記配線層が該残りの穴において前記−主面とコンタク
トしていることを特徴とする集積回路装置。 （２）第２の絶縁膜は気相成長したシリコン酸化膜であ
シ、第１の絶縁膜は表面にリンガラス層を形成した絶縁
膜であることを特徴とする特許請求の範囲第（１）項記
載の集積回路装置。 （８）導、電体で充填される穴はメモリーコードで選択
的に決定されたものであシ、集積回路装置はリードオン
リーメモリーであることを特徴とする特許請求の範囲第
（１）項もしくは第２項記載の集積回路装置。 （４）第２の絶縁膜の厚さばα１〜ＬＯμの厚さである
ことを特徴とする特許請求の範囲第（２）項記載の集積
回路装置。[Claims] (1) A first insulating film is provided on the entire surface of a semiconductor substrate, and a second insulating film is provided on the first insulating film and extends over the second insulating film. In an integrated circuit device in which a wiring layer of a conductor is provided and a plurality of holes reaching the main surface are provided in the first insulating film, a group of holes among the plurality of holes are formed on the first insulating film. The remaining holes among the plurality of holes are filled with the conductive material, so that the wiring layer is formed in the remaining holes on the main surface. An integrated circuit device characterized in that it is in contact with. (2) The second insulating film is a silicon oxide film grown in a vapor phase, and the first insulating film is an insulating film having a phosphorus glass layer formed on its surface. ). (8) Claim (1) characterized in that the hole filled with a conductive or electric material is selectively determined by a memory code, and the integrated circuit device is a read-only memory. Or the integrated circuit device according to item 2. (4) The integrated circuit device according to claim (2), wherein the second insulating film has a thickness of α1 to LOμ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58208695A JPS59130463A (en) | 1983-11-07 | 1983-11-07 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58208695A JPS59130463A (en) | 1983-11-07 | 1983-11-07 | Integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2961678A Division JPS54121685A (en) | 1978-03-14 | 1978-03-14 | Ic and method of fabricating same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59130463A true JPS59130463A (en) | 1984-07-27 |
Family
ID=16560540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58208695A Pending JPS59130463A (en) | 1983-11-07 | 1983-11-07 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59130463A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49115683A (en) * | 1973-03-07 | 1974-11-05 | ||
| JPS5245284A (en) * | 1976-07-19 | 1977-04-09 | Toshiba Corp | Manufcturing method of field effect transistor of silicon gate type |
-
1983
- 1983-11-07 JP JP58208695A patent/JPS59130463A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49115683A (en) * | 1973-03-07 | 1974-11-05 | ||
| JPS5245284A (en) * | 1976-07-19 | 1977-04-09 | Toshiba Corp | Manufcturing method of field effect transistor of silicon gate type |
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