JPS59129593A - Speed control circuit for motor - Google Patents

Abstract

PURPOSE:To drive a disc at constant linear speed by comparing in phase a data signal detected from the disc or a demodulated clock signal synchronized with the data signal with a reference frequency signal. CONSTITUTION:A data signal detected by a pickup 1 is compared by a comparator 11 in phase with the output (19) divided in frequency from the data signal with a reference from a reference oscillator 9, and the rotating speed of a motor is controlled by an error output. Thus, the rotating of the disc is driven at a constant linear speed, the demodulated clock signal output synchronized with the data a modulated clock signal generator 6 is compared in phase with the output of a reference oscillator by a switching control circuit 12 at the constant speed time of the motor, the rotating speed of the motor is controlled by the error output, thereby driving the disc at the constant linear speed.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a speed control circuit for a motor that rotates a disk at a constant linear velocity. The method of extracting the synchronizing signal to drive the disk at a constant linear velocity and controlling the motor has been revised, and now the data signal reproduced from the disk or the demodulated black riff signal synchronized with the data signal and the output of the reference oscillator have been changed. The present invention provides a speed control circuit for a motor that rotates a disk at a constant linear velocity by comparing the phases of the two.

<Background Art of the Invention> Recently, it has become possible to record information signals such as images or music on a disk in a concave and convex form (referred to as bi-lid), and to read and reproduce the recorded information using radiation such as a laser beam. A compact disc digital audio system has been developed and is attracting attention, but the rotation of the disc is stipulated so that the linear velocity is constant, and the rotational speed of the motor that drives the disc is Pi・
It is configured to change sequentially as references move.

Since the control signal that controls the motor is formed based on the data signal recorded on the disk, the longest synchronization signal of the data signal is detected from the data signal reproduced by Bi-Ref-Rep, and the time interval is determined. There is a method to control the motor rotation speed so that it remains constant.

Such methods include a method of detecting the peak value due to the longest synchronization signal by feeding the data signal detected from the disk to an integrating circuit, or a method of detecting the peak value due to the longest synchronization signal, or
There is a method of extracting the longest synchronization signal from the data signal by M detection, but it is impossible to detect the peak value by an integrating circuit and extract the synchronization signal by FM detection when the motor is started. This is nearly impossible unless the disk is driven at a constant linear velocity in advance, and it is necessary to somehow drive the motor to near constant rotational speed at startup.

Therefore, there were problems such as a complicated configuration.

<Object of the Invention> The present invention has been made in view of the above-mentioned points, and provides a data signal detected from a disk or a reference oscillator and a reverse black riff signal synchronized with the data signal detected from the disk. The present invention provides a speed control circuit for a motor that drives a disk at a constant linear velocity by comparing the phases of reference frequency signals.

<Configuration of the Invention> The configuration of an embodiment according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a motor speed control circuit according to the present invention (1
) emits a laser beam to the disc (2) and reproduces the information recorded on the disc (2).
0) is connected to a demodulation circuit (5) and a demodulated black riff signal generation circuit (
Supplied in the phrase. The demodulated black riff signal generation circuit (in the phrase, it is configured to generate a demodulated black riff frequency (4,3218 MH2) signal (Sl) synchronized with the data signal H signal (SO), and the way the generated pulses are output is Demodulation circuit (5
), the demodulation circuit (5) detects the length of the data signal (So) based on the demodulated black riff signal (Sl) and outputs binary data according to the length of the data signal C3O). do. The data signal (50) detected by the reference frequency (1) is specified to have a size of 3 to 11 bits of the reference frequency (4,3218 MH2) depending on the signal level, and the demodulation circuit ( 5) outputs the data signal (binary data corresponding to the length of S, that is, the signal level).

(7) is a digital-to-analog converter that converts the binary digital data from the demodulation circuit (5) into an analog signal, and the analog signal is amplified by an amplifier (not shown) and then reproduced by a speaker. (8) is a mouth/riff detection circuit which is supplied with a data signal (SO) and a demodulated black/riff signal (Sl) synchronized with the data signal (So), and detects constant speed rotation. (9) is the reference frequency (4,32113MH2
) signal, whose output is passed through the frequency divider (1
0), and a reference signal of 27KH2 is supplied to the phase comparator circuit (11). (1 is a switching control circuit, the demodulated black and V signal (Sl) are manually operated, and the output of the lock detection circuit (8) is supplied to the other input.
D circuit (13), a NAND circuit (14) to which the data signal (SO) output is supplied to the human input and the inverter output of the mouth/riff detection circuit (8) to the other input, and the NAND circuit (1).
3) and the two outputs of the NAND circuit (14) are supplied to the NA
It consists of an ND circuit (15). The output of the mouth/riff detection circuit (8) is configured to appropriately switch and output the demodulated black/riff signal (Sl) and the data signal (SO). (16) is a fly-jib-flow-rip function that is reset and reloaded by operating the play key (1η) and reloaded by operating the strip key (18), and stores the operating state. (1
9) is a programmable frequency divider, and the stop key (18)
ROM in which the division ratio data "100" was stored for 14 works.
(20) is set, and the outputs of ROM (21+(221) in which division ratio data "16" and "160" are respectively stored by operating the play key α are selected as appropriate by the selection circuit (23). Selection is set. Selection circuit (23
) is an AND circuit (2) in which the Q output of Flip-Flo-Rip 06) is supplied to the first human power and the output of the mouth/riff detection circuit (8) is supplied to the second human power, and the mouth/riff detection circuit (8) is supplied to the second human power. It consists of an AND circuit (sub) to which the inverter output of the riff detection circuit (8) is supplied. And inside the selection circuit is a lock detection circuit (
Based on the output of 8), ROM (21)□□□ is appropriately selected to select frequency division ratio data to be set in the programmable frequency divider (19).

The phase comparison circuit (11) is configured to receive the two outputs of the frequency divider (101 (19)) and generate an error voltage according to the phase difference between the two inputs. (26) is the phase comparison circuit 01.
) is a low-pass filter that generates a DC voltage according to the error voltage from the motor (28), and the output is supplied to a motor drive circuit (supply) to control the rotational speed of the motor (28).

Note that (29+(30) is an OR circuit, and (31) and (32) are inverters.

Figure 2 shows the main part of the demodulated black/rip signal generation circuit (6) in Figure 1.
This is a diagram showing the configuration of 1, which includes a one-shot lid multivibrator that operates on the rising edge of the data signal (So) detected by the data signal (1), and a one-shot lid multivibrator that operates on the falling edge. vibrator (61),
Both one-shot lid multivibrator (60) consists of a phase comparator circuit (65) into which the output (Sl) of the voltage-controlled oscillator (641) is input and a low-pass filter (66) that freely oscillates at a high frequency. has been done.

The phase comparison circuit is a NAND circuit in which the output (S2) of the pulse generation circuit (63) is supplied to one input, and the output (Sl) of the voltage controlled oscillator (f, 4) is directly supplied to the other input. (@ and inverter system), a P-channel FET (71) constituting a charge pump (70) whose gate electrode is supplied with the output of the NAND circuit (@), Gate (6
9) N-channel FE whose output is supplied to the gate electrode
It is configured to control the voltage between the terminals of the capacitor by controlling the charging and discharging of the capacitor connected between the connection point of the FET (FET) and the ground.

Therefore, the data signal (S
When this data signal (SO) is input by O),
The output (S2) of the one-shot lid multivibrator (marked) which is activated by the rising edge of the data signal (SO), and the output (Sl) of the free-running voltage controlled oscillator (64)
are compared in phase by a phase comparison circuit (65). If the phase of the current output is different, as shown in FIG.
The coincidence of the outputs (Sl) of 4) is detected by the NAND gate (capital), and during this time the capacitor □□□ is charged by the conduction of the P-channel FET (71), but subsequently the one-shot lid multivibrator field is Output (82)
and voltage controlled oscillator ((2) inverter output (Sl)
When a match is detected by the AND gate 1-(69), the charge in the capacitor ■ is discharged by the conduction of the N-channel FET@, so if the phases are locked, the discharge and charge periods will be the same, resulting in The potential of the capacitor (73) does not change.

However, when the phase shifts, a difference occurs between the charging and discharging periods, which causes a change in the potential of the capacitor, and a voltage corresponding to the difference in potential is supplied to the voltage controlled oscillator (IIAJ) via a low-pass filter. As a result, the frequency of the voltage controlled oscillator (64) is controlled so that the phase difference becomes zero.Also, even when the data signal (SO) falls,
The output (S2) of the one-shot lid multivibrator (61) and the oscillation frequency (Sl) of the voltage controlled oscillator (641)
), phase comparison is performed as described above, and phase matching between the voltage controlled oscillation frequency and the data signal (So) is performed.

Thus, the data signal (SO
) can be obtained.

Next, FIG. 4 is a diagram showing the configuration of the main part of the start/rep detection circuit (main part) in FIG.
This is a frame synchronization signal detection circuit that detects the frame synchronization signal pattern of Bi-LiD, for example, a 24 Bi-LiD shift register (81) and a matching circuit (
821, and the data Q of the shift register (81)
When the data matches the specific data set in the match circuit (82), a match output "CO" is generated. (831 (84) is a programmable down counter, which has a preset/soto enable terminal (PE) which is preset/read by the output of the OR circuit (85), and a black/lip pulse supplied with the demodulated black/lip signal (Sl). It has an input terminal (cp).

A specific number r588-10=578J is preset to the programmable down counter (83) from the specific number setting circuit value, and "1" is sent to the output terminal q at the down count of 578J, A programmable down counter (also a programmable down counter)
84) is set to ``58 B+'' by the specific number setting circuit (88).
10=598'' is preset. The q) output is supplied as the first input of the OR circuit (89), and the output of the OR circuit (80) is supplied to the recess/read terminal (R) of the flip-lip-flow-lip (face). (g
O) is an AND circuit, and the output of the human-powered frame synchronization signal detection circuit (80) is supplied to the extraction input with the q output of the plane. The lip/flow block has a serial terminal (Sl) to which the output of the AND circuit ((g) is supplied) and a serial terminal (R) to which the output Q of the programmable down counter (example) is supplied. The q output of the Fri-Rip-Flo-Rip (91) is supplied to the switching control circuit (12) shown in FIG. 1 via a time constant circuit consisting of an integrating circuit.

In addition, the data input terminal fDl is supplied with the output of the AND circuit ((1)), and the black riff pulse input terminal is supplied with the demodulated black riff signal (Sl). (CI) ) and OR its ρ) output
It is supplied as the second human power for the circuit (89). In addition, the programmable down counter (83! (84) is configured so that a specific number is preset via the OR circuit (85) in the programmable down counter (down count output 9 of 598J of 84I). There is.

Here, the frame data is 588 bits, as shown in Figure 5.
EFM (Eight to Fo
The 24-bit synchronization pattern signal bit that never appears in the 33-bit
It consists of an information bit lid of 6 bit lid + 72 bit lid (for connection) and an error correction bit lid of 112 bit vt + 24 bit lid (for connection), and the data consists of 14 bit lid. A 3-bead channel bead is inserted between the data pro riffs for connection.

Therefore, when the frame data shown in FIG. 5 is sequentially supplied to the frame synchronization signal detection circuit
They are sequentially shifted and stored based on the riff signal (Sl).

Then, upon detection of a 24-bit frame synchronization signal pattern, which is the longest synchronization signal of a data signal that never appears in E F hi, a coincidence output "1" is sent out. The sent coincidence signal "1" enables the programmable down counter +83) +84) to be preset/read via the OR circuit (85), and the specific number is preset/read by the specific number setting circuit fffi) [88). . Then, it is sequentially downcounted by the demodulated black riff signal [58B
-II] = 578 By down-counting J, "11 output is supplied as a flip-rip-70-rip (simply supplied), and it is serided. Therefore, the AND circuit (□□□ is the synchronization signal of the next frame data In order to detect the synchronization signal, the system enters a waiting state for detecting a synchronization signal.

Next, cases in which a frame synchronization signal is extracted and cases in which it is not extracted will be explained.

(1) When a frame synchronization signal is extracted, when a coincidence output “CO” is supplied from the frame synchronization signal detection circuit (internal) to the AND circuit (°C) in the frame synchronization signal detection standby state, the AND is established and the frame synchronization signal is detected.・Rip Flo Rep (91)
is asserted and supplies a "1" signal to the switching control circuit (12). Then, after a delay of 9 seconds, the "1" output from D Furi Rip Flo Rip (93) goes through the OR circuit and resets the surface. The AND circuit diagram in the synchronization signal detection standby state becomes non-conductive and the synchronization signal detection standby state is released.Furthermore,
The coincidence output “CO” presets the programmable frequency divider (E3) N via the OR circuit (me). Therefore, the programmable down counter (F!
By the time the down count output side of the 5 s a-HOJ is generated, the specific number "58 days + 10" will be newly preset to the programmable down counter (84). Then, a programmable down counter (83) (down count of 1 m is performed after the preset read) using the demodulated black 1 read signal (Sl).

Then, with the down count of 158B-IO = 5784, the programmable down counter outputs the down count output IQ = "1" to the flip-rip-flo-rip (field), and the AND circuit (beautiful It enters the synchronization signal detection standby state again.

+1) If the frame synchronization signal is not extracted, the programmable down counter (by the
(1)) Programmable down counter (1 by En)
If the synchronization signal detection circuit (80) does not generate the coincidence output "CO" during the down-count period of 58 B+10 J, the programmable down counter (l14) will output "58
8-1-10J down count output (OR by Q+
(Tai) circuit, programmable down counter (ft3
) t84) is forcibly preset. At the same time, free
Rip-Flo-Rip (91) is reset and re-read, but the time constant circuit (K) does not immediately output IM to the switching control circuit (121). Therefore, during the voltage maintenance period by the time constant circuit (92), A "1" signal is generated from the lock detection circuit (8), and a demodulated black riff signal (Sl) is supplied to the programmable frequency divider (19).
If the frame synchronization signal is not detected by the synchronization signal detection circuit (W) for a period longer than the voltage maintenance period of the I f92), the output of the opening/riff detection circuit (ω) is inverted and
) to the data signal (SO). .

Therefore, if the rotation of the disk (2) exceeds the tracking capability range of the voltage controlled oscillator, the data synchronization signal cannot be correctly demodulated, so the synchronization signal is not extracted and a coincidence output is performed.
CO'' is not generated, so the AND circuit (g8) becomes non-conductive and no SEV) is generated.
2) is always performed during rotation.

The data signal (SO) that is then played back from the disk (2)
How is the motor (28) controlled by the reference oscillator (9) and the reference oscillator (9)?
An explanation will be given regarding how the speed is controlled.

The data signal (SO
) is about 43, as shown in Figure 6, when looking at its frequency components.
Many frequency components of approximately 400 to 500 KH7 are included, with QKH2 as the center. (lower limit of half width 655KH2,
Upper limit 535KH2), this is a compact disc.
It is based on the encoding method of the digital audio system, and the peak frequency component of 43QKH2 is a signal corresponding to the magnitude of 5 bilido of the reference signal. Therefore, if we look at it continuously, the disk (from 21 to 43[l
Since the KH2 frequency component is regenerated with a high probability of occurrence, the motor is driven and controlled by paying attention to this 43QKH2 frequency spectrum.

<Operation of the Invention> The operation of the rose-shaped motor of the present invention having such a configuration will be explained respectively when starting, when the linear velocity of the motor is constant, when the motor is stopped, and when the speed of the motor is fluctuating.

(1) At the time of starting the motor, the disk (2) has stopped rotating, and by operating the play key (1η), FRI-RIP-FLO-RIP (16) is reset and re-read, and the play state is memorized. Then, the motor (
28) is not rotating at the end, so the data signal (SO) is not detected from the disk (2), or even if it is detected, the frequency is low, so it is not data and the frame synchronization signal cannot be extracted, so the data signal (SO) is not detected. As shown in FIG. 4, the output of the detection circuit (8) is set to kO by the selection circuit (23) because the flip-lip-flow-rip (91) is reset.
Frequency division ratio data "16" of M (21) is set in the programmable frequency divider (19). At the same time, NAND circuit Q3)
(14) are supplied with signals of "O" and '1', respectively, and the switching control circuit (12) is in a state in which a data signal (SO) to be reproduced from the disk (2) is sent out. Then, in the phase comparator circuit (11), the data signal (So
) is not supplied, or even if it is supplied, the frequency is low, so an output is sent to increase the rotational speed of the motor (28). That is, the motor (28) is activated.

(1) When the linear velocity of the motor is constant, the motor (28) starts and pick-up (
1), the data signal (SO) is detected, and the data signal (SO) is frequency-divided by 16 using the division ratio data "16" of the frequency divider 09) and is supplied to the phase comparator circuit (Ill 1ζ). The frequency division output based on the encoding method of the digital audio system, that is, the frequency division output of the divider (19), is still lower than the reference signal of 27 KHz, and the rotation speed of the motor (28) is further increased.

Therefore, when the disk (2) is gradually driven to rotate at a constant linear velocity and the data signal (SO) is supplied to the demodulated black riff signal generation circuit (6), the data signal (80) A voltage controlled oscillator (64) that has a tracking ability of only a few percent against fluctuations is supplied with a data signal (within a tracking ability range).
80) will be supplied. Accordingly, a demodulated black riff signal (Sl) synchronized with the data signal (SO) is generated from the demodulated black riff signal generation circuit (6). Therefore, the mouth/riff detection circuit (8) shown in FIG. 4 uses the data signal (
SO) is sequentially supplied to the shift register (81), and the coincidence output of the frame synchronization signal "C" is output by the coincidence circuit (82).
O” supplies the AND circuit (1) with a “1” output, and the OR circuit (85) sets a specific number in the programmable down counter (83) (841), and the down count output causes the flip Flo-rip (the surface is se-rided. Then, AND is established and AND times I
Flip Flo Rip (91) at the output of ff (90)
) is set to SE1), and the lock detection circuit (8) is set to “1”.
Output signal -□-1ll ・7+. Therefore, from the selection circuit (23) to the ROM (
The division ratio data "160" of 221 is read out and the division ratio data "160" is set in the programmable frequency divider (19), and at the same time, the output of the switching control circuit (1) is switched and the demodulated black riff signal (Sl) is output. It will now be sent.

Therefore, a signal of 27KH2 obtained by dividing 4.3218MH2 by 160 is sent from the frequency divider (19) to the phase comparison circuit (11
) and a phase comparison with a reference signal of 27 KHz is performed.

At this time, as shown in Fig. 7, if the rotational speed of the motor (28) that rotationally drives the disk (2) becomes abnormal, for example, in the case shown in the figure, if the rotational speed decreases a little, it will be detected by the pi ref-up (1). Since the phase of the data signal (SO) shifts to the right, the frequency of the demodulated clock signal is 4.3218MHz because it is synchronized with the data signal (SO).
will no longer match.

Therefore, in the present invention, the output of the voltage controlled oscillator (incorporated) is compared with the output of the reference oscillator (9) composed of a crystal oscillator using the phase comparator circuit (11), and the demodulated black riff signal is the reference oscillator (9). The motor drive circuit 41 according to its comparison error output so as to match the signal, 4.3218Mt (Z)
11. The rotation speed of the motor (28) driving the disk (2) is controlled by the rotation speed. In other words, controlling the rotation speed of the motor (28) so that the length of the data signal (SO) detected by the biref(1) is normal means that the linear velocity is constant. The rotation speed of the motor (28) is controlled so that

In this way, the demodulation circuit (5) is supplied with a demodulated clock signal (Sl) of 4,3218 MHz synchronized with the data signal (So), and the length of the data signal (SO) detected by the big-a-lip (1) is It is detected and demodulated into binary data.

Measurement: When the motor stops, the next time the strip key (18) is operated to end the performance, the fly-rip-fro-rip (16) is set and the Q) output “1” is sent to the OR circuit. (30) is supplied to the switching control circuit (12). Therefore, the output of the switching control circuit (12) is the output of the demodulated clock signal generation circuit (
A demodulated black riff signal (Sl) of the phrase is sent out. Also,
It OM (2
0), division ratio data "100" is set in the programmable frequency divider (19).

However, from the programmable frequency divider (19) it is 4.32
The output of the voltage controlled oscillator (64) free-running in the vicinity of 18M1-IZ, that is, the demodulated clock signal (Sl) of the demodulated clock signal generation circuit (6! Frequency division output or phase comparison circuit (11)
supplied to

However, the frequency of 43KIIZ is 27KH2 of the reference signal.
Since the phase and frequency are far ahead of each other, which is equivalent to a faster motor (support) speed, the phase comparator circuit (1
1) generates an error voltage that reduces the speed of the motor (28), so the speed of the motor (28) is rapidly reduced, which is equivalent to applying a brake. Then, the voltage controlled oscillator (circle) follows the lowered data signal and drops to the lower limit of the tracking capability range, but this value is a few percent of the center frequency, for example 4MH2, so
Since the branch output is still higher than the reference, further braking is applied and the station quickly comes to a halt. Thus, the example motor is instantaneously stopped.

(IVI motor fluctuation time ζ The cause of this motor example (disc information view)
Cases in which read is missing: In particular, cases in which fluctuations occur due to burst errors that exceed the error correction ability or vibrations that disturb the rotation of the disk, etc.) will be explained.

The motor (28) fluctuates, and the voltage controlled oscillator (circle) of the demodulated black riff signal generation circuit (6) generates its data signal (SO
), the output of the mouth/riff detection circuit (8) that detects constant speed rotation of the motor becomes "0".
becomes. As a result, the switching control circuit (12) outputs the data (No. “16” or programmable frequency divider (
19). Once upon a time, the phase comparator circuit (11
), the divided output obtained by dividing the data signal (SO) by 16 from the divider (19) is supplied to the phase comparator circuit (11), where it is phase-compared with the reference signal 271 (HZ), and the data signal (SO) is divided by 16.
) is rotated at a constant linear velocity, and the voltage controlled oscillator (64
) rotation is controlled until it reaches the tracking capability range.

In the embodiment, the frequency division ratio of the frequency divider that divides the output of the switching control circuit (12) is changed.・It may be configured differently.

In addition, in the embodiment, the detection of the motor starting to rotate at a constant speed was done by detecting the frame synchronization signal of the data signal detected from the disk, but this is effective when converting the circuit into an LSI. Although it is a high frequency amplification circuit (3
) to compact disc digital audio.
This is especially true if the system's encoding method (based on this) detects the average output of the data signal, 430K HZ, using a filter or other means and uses this as a lock detection circuit to indicate that the motor has entered constant speed rotation. It becomes easier because there is no need to extract the synchronization signal.

As described above, in the first embodiment of the present invention, the speed control of the motor is
1) When the motor starts, (when the linear velocity of the Ill motor is constant, when the measurement motor stops, and when the lvl motor fluctuates).When the motor starts, the data signal reproduced from the disk and the frequency of the reference oscillator are (by which the motor is started and
By focusing on the frequency spectrum 460KH2, which is the average output based on the encoding method of the compact disc digital audio system, dividing this by an appropriate value and comparing the phase with the divided output of the reference oscillator, the motor The rotation of the disk is controlled to a predetermined linear velocity, making it possible to extract the correct data signal from the disk, and at constant speed,
By comparing the phase of the demodulated clock signal synchronized with the data signal and the reference signal from the reference oscillator, the disk was controlled to be driven at a constant linear velocity.

Here, the reason why the input to the phase comparator circuit is switched when the motor is started and when the linear velocity of the motor is constant is to solve the following problem.

(1) Since the tracking ability of the voltage controlled oscillator constituting the demodulated black riff signal generation circuit is only a few percent of the center frequency, it is impossible to follow large fluctuations at startup.

(Based on the encoding method of the 11 Compact Digital Audio System (Frequency Spectrum 43131 (H
In the phase comparison between Z and the reference signal, the disk is rotated at a constant linear velocity, but compared to driving the motor by phase comparison between the demodulated clock signal and the reference signal, the rotational fluctuation of the motor is large, which adversely affects the reproduction characteristics. There is a risk of giving.

(As mentioned in Section 11(1), the ability of the voltage controlled oscillator to follow fluctuations in the data signal is only a few percent (for example, ±20QKH with respect to the center frequency of 4.3218MHz).
2) While the disk is rotating at a constant speed, if the data signal is greatly disturbed due to some reason (when the disk information read/write is missing: burst error, vibration that disturbs the disk rotation, etc.), the tracking ability of the voltage controlled oscillator will be affected. The rotation is out of range and the rotation control is not pulled to the specified rotation.

There was a problem.

Therefore, in the first embodiment of the present invention, a switching control circuit (12) is used to solve all of these problems.

Next, we will explain that if the voltage controlled oscillator has the ability to follow fluctuations in the data signal (red), it is possible to drive the disk at a constant linear velocity, including when the motor is started. FIG. 8 shows an improved demodulated black riff signal generation circuit (600).

That is, it is a voltage dividing circuit connected to the output stage of the ff41 +i milli-pass filter (%), which includes a resistor (kl) having one end grounded and the other end having a movable contact value), and the output stage of the low-pass filter (66). Fixed contact c76) (
77) Yesuru resistance (R2) (R3) horizontal.

The resistance value is set to R2 (R3), and the contact c75 is switched to the resistance (R3) side by the relay (78) which is excited by the mouth/riff detection output from the mouth/riff detection circuit (8). It is configured to be replaced. Therefore, when starting the motor, the voltage controlled oscillator (64) is controlled sufficiently by the relatively small resistance (R2) and the divided voltage (R1/A1+R2・V) by the resistor (R1). In response to the switching signal from the detection circuit (8), the resistor (R3) is switched to a relatively large one and has a small amplitude (R1/R1+R3).
■) works.

FIG. 9 shows an improved demodulated black riff signal generation circuit (60
0), the same components as in FIG. 1 are given the same figure numbers.

(210) is an RO set with branch ratio data “180”
M, it is read out by operating the play key (171) and set in the programmable frequency divider (19). (200) is a ROM in which division ratio data "100" is set, and by operating the strip key (18) The division ratio data is sent to the frequency divider (19) by
100”.

According to this configuration, by operating the now play key 0η, the ROM
Since the division ratio data “180” set in (210) is set in the programmable frequency divider (19), 4°32
Voltage controlled oscillator (free-running oscillation near 18MH2)
The output of 64) is frequency-divided by division ratio data "180". The result is 24 KHz in 4.3218 MH2 ÷ 180, which is delayed in frequency and phase from the 27 KHz divided output of the reference oscillator (9), so the phase comparison circuit (11
) outputs an output to quickly increase the rotation speed of the motor (28).

At this time, an error voltage with a large fluctuation range is applied to the motor (28) by the phase comparator circuit (11),
) is rotationally driven, but the demodulated black riff signal generation circuit (
The resistance of the voltage dividing circuit ff41 (600) is a small resistance (R2
), the fluctuation range is large and the voltage controlled oscillator (61) is controlled and follows.Next, the synchronization signal of the data signal (SO) is detected by the rotation of the disk (2) due to the rotation of the motor (28), When the riff detection circuit (8) sends out an opening/riff detection output of "1", division ratio data "160" is input from the ROM (220) to the division device (19).

Therefore, a signal of 27KH7 is obtained from the divider 09) and phase comparison is performed. In this case, if the speed of the motor (28) is constant, the output of the frequency divider (19) will be approximately equal to the reference signal and no error output will be generated from the phase comparison circuit (11), but if the speed of the motor (28) is constant , the demodulated black riff signal frequency generated from the demodulated black riff signal generation circuit (600) reaches the predetermined 4.32
Since it deviates from 18MH2, the motor (support) is controlled by generating an error voltage from the phase comparison circuit (11) according to the phase difference. The speed of the motor is controlled until the frequency of the demodulated black riff signal reaches a predetermined 4.3218 MHz due to the speed change of the motor (28), and no error output is generated from the phase comparison circuit (11). Thus the disk (
During the performance of 2), phase comparison is always performed and the motor (28)
is controlled to a constant linear velocity.

Next, stop playing and press the strip key (R if you used the old one).
By inputting the division ratio data "100" from the OM (200) to the division unit (19), the speed of the example motor is rapidly reduced, which is equivalent to applying a brake. In this way, the motor (support) is instantly stopped and becomes stopped.

Further, other embodiments will be described.

In the above, the motor is controlled to be driven at a constant linear velocity from the time of startup by comparing the phases of the demodulated black riff signal and the reference signal, but the data signal (SO
) and a reference signal, the motor can be controlled to a constant linear velocity. A description will be given below along with the drawings.

FIG. 10 shows a third embodiment of the present invention, in which (190) is a frequency divider into which the data signal (SO) output from the high frequency amplifier circuit (3) is input, and the division ratio is currently set to "16". ing. α (to) is a frequency divider that divides the output of the reference oscillator (9), which is composed of a crystal oscillator that oscillates a 4.3218MH7 reference signal, and the division ratio is changed during play and stripping. It is configured like this.

(2100) (2000) is a ROM in which the division ratio data of the divider 4 is set.The ROM (2100) is configured so that the division ratio data "160" is input to the divider Set to frequency divider by operation.

Furthermore, the ROM (2000) contains branch ratio data ``1600''.
" is set, and the frequency divider is configured to be set by operating the strip key (18). Therefore, the frequency division ratio of the normal divider is set to "160", and the divider ( 190) outputs a 27 KHz reference signal.

To explain the operation of the third embodiment having such a configuration, first, when the play key (1η) is operated, the ROM (2
By inputting the frequency division ratio data "160" from 100) to the divider a (to), 4.321 is output from the frequency divider -.
A 27KHz reference signal obtained by dividing the 8KH2 reference signal by 160 is input to the phase comparison circuit (11), but since the disk (2) has not yet been rotated, the phase comparison circuit (1
The divided output of the data signal (SO) from the frequency divider (190) is not input to 1), and an error signal is output from the phase comparison circuit (1υ) to increase the rotation of the motor (28). Therefore, The motor drive circuit end connects the motor (
28), the rotational speed is rapidly increased and a fast start-up can be obtained. Therefore, the disk (2) due to the rotation of the motor (to)
The data signal (SO
) is detected, the data signal (SO) is sent to the frequency divider (19
A signal of approximately 27KH2 frequency-divided by 16 by 0) is input to the phase comparator circuit (11), and the phase is compared with the reference signal. In this case, when the speed of the motor (28) becomes constant, the output of the frequency divider (190) is approximately equal to the reference signal L (no error output is generated from the phase comparator circuit (11), but the speed of the motor (support) When the speed deviates from the predetermined speed, the frequency divider (
The data signal (SO) output from 190) is 27KH.
2, the motor (28) is controlled by generating an error voltage from the phase comparison circuit (11) according to the phase difference. The phase comparator circuit (11) changes depending on the speed change of the motor (28).
) until no error output is generated from the motor (28).
Speed control is performed. Thus, while the disc (2) is being played, phase comparison is constantly performed and the motor (support) is controlled to maintain a constant linear velocity.

Next, when the performance ends and the strip key (18) is operated, the division ratio data "160" is read from it OM (2000).
0'' is input to the frequency divider QOI, an output of 2.7 KHz is obtained from the frequency divider diagram, and the phase comparator circuit (
11). The output of this time division unit (190) is 27KH2, which is ahead of the reference signal in phase, which is equivalent to a high speed of the motor (28), so the speed of the motor example is rapidly reduced and the brake is applied. It is equivalent to acting. Thus, the example motor is instantaneously stopped and comes to a standstill.

At this time, the output of the frequency divider (190) is
As the rotation speed decreases, the frequency of the data signal (SO) detected by Requa Lip (1) decreases, but
Because random pulses are being generated, the output of the divider (190) will never be completely zero, so the divider (190) when stopped is
190) may be determined by taking this random pulse frequency into consideration.

In the embodiment, the frequency division ratio of the strip time frequency divider αO1 is set to a large value so that the reference signal becomes low, but the reference signal may be cut off. Furthermore, although the embodiment is configured to change the division ratio of the frequency divider that divides the output of the reference signal, it is also possible to change the division ratio of the frequency divider that divides the output of the data signal. good.

Furthermore, a splitter (1
By using 000) and 1900, it is possible to control when the motor is started, when the motor is at constant speed, and when it is stopped. This is shown in FIG. (1900) is a high frequency amplifier circuit (3)
The data signal (SO) output is switched by switch switch (331).
The frequency divider is input via the frequency divider, and the frequency division ratio is currently set to "16". (1000) is a reference oscillator consisting of a crystal oscillator that oscillates a reference signal of 4.3218KH2 (
9), the division ratio is currently set to 160, and the reference signal of 27KH2 is sent to the frequency divider (100
0). Also, the output of the reference oscillator (9) is connected to the other fixed contact (33C) of the switching switch (33).
), and is configured to be supplied to the frequency divider (19 (10).The switching switch (19) is normally switched to one fixed contact (33b) side, and the strip key (19) is
8), it is configured to switch to the other fixed contact (33C) side. According to another example of the sixth example having such a configuration, when the play key (not shown) is operated, the frequency of the 4.3218 MHz reference signal is divided by 160 from the divider (1000). 2711 (Z reference signal is input to the phase comparator circuit (11), but the disc (2)
is not yet rotated, the branch output from the splitter (1900) is not input to the phase comparator circuit (11), and the error output from the phase comparator circuit (11) is sent to increase the rotation of the motor (28). Output.

Therefore, the motor (28
) is rapidly increased and a firm start-up is obtained. In this way, the disk (2) is driven at a constant linear velocity.

Next, when you want to finish playing the disc (2), operate the strip key 08) to switch the contact (33a) of the switch switch (33) to the other fixed contact (33C), thereby starting the reference oscillator (9). The reference signal is divided by 16 and divided into 2
7QKH2, so the phase comparison circuit (11) generates an error voltage that reduces the speed of the motor, so the speed of the motor (28) is rapidly reduced, which is equivalent to applying a brake. Thus the motor (28)
is stopped instantly and becomes stopped. In addition, the frequency divider (100
Although the division ratios of 0) (1900) are set to 160 and 16, they are not limited to this and may be determined according to the frequency whose phase is to be compared.

<Effects of the Invention> As described above, the motor speed control circuit of the present invention has the following advantages:
A switching control circuit that switches and outputs an output obtained by frequency-dividing a data signal detected by a repeater and a demodulation black riff signal output synchronized with the data signal, a reference oscillator that oscillates a reference frequency, and switches the output of this reference oscillator. The structure consists of a phase comparison means for comparing the phase with the output of the control circuit, and a means for driving and controlling the motor according to the error output from the means. By comparing the phase of the rotated output and the output of the reference oscillator and controlling the rotation speed of the motor using the error output, it is possible to control the rotation of the disk to a constant linear velocity, and when the motor is at constant speed, the data is By comparing the phases of the demodulation clock signal output synchronized with the signal and the output of the reference oscillator, and controlling the rotation speed of the motor based on the error output, the rotation of the disk can be controlled to a constant linear velocity. Then, focusing on the frequency spectrum of the data signal based on the encoding method of the compact disc digital audio system, the data signal detected from the disc at the time of motor startup is frequency-divided into an appropriate value. The motor can be started by comparing the phases of the circumferential output and the reference signal. the result,
Since the motor is sufficiently large to be within a few percent of the constant rotational speed at which the linear speed is constant, the switching control circuit compares the phase of the demodulating black riff signal synchronized with the data signal and the reference signal to control the motor linearly. Can be driven at a constant speed.

Additionally, if the disk becomes abnormally eccentric during play for some reason or the data signal fluctuates significantly, the voltage controlled oscillator in the demodulated clock signal generation circuit will reach its tracking ability and the phase locked loop will break. However, at this time, if the switching control circuit switches the output input to the phase comparator circuit to the branch output of the data signal detected from the disk, the rotation of the motor will be controlled by the branch output of the frequency spectrum of the data signal. Therefore, the motor can easily bring its rotational speed within a range of a few percent of the constant rotational speed at which the linear velocity is constant, making it extremely reliable.

In addition, by changing the division ratio of the frequency divider that divides the signal whose phase is compared when the motor is started, at constant speed, and when the motor is stopped, it is possible to make the motor start up quickly, and to quickly can be stopped. Further, since the frequency to be phase-compared is set outside the audible range, there is an advantage that it does not adversely affect the reproduction characteristics.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a first embodiment of a motor speed control circuit according to the present invention, FIG. 2 is a diagram showing the configuration of the demodulated clock signal generation circuit of FIG. 1, and FIG. Figure 2 shows the output waveform of the main part, Figure 4 shows the configuration of the top/riff detection circuit in Figure 1, Figure 5 shows the configuration of frame data, and Figure 6 shows the frequency spectrum of the data signal. Figure, 7th
The figure is a waveform diagram of each part of the demodulated clock signal generation circuit used to explain the present invention, and FIG.
A diagram showing the configuration of the demodulated black riff signal generation circuit shown in the figure,
FIG. 9 is a diagram showing the configuration of a second embodiment according to the present invention, FIG. 10 is a diagram showing the configuration of a sixth embodiment according to the present invention,
FIG. 11 is a diagram showing the configuration of another embodiment of the third embodiment of the present invention shown in FIG. 10. (1)... Pi riff up, (2)... Disc,
(6)... Demodulated black riff signal generation circuit, (8)...
・Mouth/riff detection circuit, (9)...Pukey, (20) (2
1) (22+...ROM, @...Motor drive circuit (28)...Motor, (63)...Pulse generation circuit, (64)...Voltage controlled oscillator, (65)...
Phase comparison circuit, (8o)...Frame synchronization signal detection circuit, (74)...Voltage dividing circuit, (200) (210X2
20) (20[]0X210[])...gOM,
(101]X191]Xlυ00)C19DD)・
...Branch unit. Required Iu5 tn φ -493- Procedural amendment (spontaneous) March 7, 1980 To the Commissioner of the Patent Office ＼ 1. Indication of the case Patent application No. 3653 of 1988 2. Name of the invention Motor speed control circuit 6 , Patent applicant address: 2-18 Keihan Hondori, Moriguchi City Name (188) Sanyo Electric Co., Ltd. Representative: Kungai Iue 1 person 4, Agent address: 2-18 Keihan Hondori, Moriguchi City Contact information : Telephone (Tokyo) 835-1111 Patent Center Resident Kamata 5, "Detailed Description of the Invention" column 6 of the specification to be amended, Contents of the amendment (1) In the fourth line of page 2 of the specification, "・The following sentence will be inserted after "...by comparing the phases.""Including when the motor is started" (11) The statement "...needs to be rotated" on page 3, line 14 of the specification will be corrected as follows. "...another circuit for rotational drive is required." (Ii
i) On page 5, line 14 of specification 1, “…is 27KH
zJ will be corrected to ``..., and approximately 27KHzJ. (1φ) On page 13, line 15 of the specification, ``supply'' will be corrected to ``supply this.'' fv ) In the 7th line of page 15 of the specification, the phrase "Is the degree controlled..." is replaced with "An explanation will be given regarding whether the rotation of the disk (2) is controlled to a constant linear velocity by the degree controlled." We will correct it. (vD In the 11th line of page 15 of the specification, [...(Half-width lower limit...]) was replaced with "...(Half-width: Lower limit...
・” I will correct it. (Vll Specification, page 24, line 9: “Compact
"Digital..." should be replaced with "Compact Disc..."
I will correct it as "Digital...". - Page 25, line 10 of the specification K [Linear velocity constant including startup...] was replaced with "Demodulated clock signal (Sl) synchronized with the data signal including startup and reference oscillator ( 9) The output of phase comparator α
By comparing the phase at υ, the linear velocity of disk (2) is kept constant...'' and the correction will be made. Please insert the following sentences in the first and second lines of page 36 of the detailed statement. ``Therefore, it is not necessary to separately provide a circuit that drives the motor up to near constant speed rotation and a circuit that drives and controls the motor to maintain a constant linear velocity during constant speed rotation. Start-up and drive at a constant linear velocity can be performed by switching between a data signal synchronized with the data signal and a demodulated clock signal synchronized with the data signal, making digital processing easy and IC implementation easy.Also, the disk can rotate at a constant speed by its own rotation. When the motor reaches near constant speed rotation, the switching control circuit automatically switches to a demodulated clock signal with a smaller fluctuation range and compares the phase with the reference signal, so you can expect rotation with less fluctuation in motor rotation. The playback characteristics will also be good.'' (1) The following sentence will be inserted on page 36, line 19 of the specification. Therefore, the disk can be controlled to be driven at a constant linear velocity, completely unrelated to the loss of the disk synchronization signal.''

Claims (1)

[Claims] (1) In the speed control circuit of a motor that drives a disk using a constant linear velocity method, demodulation supplies a demodulation black riff signal synchronized with the data signal to the demodulation circuit that demodulates the data signal detected from the disk. a black riff signal generating means, a switching control circuit for switching and outputting the demodulating black riff signal and a data signal detected from the disk, and means for comparing the output of the switching control circuit with the output of a reference oscillator; A motor speed control circuit comprising means for driving and controlling a motor according to an error output from said means.