JPS59129483A - Hall element - Google Patents

Abstract

PURPOSE:To obtain a Hall element, offset voltage thereof is small and which is manufactured easily, by forming a fixed conduction type thin-film in a square on the surface of a semi-insulating substrate and setting up ohmic electrodes at the four corners of the thin-film. CONSTITUTION:The surface of a semi-insulating GaAs substrate 11 in a square is coated with a thin SiO2 film, a positive type resist film of a predetermined shape is formed, <28>Si<+> ions are implanted while using the resist film as a mask, and an N type region 12 in a square, four-corner apices thereof are each positioned on four sides of the substrate 11, is formed. The resist film and the SiO2 film exposed under the resist film are removed, and sections being in contact with the four sides of the region 12 at the four corners of the substrate 11 are coated with electrodes 13 consisting of AuGe and Ni, thus forming a Hall element. Accordingly, a pattern of the normally cross-shaped Hall element is formed in a square, and offset voltage generated is reduced only by 5-3%.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a Hall element that utilizes the Hall effect.

The structure of the conventional example and its problems Currently, as a Hall element using a compound initial conductor, I n
One using a vapor-deposited film of Sb and the other using semi-insulating C1riLA.
Many have an n-type thin layer provided on an s-substrate. In the case of using GaAs, as shown in the side cross-sectional view in Fig. 1a and the plan view in Fig. 1b, a thin n-type layer 2 is formed on a semi-insulating substrate 1 by epitaxial method or ion implantation method, and etching is performed on this R42t mesa etch. It is formed as a cross-shaped Hall element. In addition, 3
is an electrode.

22, 2. Ideally, the output of the Hall element (Hall voltage) should be zero when there is no magnetic field. However, in reality, a slight potential difference occurs at the output end even in the absence of a magnetic field due to non-uniformity in current flow due to crystal defects and asymmetry in the shape of the Hall element during pattern Jung. This is called unbalanced voltage; the smaller this value is, the better. However, when pattern etching is performed using mesa etch as in the past, the symmetry of the Hall element shape tends to be lost due to uneven etching, and the end face of the pattern exposed by mesa etch is contaminated, resulting in a considerable amount of etching. The occurrence of unbalanced voltages was practically unavoidable.

Converting a single pole element into a brainer has not been successful due to thermal transformation of the surface of the semi-insulating substrate.

OBJECTS OF THE INVENTION The present invention provides a Hall element that can significantly reduce the unbalanced voltage that could not be avoided in the past, and that can also simplify the manufacturing process.

Structure of the Invention The present invention is a Hall element having a structure in which three square conductive regions are formed on the surface of a semi-insulating conductive substrate, and ohmic electrodes are provided at the four corners of the square conductive regions. Achieve all of your goals.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a side sectional view a and a plan view of an apparatus according to an embodiment of the present invention.

In the present invention, the semi-insulating substrate 11 is, for example, 300 μm thick and Cr-doped with a specific resistance of 108. GaA of Ql
Using S single crystal, chemically etching only a predetermined surface layer, and then applying 1,000 S as a protective film for ion implantation.
io2 film is formed.

28Si”e acceleration energy 13 as n-type dopant
Dose Kl at 0KaV: 6 x 10 CTL
Inject selectively. A positive resist film 177mk is used as a mask for selective implantation, and after the implantation, the positive resist film and the SiO2 protective film are removed. After this, 8
Capless annealing was performed at 50° C. for 16 minutes to form a square buried n-type layer 12 with a depth of 0.3 μm.

The ohmic electrode to the n-type layer 12 was formed by forming a total of 5,000 5i02 films and using a positive photoresist mask.
After removing only the Aro5iOz film on the soil of the electrode part by chemical etching, AuGe and Ni were deposited.

Use the so-called lift-off method, which removes the positive photoresist and forms the electrodes. This was heat treated at 440°C,
Furthermore, n was applied on top of this electrode using the lift-off method.

An electrode 13 was formed by forming Pt and Au.

One side of the n-type layer 12 is 0.36 ml, a dicing width of 0.025 u is taken around this, and the chip is a square with q4 skin.

Even in this structure, the insulation properties of the outside of the square n-type conductive region 12 are reduced due to thermal transformation during annealing.
Since the conductive region has a lower internal resistance than a cross-shaped pattern, it was possible to suppress the influence of the machining process on the decrease in impedance outside the region.

Now, if the aforementioned unbalanced voltage is vHo, and the unloaded Hall voltage vH is the value obtained by subtracting the unbalanced voltage from the Hall voltage that occurs when 6V is applied to the input terminal of the Hall element in the magnetic field of I KG, then the unbalanced Hall voltage is When comparing the conventional cross-shaped pattern Hall element and the Hall element of the embodiment of the present invention with respect to this unbalance ratio, it was possible to reduce the unbalance ratio to ±3% compared to ±6%.

Effects of the Invention As described above, the present invention reduces the unbalanced voltage that could not be avoided in the past by making the Hall element planar with a 1GaAs substrate. The manufacturing process can also be simplified, and the practical value is significant.

[Brief explanation of drawings]

Figure 1 1! L and b show a side sectional view and a plan view of a Hall element formed by mesa etching, and FIGS. 2a and 2b show a side sectional view and a plan view of a Hall element according to an embodiment of the present invention. 11... Semi-insulating substrate, 12... N-type conductive region. 13... Electrode. Name of agent: Patent attorney Naka Yashiki, and one other person Figure 1 Figure 2

Claims (1)

[Claims] A Hall element having a square thin layer of a predetermined conductivity type on the surface of a highly durable substrate, and having ohmic electrodes at the four corners of the square conductive layer.