JPS59127463A - Picture signal processor - Google Patents

Abstract

PURPOSE:To write image data at a high speed and to reduce the size of a copying machine by converting the image data into a parallel signal and storing the signal, and then transfering it to a memory for image data on the basis of DMA. CONSTITUTION:The image data from a sensor is converted by a conversion part 6 into the parallel digital signal, which is read, word by word, in the memory 8. Further, a counter 9 counts words written in the memory 8 and sets an FF10 when its counted value attains to a specific number, sending out a DMA request signal from its Q output. Consequently, a DMAC2 sends a request HOLD to a microcomputer 1 to enter DMA operation. The memory 8 uses a signal IOR from the DMAC2 as a shift-out clock signal during the DMA operation to transfer the image data from the memory 8 to an RAM3. This transfer data is written in a specific address of the RAM3 by using a signal MEMW from the microcomputer 1 as a clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to an image signal processing device that speeds up the writing of serial digital image signals sent from an image sensor into a dynamic RAM (hereinafter referred to as DRAM).

(B) Prior art As a conventional image signal processing device, for example, a digital copying machine is used, and a serial digital image signal (image data) corresponding to a document image sent from an image sensor is used.
The image data is stored in a magnetic storage section consisting of a hard disk, a 70 disk, etc., and the image data is read out from the magnetic storage section to a printer section using a thermal transfer method or the like to reproduce the original image.

According to such a digital copying machine, an original image is optically exposed on a photoreceptor, and the image (electrostatic latent image) is developed, transferred to transfer paper, and fixed to obtain a copy. Compared to conventional machines, this system does not require a corotron, photosensitive drum, etc., so the configuration can be simplified and maintainability can be improved.

However, in conventional digital copying machines, a two-step process is performed: the image data is once input to the CPU of the control unit, processed, and then written to the transfer destination memory (magnetic storage unit). Because of this, it takes time to transfer and process a large amount of image data, and during that time the CPU is
Because the transfer process is difficult, there is a risk that you will not be able to control other operations, and because it is equipped with a magnetic storage unit such as the aforementioned hard disk or 70 disk.
Digital copying machines had become a big deal.

(c) Purpose and structure of the invention The present invention has been made in view of the above.It is an object of the present invention to write image data sent from an image sensor into a memory at high speed, and to reduce the size and cost. , converts the image data into a parallel digital signal of a predetermined number of bits, stores it once based on the time series of the conversion, outputs it based on the time series, and converts the output parallel digital signal into a DMA (Dirset Me
The present invention provides an image signal processing device that transfers image data to an image data memory based on the image data memory.

B) Embodiment (Structure) The image signal processing device according to the present invention will be described in detail below.

FIG. 1 shows an image data cocitronic unit in a digital copying machine according to an embodiment of the present invention, and the DMA, which will be described later, is shown in FIG.
Controller (DMAC) A microcomputer (hereinafter referred to as a microcomputer) that performs preprocessing such as channel selection in 2, commands, mode instructions, etc., and resetting (intermediate processing) addresses, word count registers, etc. for each byte transfer. ) 1 and the DMAC (Dlrea
M@mory Aeass Control
r) 2, an image data RAM 3 consisting of a byte DRAM 64, and an input/output section operated based on the control of the DMAC 2, which receives image data sent from an image sensor (not shown). Parallel digital signals (
The input section 4 converts the image data stored in the RAM 3 into a serial digital signal and outputs it to the printer section (not shown). Components are connected through address buses, data buses, control paths, and the like.

The input section 4 includes a conversion section 6 that converts image data (serial digital signal) into a 16-bit 1 word parallel digital signal using an input image data clock, an input image data input circuit 7, and a 64-word x 16-bit parallel digital signal.
FIFO (First In
It is a memory of φ
After temporarily storing the image data from the converter 6, the RA
The memory 8 to be transferred to M3 and the count-up value are set in advance to a predetermined value, for example, 32 (this preset value is
The processing time ((64-32)
6 pits/word x transfer frequency is established), and the Carantuff carry signal is counted.
The bit binary counter 9 and the R8 flip-flop 10, which is set by the carry signal of the counter 9 and outputs the DMA request signal to the DMAC 2, are preset in the same way as the counter 9, and are read into the RAM 3 during the DMA operation (IOR signal, i.e. , 6-bit binary counter 11 that counts the number of words (one word is 16 bits) and resets the 7-lip 70-tub 10 with the carry signal. Similarly, counters 9 and 11 are cleared by output signals Q and Q of flip 70 and knob 10, respectively.

On the other hand, the output unit 5 is a memory having the same configuration as the output image data 12 and the memory 8, and has the same configuration as the output image data 12 and memory 8.
Shift in by device write) signal, and counter 1
Each shift-out operation is performed using the carry signal (output signal) of 2, and after temporarily storing the image data from the RAM 3, the memory 13 outputs it to the l conversion unit 14, and the output image data clock causes the image data to be output from the memory 13. A converting section 14 that converts image data (parallel digital signal, 1 word of 16 bits) into a serial digital signal and a predetermined value, for example, 3, similar to the counter 9,
A 6-bit binary counter 15 is set with a count-up value of 2 and counts the error signal of the counter 12.
is set by the carry signal of the counter 15, and the DMA
The R87 lip flop 16 that outputs the request signal to the DMAC 2 is preset in the same way as the counter 15, and is read from the RAM 3 during DMA operation (IO
A 6-bit binary counter 16 counts the number of words (1 word 16 bits) and resets the flip 7 block 16 with the carry signal. It consists of Similarly, the counters 15 and 17 are cleared by the output signals i and Q of the 7-lip flop 16, respectively.

B) Embodiment (Operation) The operation of the above configuration will be explained with reference to the time chart of FIG. 2 (A) and (→).

Before the DMAC 2 transfers image data, the microcomputer 1 performs preprocessing such as channel selection, command, and mode instructions for the DMAC 2, and then passes the address bus, data path, control bus, etc. to the DMAC 2. An initialization routine is performed to perform a DMA operation to transfer image data sent from the image sensor.

Now, the image data sent from the image system ((b) in FIG. 2(A)) is converted to 1 by the l converter 6 by the input image data clock ((a) in FIG. 2(0)).
The signal is converted into a parallel digital signal of 6 bits and 1 word and inputted to the memory 8. At this time, S I (5
The carry signal ((C) in FIG. 2(A)) of the Kaukakunta 7 is given to υ(initialization routine), and the I
r@ady) is @″1″), memory 8
The input image data is read word by word. Further, the counter 9 counts the number of words of the image data read into the memory 8 by counting the carry signal of the counter 7, and the count number reaches a predetermined number 32 (here, 32 is treated as one block). ), output a carry signal and set flip 7 and flip 10. In the initialization routine, OR (0output r@ady) @ of memory 8.
The DMA request signal is output from the Q output ((e) in FIG. 2 0)). This DM
In response to the A request signal, the DMAC 2 issues a HOLD request to the microcomputer 1, and upon receiving the IOLD acknowledge signal confirming the request, begins a DMA operation. During the DMA operation, the memory 8 reads the image data read into the memory 8 and transfers it to the RAM 3 using the IOR signal (IO device read signal) from the DMAC 2 as a shift-out clock signal. The transferred image data is written to a predetermined address in the RAM 3 using the MEMW signal from the microcomputer 1 as a clock signal. This D
During MA operation, the counter 11 counts the IOR signal and the counter 11 flips 70. Counting is started after clearing by the Q output of step 10), and a carry signal is output after counting one block, that is, 32 words. 10
Reset. At this time, the counter 9 is cleared by the output of the 7-lip 70-tub 10. Below, input section 4
, DMAC2, etc., as shown in Fig. 2 ←), the same operation as above is performed repeatedly, and after writing the byte (1 segment) of image data to 64, the D
MAC2 is an interrupt signal due to the end of DMA (Figure 2 (b)
(d)) is applied to microcomputer 1.

This completes the input operation of input image data. However, if a large amount of data is to be transferred and the data is to be transferred beyond the memory address space of RAM3, the microcomputer 1 receives the interrupt signal and performs necessary intermediate processing, for example, Updates the upper address of , resets the DMAC address, word count register, etc. At this time, in order to provide enough time for intermediate processing by microcomputer 1 (to prevent image data that continues to be sent even during intermediate processing from being dropped), the preset values of counters 9 and 11 are changed, for example, from 32 to 4. Perform the switching operation to After completing these intermediate processing and switching operations in the microcomputer 1, a DMA operation is performed to transfer the next segment, thereby making it possible to transfer a large amount of image data.

Next, the image data output operation will be explained with reference to the time charts shown in FIG. 3 (a) and ←).

The memory 13 receives the IOW signal (IO device write signal,
Shift in at (f) in Figure 3 (a), and change the output image data clock (a) in Figure 3 (a)) to (a) in Figure 3 (a).
Due to the shift out operation in (C)), RAM 3
Output image data is written word by word (16-bit parallel signal). Counter 15 is this memory 1
When the count reaches 1 block (32 words), a carry signal ((d) in FIG. 3(a)) is output, and the flip-flop 16 is set. The shift flip 70 knob 16 of this set outputs a DMA request signal to the DMAC 2 and enters a DMA operation. During the DMA operation, the Pβ converter 14 converts the parallel digital signal from the memory 13 into a serial digital signal and outputs the serial digital signal using the output image data clock.

During this DMA operation, the counter 17 counts the IOW signal, counts one block, outputs a carry signal, and resets the flip-flop 16 (FIG. 3(a) (g)). Thereafter, in the output unit 5 DMAC2, etc., the same operation as above is performed repeatedly as shown in Figure M3←], and the reading of the image data of 64 bytes is completed, and the DMAC2 outputs the output image data. Finish the operation.

In this output image data output operation, if a large amount of data needs to be transferred, the microcomputer 1 uses counters 15 and 17 to secure intermediate processing time, as described in the input image data input operation. Switch the preset value.

Similarly, the present invention is not limited to the digital copying machine of the above embodiment, but may be applied to other image signal processing apparatuses, such as facsimile machines.

(f) According to the detailed description of the invention, the image signal processing device of the present invention:
Converting a serial digital image signal into a parallel digital image signal with a predetermined number of bits, storing it once based on the time series of the conversion, outputting it based on the time series, and converting the output parallel digital image signal into a parallel digital image signal. Since the image data is transferred to the image data memory (dynamic RAM) based on DMA, the image data sent from the image sensor can be written into the memory at high speed.

Furthermore, since it does not include a hard disk or floppy disk, the device can be made smaller and less expensive.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an image data control section of a digital copying machine according to an embodiment of the present invention, FIG. 2 (a) and (b) are a time chart showing the operation of the input section, and FIG. (a) and ←) are time charts showing the operation of the output section. Explanation of symbols 1... Microcomputer, 2... DMAC, 3... Dynamic RAM (RAM for image data), 4...
...Input section, 5...Output section, 6...φ conversion section, 7.12...4-bit binary counter, 8.1
3...FIFO memory, 9,11,15゜17
...6-bit binary counter, 1o. 16...R87 lipfrog. Patent applicant Fuji Xerox Co., Ltd. Agent Patent attorney Shin Matsubara 2

Claims (1)

[Scope of Claims] An image signal processing device that stores a serial digital image signal sent from an image sensor in a memory, reads it from the memory, and outputs it to an image reproduction section, wherein the serial digital image signal is determined in advance. converting means for converting the parallel digital image signals into parallel digital image signals of the number of bits; memory means for inputting the parallel digital image signals based on the time series of the conversion and outputting them based on the time series; and output from the memory means. The parallel digital image signals obtained are processed by DMA (Direct Memory Access).
An image signal processing apparatus comprising: a control means for storing image data in an image data memory based on the image data (ss).