JPS5912626A - Current switching type logical circuit - Google Patents

Current switching type logical circuit

Info

Publication number
JPS5912626A
JPS5912626A JP57121587A JP12158782A JPS5912626A JP S5912626 A JPS5912626 A JP S5912626A JP 57121587 A JP57121587 A JP 57121587A JP 12158782 A JP12158782 A JP 12158782A JP S5912626 A JPS5912626 A JP S5912626A
Authority
JP
Japan
Prior art keywords
emitter
transistor
base
voltage
trq3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57121587A
Other languages
Japanese (ja)
Other versions
JPH0261820B2 (en
Inventor
Kazumi Yamada
和美 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57121587A priority Critical patent/JPS5912626A/en
Publication of JPS5912626A publication Critical patent/JPS5912626A/en
Publication of JPH0261820B2 publication Critical patent/JPH0261820B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain the suppression of a reverse base-emitter voltage with high general-purpose application, by connecting a base of the 3rd transistor(TR) to an emitter common connecting point of the 1st and the 2nd TRs, connecting the collector to a high potential power supply and connecting the emitter to a reference power supply. CONSTITUTION:A TRQ3 is provided, whose emitter is connected to a base of a TRQ1, whose base is connected to the emitter of the TRQ1 and whose collector is connected to a power supply VCC. When an input level VIN of an input terminal IN is decreased and a reverse base-emitter voltage of the TRQ1 is equal to a forward base-emitter voltage VF of the TRQ3, the TRQ3 turns on and an emitter current of the TRQ3 flows from the terminal IN through a current limit resistor RB1. Thus, the reverse base-emitter voltage of the TRQ1 does not exceed the VF.

Description

【発明の詳細な説明】 本発明は、電流切換型論理回路に関する。[Detailed description of the invention] The present invention relates to a current switching type logic circuit.

エミッタを相互に接続したトランジスタ対で、一方のト
ランジスタのベースを入力端子ｌＮ１７Ｃ，他方のトラ
ンジスタのベースを基準電圧源ＶＢＩＦ　Ｉｃ接続した
、所謂電流切換型論理回路の一例を、第１図に示す。同
図で、入力端子ＩＮの入力レベルＶＩＮが、基準電圧源
ＶＢＩＰの電圧レベルＶＲより低い場合、トランジスタ
Ｑ！にオフ（ＯＦＦ　）　ｌ、、トランジスタＱｚがオ
ン（ＯＮ）する。この時、トランジスタＯＮ時のベース
＝エミッタ電圧をＶＦとすると、トランジスタＱ１と、
トランジスタＱ２のエミッタ接続点の電位ＶＢに、Ｖｍ
＝Ｖａ−ＶｒｌＣ固定され、入力レベル■■Ｎとは無関
係となる。従って、入力レベルＶＩＮが非常に低く＜、
例えば接地電位ｕ（Ｖ）である様な時には、トランジス
タＱ１のベース＝：Ｌ　ミｙ　ｐ接合ｖＣＶＩＮ　−Ｖ
ｉ＝Ｖｐ　−ＶＲ（＜０　）　！　ル逆方向電圧が加わ
る。FIG. 1 shows an example of a so-called current switching type logic circuit, which is a pair of transistors whose emitters are connected to each other, and in which the base of one transistor is connected to an input terminal IN17C and the base of the other transistor is connected to a reference voltage source VBIF Ic. In the figure, when the input level VIN of the input terminal IN is lower than the voltage level VR of the reference voltage source VBIP, the transistor Q! When the transistor Qz is turned off (OFF) l, the transistor Qz is turned on (ON). At this time, if the base-emitter voltage when the transistor is ON is VF, then the transistor Q1 and
Vm is applied to the potential VB at the emitter connection point of transistor Q2.
=Va-VrlC is fixed and has no relation to the input level ■■N. Therefore, the input level VIN is very low<,
For example, when the ground potential is u (V), the base of the transistor Q1 =:L y p junction vCVIN -V
i=Vp-VR(<0)! reverse voltage is applied.

一方、最近の高速論理回路に於いては、高速化の為、ベ
ース幅が極端に狭く、従って、比較的低いペース＝エミ
ッタ逆方向電圧ＢＶＢＰＩの印加で容易にブレークダウ
ンやパンチスルーを生ずるから、基準電圧レベルＶＢの
値によってｕ　、　Ｂ　ＶＢＩ　＜ＶＲ−ＶＦとなり、
トランジスタＱ１のエミッタカラ、ベースに回って急減
に電流が流れ、素子の破壊や％動作不全の原因となり得
る。On the other hand, in recent high-speed logic circuits, the base width is extremely narrow in order to increase the speed, and therefore breakdown or punch-through can easily occur when a relatively low pace=emitter reverse voltage BVBPI is applied. Depending on the value of the reference voltage level VB, u, B VBI < VR - VF,
Current flows rapidly between the emitter and base of the transistor Q1, which may cause destruction of the element or malfunction.

上記の様な、過大な逆方向電圧の印加を防止する為、第
２図に示す様なダイオードスイッチが従来より用いられ
ている。同図で、入力端子が接地レベル皮下っ念楊合、
ダイオードＤ１には抵抗ＲＢｊＪ　を通してＯＮ電流が
流れ、トランジスタＱｔのペース電位は２ＶＦ以下にほ
ならない０従って一トランジスタＱｌのベース＝エミッ
タ逆方向電圧ｔａ　２Ｖｒ−Ｖａ＋Ｖｐ＝３Ｖｐ−Ｖｈ
　　（！：　！　Ｄ、余８　高イＶｕ’ｅ加えない限ジ
トランジスタＱｌのエミッタ＝ペース接合がブレークダ
ウン等を起こす事ぼなくなる。In order to prevent the application of excessive reverse voltage as described above, a diode switch as shown in FIG. 2 has been conventionally used. In the same figure, make sure the input terminal is at ground level below the skin.
An ON current flows through the diode D1 through the resistor RBjJ, and the pace potential of the transistor Qt must be less than 2VF. Therefore, the base-emitter reverse voltage of one transistor Ql is ta 2Vr-Va+Vp=3Vp-Vh
(!: ! D, extra 8 As long as Vu'e is not added, the emitter-pace junction of the ditransistor Ql will not cause breakdown etc.

しかしながら、第２図の回路では、基準電圧■の選び方
次第でに未だブレークダウンの可能性は残る事、又、入
力レベルＭＩＮが高く、トランジスタＱ２のペース−エ
ミッタに高い逆方向電圧が加わる場合には適用できない
事等の問題があり、回路設計上の制約を与えている０ 本発明の目的に、上述のトランジスタのペース＝エミッ
４逆方向電圧印加による動作不全を防止すると共に、従
来回路（Ｃあった回路設計上の制約を取り除き、入力端
子側でも、基準電圧側でも適用できる等汎用性を兼え之
回路を提供するものである。However, in the circuit shown in Figure 2, there is still a possibility of breakdown depending on how the reference voltage ■ is selected, and if the input level MIN is high and a high reverse voltage is applied to the pace-emitter of transistor Q2. The purpose of the present invention is to prevent malfunctions due to the application of a reverse voltage to the transistors described above, and also to prevent the conventional circuits (C This eliminates the existing circuit design constraints and provides a circuit that is versatile and can be applied to both the input terminal side and the reference voltage side.

上記目的の為、本発明は、エミッタを相互に結合した第
１及び第２のトランジスタにより構成される電流切換型
論理回路に於いて、該第１のトランジスタのベースに、
第３のトランジスタのエミッタをｗｉｔ、、該第３のト
ランジスタのベースを、該第１及び第２のトランジスタ
のエミッタ共通接続点に接続し、更ＶＣ該第３のトラン
ジスタのコレクタを高位側電源に接続すると共に、該第
３のトランジスタの工ばツタを適当な抵抗を介して入力
端子又は基準電源に接続した事を特徴とする。For the above purpose, the present invention provides a current switching type logic circuit constituted by first and second transistors whose emitters are coupled to each other, in which the base of the first transistor is connected to the base of the first transistor.
The emitter of the third transistor is connected to a common connection point of the emitters of the first and second transistors, and the collector of the third transistor is connected to a high-side power supply. In addition, the terminal of the third transistor is connected to the input terminal or the reference power source via a suitable resistor.

本発明第３図に示す実施例を用いて説明する。The present invention will be explained using an embodiment shown in FIG.

第３図（ａ）における本発明の第一の実施例においてに
、エミッタがトランジスタＱ１のベースに接続し、ベー
スがその工ξツタＶＣ＃続し、コレクタが電源Ｖｃｃに
接続されたトランジスタＱ８に−設けることによって、
入力端子ＩＮ側のトランジスタＱ１の工ばツタ−ペース
逆電圧葆護を行なう実施例である。同図で、入力端子Ｉ
Ｎの入力レベル、ＶＩＮが低下し、トランジスタＱ１’
ｏベース＝エミッタ逆方向電圧が、トランジスタＱａの
ベース＝エミッタ順方向電圧ＶＦに等しくなると、トラ
ンジスタＱがオンして、トランジスタＱａの工ぐツタ電
流が、電流制限抵抗ＲＢｔを通って、入力端子ＩＮから
流出する。従って、トランジスタＱｌのベース＝エミッ
タ逆方向電圧はＶＦ以上にならない。尚、トランジスタ
Ｑａのエミッタ電流ＩＢ３は、 Ｉｎ５＝（Ｖｎ−２Ｖｐ−ＶｒＮ）／ＲＢ１　とする。In a first embodiment of the invention in FIG. 3(a), the emitter is connected to the base of transistor Q1, the base is connected to the transistor Q8 whose collector is connected to the power supply Vcc. -By providing,
This is an embodiment in which the transistor Q1 on the input terminal IN side is protected against reverse voltage. In the same figure, input terminal I
The input level of N, VIN, decreases and transistor Q1'
o When the base-emitter reverse voltage becomes equal to the base-emitter forward voltage VF of the transistor Qa, the transistor Q is turned on and the trickling current of the transistor Qa passes through the current limiting resistor RBt and reaches the input terminal IN. flows out from Therefore, the base-emitter reverse voltage of transistor Ql does not exceed VF. Note that the emitter current IB3 of the transistor Qa is set as In5=(Vn-2Vp-VrN)/RB1.

以上の様に、本発明によれば、トランジスタのペース＝
工ばツタ逆方向電圧を検知し、同電圧を、ある値以上に
ならない様直接りラングする為、どの様な基準電圧■几
を用いても同様の効果を発揮する。As described above, according to the present invention, the pace of the transistor =
Since the reverse voltage is detected and the voltage is directly controlled so that it does not exceed a certain value, the same effect can be achieved no matter what reference voltage is used.

第３図［有］）における本発明の他の実施例ではトラン
ジスタＱ３を差動部のトランジスタＱ２側に設けて基準
電圧源側のトランジスタＱ２のベース；エミッタ逆電圧
保護を行なうようにしている。同図の如く、トランジス
タＱ３により、トランジスｚＱｚのペース＝エミッタ逆
電圧をＶＦ以上にならない様にクランプし、トランジス
タＱ　３　（７）ＯＮＩＩ（流は、抵抗ＲＢ２を介して
、基準電圧源、ＶＲｇｐＫ流出する。In another embodiment of the present invention shown in FIG. 3, a transistor Q3 is provided on the transistor Q2 side of the differential section to provide base-emitter reverse voltage protection for the transistor Q2 on the reference voltage source side. As shown in the figure, the transistor Q3 clamps the pace-emitter reverse voltage of the transistor zQz so that it does not exceed VF, and the transistor Q3 (7) ONII (current flows from the reference voltage source VRgpK through the resistor RB2 do.

更に、第４図に、入力側及び基準電圧側相方のトランジ
スタを過大なベース＝エミッタ逆方向電圧印加から防止
する事を目的とした他の実施例で、トランジスタＱ３．
Ｑ４により、トランジスタＱｌ。Furthermore, FIG. 4 shows another embodiment of the invention aimed at preventing excessive base-emitter reverse voltage from being applied to the transistors on the input side and the reference voltage side, transistor Q3.
Q4 causes transistor Ql.

Ｑ２のベース＝エミッタ逆方向電圧をクランプしている
。尚、トランジスタＱ４のエミッタ電流制限抵抗は、基
準電圧発生用抵抗Ｒｘ、Ｒ２の内、抵抗Ｒ２にて代用し
ている。The base-emitter reverse voltage of Q2 is clamped. Note that the emitter current limiting resistor of the transistor Q4 is substituted by the resistor R2 of the reference voltage generating resistors Rx and R2.

以上の様に、本発明によれば、基準電源電圧の値の如何
に係らず、又、入力端子側、基準電源側倒れのトランジ
スタに対しても適用し得る汎用性の高いベースにエミッ
タ逆方向電圧抑制を行なう事が出来る。As described above, according to the present invention, the emitter is placed in the opposite direction on the base, which is highly versatile and can be applied to transistors that are oriented on the input terminal side or on the reference power source side, regardless of the value of the reference power supply voltage. Voltage suppression can be performed.

本発明は、Ｃ−ＭＯ８ＩＣの出力を入力とする電流切換
型論理回路の様に、入力レベルが高位側電源電圧値から
接地レベルまで、大きく振れる様な場合に、入力部分の
トランジスタｖｃ過大なエミッタ＝ペース逆方向電圧が
加わる事を有効に防止できる為、各種ＩＣ混用システム
に使用する電流切換型論理ＩＣｖｃ特に好適である。The present invention is applicable to a current-switching logic circuit that uses the output of a C-MO8IC as an input, in which the input level fluctuates widely from the high-side power supply voltage value to the ground level. Since it can effectively prevent the application of pace reverse voltage, it is particularly suitable for current switching type logic ICvc used in systems that use various ICs.

尚以上の説明では、単一人力について述べたが、多入力
及び、相補入力を有する場合でも同様に適用し得る事は
明らかである。In the above explanation, the explanation was given regarding a single person's power, but it is clear that the present invention can be similarly applied to cases with multiple inputs and complementary inputs.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来の回路を示す図、第３図（ａ
）、　（ｂ）および第４図は本発明の実施例を示す図で
ある。 工Ｎ：入力端子、　ＶＲＩ！ＩＦ：基準電圧綜、几し：
負荷抵抗、Ｉｃ：定電流源、Ｑｌ−Ｑ４　：　）ニアｙ
ジスタ、Ｄｌ：ダイオード、ＲＢＪＩ！”’−）？Ｂ２
　；電流制限用抵抗、Ｖｃｃ　：高位側電圧源、几ｔ、
Ｒ２：基準電圧発生冶　１　回 第　Ｚ　閏Figures 1 and 2 are diagrams showing conventional circuits, and Figure 3 (a
), (b) and FIG. 4 are diagrams showing embodiments of the present invention. Engineering N: Input terminal, VRI! IF: Reference voltage adjustment:
Load resistance, Ic: Constant current source, Ql-Q4: ) Near y
Dista, Dl: Diode, RBJI! ”'-)?B2
; Current limiting resistor, Vcc: High voltage source,
R2: Reference voltage generator 1st Z leap

Claims (1)

【特許請求の範囲】[Claims] エミッタを相互に結合した第１及び第２のトランジスタ
によ）構成される電流切換型論理回路に於いて、該第１
のトランジスタのベースに第３のトランジスタのエミッ
タを接続し、該第３のトランジスタのベースを該第１及
び第２のトランジスタのエミッタ共通接続点に接続し、
更に該第３のトランジスタのコレクタを高位側電源に接
続すると共に、該第３のトランジスタのエミッタヲ、適
当な抵抗を介して、入力端子又は基準電圧源に接続した
事を特徴とする電流切換型論理回路。In a current switching type logic circuit constituted by first and second transistors whose emitters are coupled to each other, the first
connecting the emitter of a third transistor to the base of the transistor, and connecting the base of the third transistor to a common connection point of the emitters of the first and second transistors;
Furthermore, the collector of the third transistor is connected to a high-level power supply, and the emitter of the third transistor is connected to an input terminal or a reference voltage source via a suitable resistor. circuit.
JP57121587A 1982-07-13 1982-07-13 Current switching type logical circuit Granted JPS5912626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57121587A JPS5912626A (en) 1982-07-13 1982-07-13 Current switching type logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57121587A JPS5912626A (en) 1982-07-13 1982-07-13 Current switching type logical circuit

Publications (2)

Publication Number Publication Date
JPS5912626A true JPS5912626A (en) 1984-01-23
JPH0261820B2 JPH0261820B2 (en) 1990-12-21

Family

ID=14814930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57121587A Granted JPS5912626A (en) 1982-07-13 1982-07-13 Current switching type logical circuit

Country Status (1)

Country Link
JP (1) JPS5912626A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029007A (en) * 1983-07-27 1985-02-14 Mitsubishi Electric Corp Output circuit
US6274519B1 (en) * 1997-08-21 2001-08-14 Michiko Omori Food wrapping cloth

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175856A (en) * 1982-04-07 1983-10-15 Mitsubishi Electric Corp Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175856A (en) * 1982-04-07 1983-10-15 Mitsubishi Electric Corp Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029007A (en) * 1983-07-27 1985-02-14 Mitsubishi Electric Corp Output circuit
JPH0249563B2 (en) * 1983-07-27 1990-10-30 Mitsubishi Electric Corp
US6274519B1 (en) * 1997-08-21 2001-08-14 Michiko Omori Food wrapping cloth

Also Published As

Publication number Publication date
JPH0261820B2 (en) 1990-12-21

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