JPS60217727A - Logic circuit - Google Patents

Abstract

PURPOSE:To prevent surely malfunction or damage due to undershoot voltage by providing a voltage clamp circuit comprising an active circuit which prevents an output voltage from going to an opposite polarity to the polarity of a power supply voltage. CONSTITUTION:When a voltage of a logic output OUT is about to go to the negative polarity in a bipolar logic circuit such as TTL where the input and output are coupled in terms of DC, a clamp current Ic flows from an emitter of a transistor (TR)Q8 to the logic output OUT, the voltage at the output OUT is boosted and the output voltage is clamped actively at the positive polarity. Even if any undershoot is caused in the output voltage, since the voltage is limited to the clamp voltage, malfunction or damage due to the said undershoot voltage is prevented surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology that is particularly effective when applied to logic circuit technology and TTL.

[Background technology]

For example, the scimit key T, which is often used in logic circuits.
As shown in FIG. 1, TL is bipolar transistors Q1 to Q6 and a diode DI.

D2, and resistors R1 to R6, etc. (
Integrated Circuit Engineering (2) p. 76: Corona Publishing: Published April 30, 1981). Here, transistors Ql, Q2 . Q3
．． Q4. The Q6 has a built-in circuit key barrier diode that connects in the forward direction from the pace to the collector.

This is a so-called Schottky transistor.

The scimit key TTLIO shown in FIG. 1 has two logic inputs A, B and one logic output OUT, and is connected to the positive power supply V.
Since power is supplied from cc (5V) and ground potential (OV), it operates as a two-manpower NAND circuit.

By the way, this type of bipolar logic circuit is often used particularly as an output buffer circuit because its output can easily have a large current driving power. Therefore, its output OU
In many cases, an inductive load Ls due to an inductance component such as a cable or inter-board wiring is connected to T with equal restrictions.

However, the logic output 0UTK some kind of inductive load L
When s is connected, for example, in the TTLIO shown in FIG. 1, as shown in FIG. 2, the state of the logic output OUT is switched from "H" to "L"K. The voltage Vo momentarily swings significantly to the negative side, resulting in a so-called negative overshoot voltage -Vp. This overshoot voltage -Vp is generated when the logic state of "H", in which the current Io discharged from the output OUT flows, changes to the "L II" logic state, in which the sinking current If flows into the output OUT, in FIG. The current flowing through the inductive load Ls connected to the output 0UTK suddenly changes, and this change causes an inductive phenomenon.The underarm voltage Vp generated due to this change is caused by the operating speed of the TTLIO. The faster it goes, the more noticeable it becomes.

On the other hand, a bipolar logic circuit such as the above-mentioned Schottky TTLIO often has its input side and output side coupled with direct current.

For example, in the Schottky TTLIO shown in FIG.
The base of the input side transistor Q1 is connected to the transistor Q1.
1, the base-emitter forward direction of the 9-phase splitting transistor Q2, and the built-in Schottky barrier diode of the output-side Schottky transistor Q5 in the forward direction, respectively. There is.

However, since the connection direction is unidirectional, only from the input side to the output side, under normal operating conditions, the output OU
There is no possibility that the state of T will feed back to the input side and cause problems such as disturbing the operation.

However, when the undershoot voltage -Vp as mentioned above appears at the output 0UTK, at that moment the output OUT
The voltage Vo becomes significantly negative with respect to the input side, and this causes an abnormal current Ix to flow from the input side toward the output OUT, as shown by the arrow in Figure 1.
It becomes like this.

The inventors of the present invention have found that this causes a problem in that instantaneous malfunctions occur, and in some cases, the TTLIO itself may even be destroyed.

Therefore, the present inventors developed a technique of inserting a clamping Schottky barrier diode Dc in parallel to the output OUT to limit the undershoot voltage -vp, as shown by the dotted line in FIG. It's arrived.

According to this K, as shown in FIG.
The amplitude of the neat voltage -Vp, especially the amplitude to the negative side, can be limited to below the Schottky barrier diode DcO forward voltage -Vf.

However, even with this technology, the limiting voltage of the undershoot voltage -vp, that is, the clamp value (-V
The inventors have clarified that f) is still high and that it is still insufficient to solve the above-mentioned problems.

In other words, it has been found that in order to solve the above-mentioned problems, it is necessary to further significantly lower the clamp value (-Vf).

However, the Schottky barrier diode D
In order to reduce the forward voltage of the Schottky barrier diode Dc, the barrier area of the Schottky barrier diode Dc must be made extremely large. This is extremely difficult.

This invention was made in view of the above background.

[Purpose of the invention]

It is an object of the present invention to reduce overshoot voltages occurring at the output of bipolar logic circuits such as Schottky TTLs to a level significantly greater than that achieved with conventional Schottky barrier fog diodes, without resulting in a significant increase in area. The purpose of the present invention is to provide a technique that makes it possible to limit the undershoot voltage to a low level, thereby reliably preventing malfunctions or damage caused by the undershoot voltage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Overview of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by limiting the abnormal voltage amplitude at the output of a bipolar logic circuit such as a Schottky TTL with an active voltage clamp circuit, the undershoot voltage generated at the output of the logic circuit can be reduced by significantly increasing the area. Normal Schottky barrier without
It is possible to limit the voltage to a level significantly lower than that achieved with a diode, thereby ensuring that malfunction or damage caused by the undershoot voltage is prevented. This goal is achieved.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 3 shows a first embodiment of a logic circuit according to the invention.

The logic circuit shown in the figure is a Schottky TTLIO in which the input A, B side and the output OUT side are DC-coupled, and the voltage Vo at the output OUT of this TTLIO is opposite to the polarity side of the power supply voltage Vcc. The present invention is characterized in that it is provided with a voltage clamp circuit 20 that limits the swing to polarity (2), and that this voltage clamp circuit 20 is constituted by an active circuit using an emitter follower.

To explain the circuit shown in FIG. 3 in more detail, first, Schottky TTLIO is composed of bipolar transistors Q1 to Q6, diodes DI and D2, resistors R1 to R6, and the like. Here, transistors Ql, Q2°Q3. Q4. Q6 has a built-in Schottky barrier φ diode connected in the forward direction from the pace to the collector. This is a so-called Schmitt key transistor. It also has two logic inputs A and B and one logic output OUT, and is supplied with power from the positive power supply Vc c (5Vl and ground potential (OV)), allowing two-man power NA
It operates as an ND circuit.

Next, the voltage clamp circuit 20 is composed of a bipolar transistor Q8, a resistor R6, and a Schottky barrier diode D3. transistor Q8
constitutes an emitter 7 lower, whose collector is connected to the power supply Vc
c, their emitters are respectively connected to the output OUT of the TTLIO. Also, resistor R6 and diode D
3 is connected between the series-connected power supply Vcc and the ground potential, so that the forward voltage V of the diode D3 is
A constant voltage corresponding to f3 is generated. This constant voltage (Vf3
) is given to the pace of the emitter follower transistor Q8.

As a result, the emitter and peak voltages of the transistor Q8 vary from the forward voltage Vf3 of the diode D3 to the transistor Q8.
Voltage (V
f3-Vbe8). Therefore, the voltage Vo at the logic output OUT is the voltage (Vf3-Vb
When trying to swing to the negative side than e8), the transistor Q
A clamp current Ic is applied from the emitter of 8 to the logic output OUT side.
flows out, thereby raising the voltage at the output OUT to the above voltage (Vf3-Vbe8). □In other words, the voltage Vo at the output OUT is the voltage (
(2) It is actively clamped to the positive side of f3-Vbe8).

Therefore, as shown in FIG. 4, the logic output OUT is 'H'
In the process of switching from the logic state of ``L'' to the logic state of
Even if Vp is about to occur, this undershoot voltage -
Vp is the clamp voltage (V f 3 - V'b
e 8 ).

Here, the forward voltage Vf3 of the Schottky barrier diode D3 is set to 0.5 V, and the emitter-to-lid voltage Vbe of the emitter follower transistor Q8 is set to 0.5 V.
8 is 0.75V, the above clamp voltage (Vf3-
Vbe8) can be a low voltage of -0.25V. In other words, the negative swing of the voltage Vo at the logic output OUT can be clamped to -0.25V or less.

This value (0,25■) is the standard Schottky barrier.
This is only about half of the value (0.5V) obtained using the diode alone.

Incidentally, given the above value (0.25V), the barrier area of the Schottky barrier diode will be as follows.

That is, the forward voltage Vf of the Schottky barrier diode can be determined as follows.

First, the following equation (11 (21) is given.

V f-:KT/q #1 n (1f/I o+1
) --(I n = KT/q ・I n (l f/I
o) \However, If) > Io (2) Note that Io is a dark current, and Io = AST2 exp (-φb/KT).

Here, K is Boltzmann's constant and T is the absolute temperature.

q is the electronic charge, If is the forward current flowing through the Schmittky barrier diode, A is the barrier area of the Schottky barrier diode, S is Richard Non's constant, and -φb is the height of the barrier.

The following calculation formula is obtained from the above formula (11 (21).

Vf=KT/q @In (l f/(AST” ex
p(-φb/KT))") = 2.3X26mVX10g(If/AST"exp
(-φb/KT))) From the above formula, if the barrier area A is multiplied by 10, Vf is 6
If the person decreases by 0mV and increases the number of people by 100 times, Vf becomes 120mV.
descend.

In other words, the forward voltage Vf of the Schottky barrier diode is approximately 0. In order to lower the IV, the barrier area must be increased by 100 times. Therefore, in order to lower the forward voltage Vf from 0.5V to 0.25V, it becomes necessary to increase the barrier area by tens of thousands of times. In other words, in the embodiment shown in FIG. 3, it is possible to achieve a low clamping value that can only be achieved by a Schottky transistor with a barrier area tens of thousands of times larger than that of a normal Schottky transistor, with a significant increase in the area where the resistor is formed. It can be obtained easily without any complications. This reduces the undershoot voltage that occurs at the output of bipolar logic circuits such as Schottky TTL.
It can be limited to significantly lower levels than achieved with conventional Schottky barrier diodes without significantly increasing area, thus ensuring that malfunctions or damage caused by such undershoot voltages are prevented. It is possible to obtain the following effect.

FIG. 5 shows a second embodiment of the logic circuit according to the invention.

The logic circuit shown in the figure is also a Schottky TTLIO, and the input circuit portion 12 is a Schottky transistor QI.
IA, QI IB, Ql 2, Simitz key barrier
Diode Di IA, DI IB1 Resistor R11, R1
2 and the like is the same as that shown in FIG. 3.

The voltage clamp circuit 20 connected to the logic output OUT is the same as the one in FIG. 3 in that it uses an emitter follower formed by the transistor Q8, but the constant voltage applied to the base of the transistor Q8 is This is generated by R6 and transistor Q9. The collector and base of this transistor Q9 are connected to each other, and the resistor R
6 to the power supply Vc cK. The voltage appearing at the collector and base, which are connected to each other, is applied to the base of the emitter follower transistor Q8. As a result, the base-emitter voltage Vbe9 of the transistor Q9 is applied to the base of the emitter follower transistor Q8. Therefore, as shown in FIG. 6, the voltage Vo at the logic output OUT is equal to the voltage (Vb
e9-Vbe8). Here, both transistors Q8. If the characteristics of Q9 are made to be the same, the voltage (Vbe9-Vbe8) will be almost Ov.
can be approached. As a result, it becomes possible to easily and reproducibly obtain a very ideal lamp voltage for achieving the object of the present invention.

〔effect〕

(1) In a bipolar logic circuit whose input side and output side are DC-coupled, a voltage clamp circuit is used to limit the voltage at the output of this logic circuit from swinging to the opposite polarity to the polarity of the power supply voltage. In addition, by configuring this voltage clamp circuit with an active circuit, the undershoot voltage that occurs at the output of a bipolar logic circuit such as a Schottky TTL can be suppressed by using a normal Schottky barrier diode without significantly increasing the area. This has the effect of reliably preventing malfunctions or damage caused by the undershoot voltage.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the emitter follower of the voltage clamp circuit may be a source follower formed by an MO8 field effect transistor.

[Application field]

The above explanation will mainly focus on the Schottky TTL, which is the application field that is the background of the invention made by the present inventor.
Although the case where the present invention is applied to the above technology has been described, the present invention is not limited thereto, and can be applied to other logic circuits as well. It can be applied to bipolar logic circuits in which at least the input side and the output side are DC-coupled.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a logic circuit studied prior to the present invention, FIG. 2 is a diagram showing an example of a state of change in the output voltage of the logic circuit of FIG. 1, and FIG. 3 is a diagram showing a logic circuit according to the present invention. FIG. 4 is a diagram showing an example of the output voltage change state of the logic circuit of FIG. 3; FIG. 5 is a diagram showing a second embodiment of the logic circuit according to the present invention; FIG. 6 is a diagram showing an example of a state of change in the output voltage of the logic circuit shown in FIG. 5. 10...Logic circuit (TTL), 12...Input circuit portion of logic circuit, 20...Voltage clamp circuit, Q1-Q
9. QI IA, QI IB, Ql 2... Bipolar transistor, R1 to R6, R11, R12... Resistor, DC... Short key barrier diode for voltage r2 amplifier, DI, D2. D3. DIIA, DIIB...
・Schottky barrier diode, A, B...logic input, OUT...logic output, Vcc...power supply, I
O...Discharge current, Ii...Sink current, Ic...
・Clamp current, Ix...abnormal current, ■0...voltage at logic output, vp...overshoot voltage,
-Vf. Vf3...Forward voltage of diode Dc, Vbe8°Vbe9...Base-emitter voltage of bipolar transistor, Ls...Inductive load. Figure 1 Figure 2 VP Figure 3 Figure 4 VP Figure 5 Z Figure 6

Claims (1)

[Claims] 1. A bipolar logic circuit whose input side and output side are DC-coupled, which limits the voltage at the output of this logic circuit from swinging to the opposite polarity with respect to the polarity of the power supply voltage. 1. A logic circuit characterized in that the voltage clamp circuit is provided with a voltage clamp circuit, and the voltage clamp circuit is constituted by an active circuit. 2. The logic circuit according to claim 1, wherein the active circuit is an emitter follower.