JPH0359609B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level conversion circuit that converts a CML level to a positive level such as a TTL level, and particularly to an output short-circuit protection circuit thereof.

Since both the H (high) and L (low) levels of the CML (current mode logic) level are negative potentials and have small amplitudes, they cannot be directly connected to a positive level logic circuit such as TTL (transistor logic). Therefore, in order to connect or exchange the two, a level conversion circuit that converts the CML level to the TTL level is required. This type of circuit generally consists of a current switch that takes the CML level as one input and operates on both positive and negative power supplies, and an emitter follower transistor in the output stage that receives one output and outputs a binary level of positive and ground potentials. It is composed of the main parts. However, this circuit has the disadvantage that if an accident occurs where the emitter of the transistor in the output stage, and therefore the output terminal, is shorted to ground potential while in the H level output state, an overcurrent will flow and the transistor will be thermally destroyed. .

The present invention provides an output short-circuit protection circuit to improve this point, and this will be explained in detail below with reference to the illustrated embodiments.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
T ₁ and T ₂ are a pair of transistors that form the main parts of the current switch (differential amplifier) 1. The emitters of transistors T ₁ and T ₂ are commonly connected and further connected to a negative power supply -V _EE via a constant current source J ₁ . The base of transistor T ₂ has a reference voltage V _BB (−1.3V)
is supplied, and the base of transistor _T1 is
CML mode input V _IN (H=-0.8V, L=-
1.7V) is supplied. and transistor T ₁ ,
Each collector of T ₂ is connected to the positive power supply +V _CC through load resistors R ₁ and R ₂ . In a general level conversion circuit, the output is output to one side of current switch 1, for example, N ₁
is applied to the output stage transistor _T3 , and the TTL level output is output from its emitter, and therefore output terminal 2.
Take out V _OUT . For example, when V _IN = -0.8V, transistor T ₁ is on and T ₂ is off, and current flows to output terminal 2 through the base and emitter of transistor T ₃ along the path +V _CC -R ₁ -T ₃ . The transistor T ₃ is turned on and V _OUT V _CC −V _BE3 . . . (1). This is the H level in TTL mode,
It is at a positive level. Note that V _BE3 is the potential between the base and emitter of the transistor _T3 . Also, V _IN = −1.7V
Then, transistor T ₁ is turned off, T ₂ is turned on, and current J ₁ flows through resistor R ₁ , so that V _OUT V _CC −R ₁ J ₁ −V _BE3 ……(2). This is the L level of TTL mode,
Generally designed to be 0V. Therefore, even if the output terminal 2 is short-circuited to the ground potential GND, no overcurrent will flow through the transistor _T3 .
However, if output terminal 2 is short-circuited to ground potential when V _OUT is at the above level, an unlimited current will flow from the power supply +V _CC to output terminal 2 through the collector and emitter of transistor T ₃ . Transistor _T3 is thermally destroyed due to this overcurrent.

In order to prevent this problem, the present invention provides an output short-circuit protection circuit 3 consisting of transistors T ₄ and T ₅ , resistors R ₃ and R ₄ and a diode Dn. It is for protection of transistor _T4 , and its collector and emitter are connected to the base and emitter of transistor _T3 , respectively. Resistors R ₃ and R ₄ and one or more diodes Dn are connected in series between the power supply +V _CC and the ground potential GND (this may be another constant voltage element, such as a Zener diode, etc., and temperature compensation must be considered. (for example, a resistor may be used) constitutes a bias circuit 4, which applies the potential _VX at the connection point between the resistors _R3 and _R4 to the base of the transistor _T4 . The transistor _T5 is for bias voltage switching, and its collector and emitter are connected to the base of the transistor _T4 and the ground potential GND, respectively. The resistor R ₂ is the load of the transistor T ₁ mentioned above, and the other output N ₂ of the current switch 1 is connected to the transistor T 1.
Control the base potential of _T5 .

According to the above configuration, V _IN is at CML level H(-
0.8V), when transistor T ₁ is turned on, current flows through the base and emitter of output stage transistor T ₃ as described above, and V _OUT is shown in equation (1).
It becomes H at TTL level. At this time, the potential at the point _N2 is low and the transistor _T5 is off, so the voltage _VX determined by the voltage division ratio of the bias circuit ₄ is applied to the base of the transistor T4. This voltage is _V
Since V _CC −V _BE3 , at this point the transistor
T ₄ is off and does not affect the operation of transistor T ₃ . However, when the output terminal 2 is short-circuited to the ground potential GND, the emitters of the transistors T ₃ and T ₄ are grounded, so that they suddenly try to shift to the completely on region. If transistor T ₃ is completely turned on, an unlimited current will flow along the path +V _CC −T ₃ −2, or at this time, transistor T ₄ will be turned on and its collector current will be V _CC −R ₁ −T ₄ As a result, the base current of the transistor _T3 decreases rapidly, and finally it becomes unable to maintain the on state. Therefore, thermal breakdown of the transistor _T3 is prevented. Furthermore, since the current flowing through the transistor T ₄ is limited by the resistor R ₁ ,
There is no risk of destruction with transistor T ₄ .

On the other hand, when V _IN is at the CML level L (-1.7V), the transistor T ₁ is off and T ₂ is on, and the output V _OUT is at the TTL level L shown in equation (2) above.
This value is _normally 0V _, so if its base _potential is the _above -mentioned V
cannot be migrated to). However, in this circuit, at this time
Since the potential at point _N2 is high and therefore transistor _T5 is turned on, _the base of transistor _T4 is forcibly grounded, regardless of other conditions.
remains off. For this reason the transistor
There is no problem with the operation of _T3 .

As described above, the present invention has the advantage of being able to prevent element destruction due to short-circuit accidents in the output stage of the level conversion circuit with a simple circuit configuration. Note that this level conversion circuit can convert the CML level to an appropriate positive level, and the positive level is not limited to the TTL level.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1 is a differential amplifier, 2 is an output terminal, 3 is an output short circuit protection circuit, 4 is a bias circuit, _T3 is an output stage transistor, _T4 is a protection transistor,
_T5 is a bias voltage switching transistor.

Claims (1)

[Claims] 1 Consists of a pair of transistors whose emitters are commonly connected, each collector is connected to a positive power supply via a load resistor, and the commonly connected emitters are connected to a negative power supply via a constant current source,
Further, there is a differential amplifier 1 to which a negative reference voltage is supplied to one base and a CML level input to the other base, and a differential amplifier 1 whose output is supplied to the collector of one of the pair of transistors. One output level is supplied to the base, and the collector is connected directly to the positive power supply and the emitter is connected to the output terminal to provide high and low levels.
an output stage transistor _T3 that outputs a value level;
It consists of a protection transistor _T4 whose collector and emitter are respectively connected to the base and emitter of the output stage transistor, a resistor and a constant voltage element connected in series between the positive power supply and the ground potential, and the base of the protection transistor. a bias circuit 4 which applies a bias voltage to the differential amplifier; the output level of the other differential amplifier is supplied to the base; and the collector and emitter of the protective transistor are connected to the base and ground potential of the protective transistor, respectively. A bias voltage switching transistor _T5 is provided, and when the output terminal is short-circuited to the ground potential side when the output terminal is at a high level, the voltage is supplied from the positive power supply through the load resistor _R1 and the protective transistor _T4 . 1. A level conversion circuit equipped with an output short-circuit protection circuit, characterized in that a short-circuit current is supplied to the output terminal to protect a transistor in an output stage.