JPH033658A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH033658A
JPH033658A JP13866789A JP13866789A JPH033658A JP H033658 A JPH033658 A JP H033658A JP 13866789 A JP13866789 A JP 13866789A JP 13866789 A JP13866789 A JP 13866789A JP H033658 A JPH033658 A JP H033658A
Authority
JP
Japan
Prior art keywords
diode
circuit
power supply
capacitor
diodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13866789A
Other languages
Japanese (ja)
Other versions
JP2522054B2 (en
Inventor
Masayuki Hattori
雅之 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1138667A priority Critical patent/JP2522054B2/en
Publication of JPH033658A publication Critical patent/JPH033658A/en
Application granted granted Critical
Publication of JP2522054B2 publication Critical patent/JP2522054B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To enable obtaining a constant ON-state resistance by making it possible to double the supply voltage of an output circuit through adding diodes to a boosting circuit. CONSTITUTION:An oscillation circuit 10 is driven by an electric-supply line 9. The output of the oscillation circuit 10 is connected with an output circuit 12 via a series circuit of an inverter 3, capacitor 4 and diodes 7, 8; a capacitor 5 is connected between the input ene of the inverter 3 and the connection of the diodes 7, 8; and both ends of the diode 7 are respectively connected with the power-supply line 9 via Zener diodes 1, 2. Also, the both ends are further connected with an electric-supply line 11 via Zener diodes 13, 14. Therefore, a higher voltage out of voltages of the electric-supply lines 9, 11 is applied to the both ends of the diode 7 so as to be capable of being further boosted to twice the supply voltage. Thus, it is possible to obtain an almost constant ON-state resistance independent of the supply voltage of the output circuit 12.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にＮ型電界効果トランジ
スタ４個で構成されたＨブリッジ回路を出力段に持つモ
ータードライブ用半導体集積回路内で用いられる昇圧回
路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device for use in a motor drive semiconductor integrated circuit having an H-bridge circuit composed of four N-type field effect transistors in the output stage. This invention relates to a booster circuit.

〔従来の技術〕[Conventional technology]

従来この種の回路には、ダイオードとコンデンサと発振
回路を組み合わせた昇圧回路があった。Conventionally, this type of circuit has been a booster circuit that combines a diode, a capacitor, and an oscillation circuit.

すなわち第３図に示す様に、電源９で駆動される発振回
路１０の出力をインバータ３とダイオード７．８．１８
とを直列に介して出力回路１２のＮチャンネルトランジ
スタのゲートに接続するとともに、コンデンサ６を介し
て接地し、インバータ３の入力側とダイオード７と８と
の接続点との間にコンデンサ４を接続し、さらにインバ
ータ３の出力側とダイオード８と１８との接続点との間
にコンデンサ５を接続して、ダイオード１８とコンデン
サ６との接続点に昇圧された電圧を得ていた。That is, as shown in FIG.
are connected in series to the gate of the N-channel transistor of the output circuit 12, and grounded via the capacitor 6, and the capacitor 4 is connected between the input side of the inverter 3 and the connection point between the diodes 7 and 8. Furthermore, a capacitor 5 is connected between the output side of the inverter 3 and the connection point between the diodes 8 and 18, so that a boosted voltage is obtained at the connection point between the diode 18 and the capacitor 6.

この昇圧された電圧で例えば、Ｎ型電界効果トランジス
タ４個で構成された出力Ｈブリッジ回路を駆動していた
。This boosted voltage was used to drive an output H-bridge circuit composed of, for example, four N-type field effect transistors.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来技術の昇圧回路は、発振回路の電源電圧ｖ
０の３倍まで昇圧し出力Ｈブリッジ回路を駆動していた
。これは、Ｎ型電界効果トランジスタのオン抵抗を下げ
るため、出力回路の電源電圧ＶＭ　（ｖｃ）より昇圧す
る必要があるからである。具体的はＶ。が５ｖの場合昇
圧電圧は、ダイオードのｖ２電圧ドロップ３個分を加味
して１３Ｖ程度になりＶＭが５ｖの場合、出力回路を駆
動するのに十分な、電圧を得る。しかし■。よりＶＭが
高い場合、例えばＶｃが５Ｖ、ＶＭが１２Ｖの場合ｖＭ
からの昇圧電圧が１〜２ｖ程度になってしまいオン抵抗
が増加してしまう欠点がある。In the prior art booster circuit described above, the power supply voltage v of the oscillation circuit
The voltage was boosted to 3 times 0 to drive the output H bridge circuit. This is because in order to lower the on-resistance of the N-type field effect transistor, it is necessary to boost the power supply voltage VM (vc) of the output circuit. Specifically, V. When VM is 5V, the boosted voltage becomes about 13V, taking into account three v2 voltage drops of diodes, and when VM is 5V, a voltage sufficient to drive the output circuit is obtained. However ■. If VM is higher, for example, if Vc is 5V and VM is 12V, vM
There is a drawback that the boosted voltage from 1 to 2 V is about 1 to 2 V, and the on-resistance increases.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の昇圧回路は、第１の電源端子と、第１の電源端
子に接続された発振回路と、この発振回路の出力を受け
るインバータと、このインバータの出力を受ける第１の
コンデンサと第１及び第２のダイオードとの直列接続回
路と、この直列接続回路の出力に接続された出力端子及
び第２のコンデンサと、インバータの入力側と第１と第
２のダイオードの接続点の間に接続された第３のコンデ
ンサと、第１のコンデンサと第１のダイオードとの接続
点と第１の電源端子との間に接続された第３のダイオー
ドと、第１の電源端子と、第１及び第２のダイオードの
接続点との間に接続された第４のダイオードとを含む、
さらに第１の電源ラインとは別の第２の電源ラインと第
１のコンデンサと第１のダイオードとの接続点との間に
接続された第５のダイオードと第２の電源端子と第１及
び第２のダイオードの接続点との間に接続された第６の
ダイオードで構成されている。すなわち本発明の昇圧回
路は、従来電源とコンデンサを直接結んでいなかったも
のを、ダイオードを用いて接続し、フントロール電源Ｖ
。が出力回路の電源ＶＭより高い時ａｘｖｃにｖｏがｖ
Ｍより低い時ＶＭ＋２×ｖｏになる様にする。これによ
りモーター電圧ＶＭに無関係に常にＶＭより８ｖ程度高
い電圧で出力回路を駆動できる為、ＶＭに無関係に低オ
ン抵抗にする事ができる。又、本発明を用いるとダイオ
ードＶ、による昇圧電圧の低下は、従来回路と同一にで
きるため機能を追加することによる特性劣化は発生しな
い特徴をも合せ持つ。The booster circuit of the present invention includes a first power supply terminal, an oscillation circuit connected to the first power supply terminal, an inverter receiving the output of the oscillation circuit, a first capacitor receiving the output of the inverter, and a first capacitor receiving the output of the inverter. and a series connection circuit with a second diode, an output terminal connected to the output of this series connection circuit, a second capacitor, and a connection between the input side of the inverter and the connection point of the first and second diodes. a third capacitor connected between the first capacitor and the first diode, a third diode connected between the first power terminal and the first power terminal; a fourth diode connected between the connection point of the second diode;
Furthermore, a fifth diode connected between a second power supply line different from the first power supply line and a connection point between the first capacitor and the first diode, a second power supply terminal and the first and The sixth diode is connected between the connection point of the second diode and the second diode. In other words, the booster circuit of the present invention uses a diode to connect the power supply and the capacitor, which was not directly connected in the past.
. When VO is higher than the power supply VM of the output circuit, VO becomes VO on axvc.
When it is lower than M, it should be VM+2×vo. As a result, the output circuit can always be driven at a voltage about 8V higher than VM regardless of the motor voltage VM, so it is possible to achieve low on-resistance regardless of VM. Further, when the present invention is used, the reduction in the boosted voltage caused by the diode V can be made the same as in the conventional circuit, so that characteristic deterioration due to the addition of functions does not occur.

なお、第３．第４．第５．第６のダイオードとしてツェ
ナーダイオードを用いることができる。In addition, 3rd. 4th. Fifth. A Zener diode can be used as the sixth diode.

このように、従来の昇圧回路は、発振回路のコントロー
ル電源の３倍までしか昇圧できなかったのに対し、本発
明においては、ダイオードをさらに追加して、出力回路
の電源電圧を基準にさらにコントロール電源の２倍まで
の昇圧を可能にしている。こｈによりどの様な電圧を出
力回路の電源に用いようとも十分低いオン抵抗を実現で
きる。In this way, conventional booster circuits were only able to boost the voltage up to three times the control power supply of the oscillation circuit, whereas in the present invention, an additional diode is added to further control the power supply voltage of the output circuit. It is possible to boost the voltage up to twice the power supply. This makes it possible to achieve a sufficiently low on-resistance no matter what voltage is used for the power supply of the output circuit.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す昇圧回路の回路図であ
る。発振回路１０は電源ライン９で駆動されている。発
振回路１０の出力は、インバータ３、：Ｉンデンサ４．
ダイオード７、及びダイオード８の直列回路を介して出
力回路に接続されている。コンデンサ５はインバータ３
の入力端とダイオード７と８との接続点との間に接続さ
れている。FIG. 1 is a circuit diagram of a booster circuit showing one embodiment of the present invention. The oscillation circuit 10 is driven by a power supply line 9. The output of the oscillation circuit 10 is supplied to the inverter 3, the I capacitor 4.
It is connected to the output circuit via a series circuit of diode 7 and diode 8. Capacitor 5 is inverter 3
and the connection point between diodes 7 and 8.

ダイオード７の両端は、それぞれツェナーダイオード１
，２を介して電源ライン９に接続されている。又この両
端はツェナーダイオード３，４を介してさらに電源ライ
ン１１にも接続されている。Both ends of diode 7 are connected to Zener diode 1, respectively.
, 2 to the power supply line 9. Further, both ends thereof are further connected to a power supply line 11 via Zener diodes 3 and 4.

よってダイオード７０両端は電源ライン９及び１１のう
ち電圧の高い電位になるためこの電圧を基準にさらに電
源電圧の２倍までの昇圧可能になる。Therefore, both ends of the diode 70 have the potential of the higher voltage of the power supply lines 9 and 11, so that it is possible to further increase the voltage up to twice the power supply voltage based on this voltage.

第２図は本発明の他の実施例の回路である。基本動作は
第１の実施例の場合と同じであり、特にコンデンサー６
が短絡破壊した時の電源保護の為にツェナーダイオード
１．２及び３，４と電源ライン９．及び１１０間にそれ
ぞれ抵抗１６．１７及び１８．１９を入れている。この
様にすると第１の実施例の効果は変わりなくさらに電源
保護機能を含んだ昇圧回路を構成できる。FIG. 2 shows a circuit of another embodiment of the invention. The basic operation is the same as in the first embodiment, especially the capacitor 6.
Zener diodes 1.2, 3, and 4 and power supply line 9. Resistors 16.17 and 18.19 are inserted between and 110, respectively. In this way, the effects of the first embodiment remain unchanged, and a booster circuit that further includes a power supply protection function can be constructed.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明は、昇圧回路に新たにダイオ
ードを用いて発振回路のコントロール電源だけでなく、
出力回路の電源と昇圧回路を接続することにより、昇圧
電圧を第４図に示すように出力回路の電源ＶＭを基準に
さらにコントロール電源ｖ０の２倍まで昇圧することが
可能になる。As explained above, the present invention newly uses a diode in the booster circuit to provide not only the control power supply for the oscillation circuit, but also the
By connecting the power supply of the output circuit and the booster circuit, the boosted voltage can be further increased to twice the control power supply v0 based on the power supply VM of the output circuit as shown in FIG.

これにより出力回路にＮ型電界効果トランジスタ４個で
構成されたＨブリッジ回路を用いた時第５図に示す様に
従来の回路では出力回路の電源電圧が高くなると出力回
路のオン抵抗が急激に高くなるが本発明の回路は、出力
回路の電源電圧に依存せずほぼ一定のオン抵抗にする事
が可能になる。As a result, when an H-bridge circuit consisting of four N-type field effect transistors is used in the output circuit, as shown in Figure 5, in the conventional circuit, when the power supply voltage of the output circuit increases, the on-resistance of the output circuit increases rapidly. Although the on-resistance is higher, the circuit of the present invention can maintain an almost constant on-resistance regardless of the power supply voltage of the output circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図はそれぞれ本発明の一実施例及び他の実
施例による昇圧回路の回路図であり、第３図は従来技術
の昇圧回路の回路図である。第４図は昇圧時間と昇圧電
圧との関係を示す図であり第５図は出力回路の電源電圧
と出力回路のオン抵抗との関係を示す図である。 １・・・・・・（ツェナー）ダイオード、２・・・・・
・（ツェナー）ダイオード、３・・・・・・インバータ
ー　４・・・・・・コンデンサー　５・・・・・・コン
デンサー　６・・川・コンデンサー　７・・・・・・ダ
イオード、８・・・・・・ダイオード、９・・・・・・
電源ライン、１０・・・・・・発振回路、１１・・・・
・・電源ライン、１２・・・・・・出力回路、１３・・
・・・・（ツェナー）ダイオード、１４・・・・・・（
ツェナー）ダイオード、１５・・・・・・抵抗、１６・
・・・・・抵抗、１７・・・・・・抵抗、１８・・・・
・・抵抗。1 and 2 are circuit diagrams of a booster circuit according to one embodiment of the present invention and another embodiment, respectively, and FIG. 3 is a circuit diagram of a booster circuit of the prior art. FIG. 4 is a diagram showing the relationship between the boost time and the boost voltage, and FIG. 5 is a diagram showing the relationship between the power supply voltage of the output circuit and the on-resistance of the output circuit. 1... (Zener) diode, 2...
- (Zener) diode, 3... Inverter 4... Capacitor 5... Capacitor 6... River Capacitor 7... Diode, 8... ...Diode, 9...
Power line, 10...Oscillation circuit, 11...
...Power line, 12... Output circuit, 13...
・・・・・・(Zener) diode, 14・・・・・・(
Zener) diode, 15... Resistor, 16.
...Resistance, 17...Resistance, 18...
··resistance.

Claims (3)

【特許請求の範囲】[Claims] （１）第１の電源端子と、前記第１の電源端子に接続さ
れた発振回路と、この発振回路の出力を受けるインバー
タと、このインバータの出力を受ける第１のコンデンサ
と第１及び第２のダイオードとの直列接続回路と、この
直列接続回路の出力に接続された出力端子及び第２のコ
ンデンサと前記インバータの入力側と前記第１と第２の
ダイオードの接続点の間に接続された第３のコンデンサ
と、前記第１のコンデンサと前記第１のダイオードとの
接続点と第１の電源端子との間に接続された第３のダイ
オードと前記第１の電源端子と前記第１及び第２のダイ
オードの接続点との間に接続された第４のダイオードと
を含みさらに前記第１の電源ラインとは別の第２の電源
ラインと、前記第１のコンデンサと前記第１のダイオー
ドとの接続点との間に接続された第５のダイオードと前
記第２の電源端子と前記第１及び第２のダイオードの接
続点との間に接続された第６のダイオードを含むことを
特徴とする半導体装置。(1) a first power supply terminal, an oscillation circuit connected to the first power supply terminal, an inverter receiving the output of the oscillation circuit, a first capacitor receiving the output of the inverter, and first and second capacitors connected to the first power supply terminal; a series connection circuit with a diode, an output terminal connected to the output of this series connection circuit, and a second capacitor connected between the input side of the inverter and the connection point of the first and second diodes. a third capacitor; a third diode connected between a connection point between the first capacitor and the first diode; and a first power terminal; a fourth diode connected between the connection point of the second diode and a second power supply line that is different from the first power supply line; the first capacitor and the first diode; and a sixth diode connected between the second power supply terminal and the connection point of the first and second diodes. semiconductor device. （２）前記第３及び第４のダイオードと前記第１の電源
端子との間及び前記第５及び第６のダイオードと前記第
２の電源間に保護抵抗が接続されていることを特徴とす
る請求項１記載の半導体装置。(2) A protective resistor is connected between the third and fourth diodes and the first power supply terminal and between the fifth and sixth diodes and the second power supply terminal. A semiconductor device according to claim 1. （３）前記第３、４、５、６のダイオードがツェナーダ
イオードであることを特徴とする請求項１記載の半導体
装置。(3) The semiconductor device according to claim 1, wherein the third, fourth, fifth, and sixth diodes are Zener diodes.
JP1138667A 1989-05-30 1989-05-30 Semiconductor device Expired - Lifetime JP2522054B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1138667A JP2522054B2 (en) 1989-05-30 1989-05-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1138667A JP2522054B2 (en) 1989-05-30 1989-05-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH033658A true JPH033658A (en) 1991-01-09
JP2522054B2 JP2522054B2 (en) 1996-08-07

Family

ID=15227311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1138667A Expired - Lifetime JP2522054B2 (en) 1989-05-30 1989-05-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2522054B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0395655U (en) * 1990-01-11 1991-09-30
JP2006322821A (en) * 2005-05-19 2006-11-30 Hioki Ee Corp Impedance measuring instrument

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0395655U (en) * 1990-01-11 1991-09-30
JP2006322821A (en) * 2005-05-19 2006-11-30 Hioki Ee Corp Impedance measuring instrument
JP4695920B2 (en) * 2005-05-19 2011-06-08 日置電機株式会社 Impedance measuring device

Also Published As

Publication number Publication date
JP2522054B2 (en) 1996-08-07

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