JPS59125795U

JPS59125795U - display device

Info

Publication number: JPS59125795U
Application number: JP18508782U
Authority: JP
Inventors: 英昭林
Original assignee: 日本コロムビア株式会社
Priority date: 1982-12-07
Filing date: 1982-12-07
Publication date: 1984-08-24

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案の表示装置の系統図、第２図は第１図の
波形説明図、第３図は本考案の表示装置の他の実施例を
説明するための系統図、第４図は第３図の波形説明図、
第５図は本考案の表示装置をアダプタとした場合の斜視
図である。図中、Ｔ・・・・・・入力端子、Ａ・・・・・・増幅器
、ＰＭ・・・・・・ビークメータ、ＳＰ・・・・・・ス
ピーカ、■Ｒ□−１・ＶＲｌ−２、ＶＲ・・・・・・可
変抵抗器、ＰＤ□、　ＰＤ２．　ＰＤ３・・・・・・ピ
ーク検波器、Ｃ１，Ｃ２・・・・・・比較増幅器、Ｄ・
・・・・・遅延回路、Ｇ・・・・・・アンドゲート回路
、ＦＦ・・・・・・フリップフロップ回路、１・・・・
・・入力コネクタ、２・・・・・・出力端子、３・・・
・・・アダプタ。FIG. 1 is a system diagram of the display device of the present invention, FIG. 2 is a waveform explanatory diagram of FIG. 1, FIG. 3 is a system diagram for explaining another embodiment of the display device of the present invention, and FIG. 4 is the waveform explanatory diagram of Fig. 3,
FIG. 5 is a perspective view of the display device of the present invention used as an adapter. In the figure, T...Input terminal, A...Amplifier, PM...Beak meter, SP...Speaker, ■R□-1/VRl-2, VR...Variable resistor, PD□, PD2. PD3... Peak detector, C1, C2... Comparison amplifier, D.
...Delay circuit, G...AND gate circuit, FF...Flip-flop circuit, 1...
...Input connector, 2...Output terminal, 3...
···adapter.

Claims

[Scope of utility model registration request]

Comparing means for extracting and comparing levels on the input side and output side of the amplifier so that they are the same, and detecting means for detecting that the peak level on the output side of the amplifier has decreased by 1 compared to the peak level on the input side. A display device characterized in that the output of the detection means is added to the display device.