JPS59125127A - Transmitter - Google Patents

Abstract

PURPOSE:To eliminate the chattering effect of a display switch by providing a timer circuit which delivers an output for a period longer enough than the working time of the display switch. CONSTITUTION:When a display switch 16 is operated, a signal ''1'' is applied to a set terminal S of an FF19. Then the 1st timer signal is delivered from an output terminal Q. While the accumulated electric charge of a capacitor 21 is slowly discharged via a resistance 20. Then an inverter 25 delivers the signal ''1'' to a reset terminal R when the potential of the capacitor 21 is reduced less than a fixed level. Thus the terminal Q is inverted to ''0''. In this case, the chattering effect of the switch 16 can be eliminated since the time of the 1st timer is set longer enough than a period during which the switch 16 is kept on.

Description

[Detailed Description of the Invention] Technical Details This invention relates to a transmitter, and more particularly to a sign display device used in restaurants, coffee shops, etc., to inform staff of the sign (number, alphabet, etc.) of the seat (chiful) for which service is being requested. The present invention relates to a transmitter used and disposed on the seat.

Purpose The present applicant has proposed a sign display device@ in an earlier patent application (Japanese Patent Application No. 175054/1983, filed on October 5, 1982). With this device, when a customer activates the display switch on the transmitter, a unique signal is transmitted from the transmitter to the location where the clerk is waiting, and the number corresponding to the transmitted signal (seat number requesting service) is configured to be displayed.

With this system, the customer may activate the display switch many times in a short period of time, sending the same signal over and over again, and the chattering of the display switch may occur. Due to influence, the transmission is not ensured when 17!] Node is not resolved. Furthermore, the problem that the +a transmission is performed while the display switch is in operation increases the power consumption.

An object of the present invention is to ensure that transmission is performed for a predetermined period of time regardless of the time when the switch is activated on the display switch of the transmitter, and that the influence of chatter of the display switch is removed. The object of the present invention is to provide a transmitter that can perform transmission with 1% less power consumption.

Embodiment Hereinafter, one embodiment of the present invention will be described with reference to all the drawings, in which the present invention is embodied in a persimmon display device.

In a restaurant, coffee shop, etc., a transmitter 1 shown in FIG. 1 is placed on each chiffle (not shown). The transmission circuit 3 is installed on the machine base 2, and the POL!
A cover 5 made of an insulating material is fixed by 4, and an obstacle is formed between the lower edge of the cover 5 and the machine base 2. A pushbutton 8 is provided in the additional part of the cover 5 facing the transmitting circuit 3 so that it can be pressed down against the spring force of the compression spring 6. A pushbutton 7 regulates the pushbutton 8 to the raised position. The one-thread retainer 9 shown in FIG. , etc. ◇ fAt has a notch formed in such a manner that a stop piece 11 with good elasticity protrudes upwards.As shown in the fifth piece, a part 1 to 9 is inserted, the locking piece 11 folds and passes through the gap g, and the cover 5 is inserted.
When inserted into the interior, the engaging piece 11 projects upward again due to its own elasticity and is caught on the inner peripheral surface of the wall 5. For this reason, if the tip of the button 12 is fixed to a difle or the like, it becomes impossible to take out the transmitter 1 from the difle, thereby preventing theft.

Next, the transmitting circuit 3 will be explained according to FIGS. 4 to 8.

The negative terminal of the dry battery 14 in the mold circuit 13 is connected
1, the positive terminal of which is connected to a resistor 15, an indicator switch 16 operated by the press button 8, and a series 111 of resistors 11)
One of the roads is located on the ground. υE, when the display switch 16 is turned on for a time 'I' SW (exit), the voltage from both ends of the resistor 17 is 1' as shown in FIG. 5 (+L).
SW (second) t goke theory 1'l! A switch signal 5O8W which becomes I is output. That Sui Nochi Shin + f S (
-1S vV is 1st time 1), 8 flip-flop circuit (below, It S -F F time II
! I was surprised by the set terminal S of the old and one solo)L.

I (・8-F F loJ path 19 output terminal [) is open? is warmed through a series circuit of a resistor 20 and a capacitor 21, and a charging resistor 20 and a diode 2 are connected to the discharging resistor 20.
A series circuit with 3 is continued in parallel with 7. discharge resistance 20
The connection point between the capacitor 21 and the capacitor 21 is connected to the reset terminal R1 of the 1(,f'i-,1"I" circuit 19) via the resistor 24 and the inverter 25.

Separately stated, when S is logic 0, Its-FF circuit 1
The output terminal Q of 9 is reset to logic 1, and the capacitor 21 is charged via the charging resistor 22 and diode 23. The capacitor 210 is connected to the reset terminal H via the resistor 24 and the inverter 25 to provide a logic 0 signal. Now, the logic I switch signal 8U8 is applied to the seventh node terminal S'.
When W is applied, the first timer signal M, 801'F of logic 1 shown in FIG. 5(1) is output from the output terminal Q, and the output terminal becomes logic 0.

Due to the SOLT, the M product charge of the capacitor 21 is gradually discharged through the discharge resistor 20, and the voltage 4;l of the capacitor 21 gradually decreases. 1st timer time' gate (approximately 1
After 5 seconds to 90 seconds), when the output voltage of the controller 21 (q) becomes below a certain level, the inverter 25 sends a logic 1 signal to the reset terminal 1t, and the output terminal Q becomes logic 0 and the output Terminal Q is inverted to logic JIIi 1.

In this case, the first timer time 1'i'F (seconds) is set to be sufficiently longer than the time TOW (seconds) during which the display switch 16 is turned on, and regardless of the time during which the display switch 16 is turned on, the first timer time From the circuit 18, a first timer signal SC) which becomes logic 1 for a first timer time F (seconds);
1"F will be output. Also, during the first timer time TTF (seconds), the display switch 16 will be turned ON.
Even if the first timer signal 801'F is changed, it does not affect the first timer signal 801'F, and the influence of chattering of the display switch 16 can be eliminated.

), '[The first timer signal S GT F is assigned a value to the input terminal of the second timer circuit 26 configured similarly to the first timer circuit 18 , and the first timer signal S As shown in Figure 5 ((1), the necessary and minimum time for transmission is 1'T It, (approximately 0.7 seconds).
R is 114 times.

The transmission activation signal S('J'I'R) is applied to the activation display circuit 27 and the ITU power supply circuit 13.

To explain the operation display time 1 case 27, capacitor 2
8 and a resistor Z9 in series, a differential circuit is constructed, the terminal on the capacitor 28 side is connected to the output terminal of the second timer circuit 26, and the terminal on the resistor 29 side is grounded. Transmission activation signal S GT R7% From logic 0 to logic IK9 - Then, the light minute required to activate the transmission display element 31 and the minimum time (approximately 005 seconds) are applied to both ends of the resistor 29. Pulse signal S G , l with logic ■
t[J occurs. The operation display circuit 21 amplifies the pulse signal S (+ l' U by the amplifier circuit 30 and generates the operation display signal SC,I N I shown at 5N(tl).
), and the transmission display element 31 such as a buzzer is activated by the operation display circuits S G and rN D.

Therefore, it can be confirmed by the display signal such as vinegar that the display unit Y-16 has been activated. In order to reduce the power consumed by this operation indicator circuit 21 and extend the life of the dry cell battery 14, the operation indicator circuit 21 (S G I N
The transmission display time 1'lND at which D becomes logic 1 is made as short as possible. ), transmission activation signal S G i”R.

When the signal changes from logic 1 to logic 0, the pulse signal of negative current λγ generated across the resistor 29 is cut off by the amplifier circuit 30.

Next, the power source 1raku 13 will be explained. Both collector terminals of the front and rear stage I-runnostars 33 and 34 connected to Turlington are connected to the positive terminal of the dry battery 14, and the RU
The transmission activation signal SIG'l"lt is connected to the base terminal of the transistor 33 through a resistor 32. The emitter terminal of the transistor 34 at the second stage is connected to the positive terminal of a constant voltage diode 36 through a resistor 35. The negative terminal thereof is grounded. Note that a noise canceling capacitor 31 is connected in parallel to the constant voltage diode 36.

When the transmission activation signal S (1'l'lL) is added, both transistors 33 and 34 are turned on, and the constant voltage diode 36 is turned on.
Both ends become the constant voltage power supply terminals of the transmitter JC38, and the emitter terminal of the latter stage transistor 34 becomes the high-frequency oscillation terminal 11.
! It becomes a positive power supply terminal with δ39 and modulation amount of 1-heat 40. A transmitter IC 3B, a high frequency preorder circuit 39, a modulation circuit 40, etc. constitute a transmission radio wave emission circuit, and the transmission radio wave emission circuit receives a logic 1 transmission activation signal 80T It.
It operates during the time when 'r' is output.

Therefore, regardless of the time during which the display switch 16 is turned on, the transmission operation is performed in the necessary and minimum amount of time, reducing power consumption and extending the life of the dry battery.

T for transmitter (M501 made by Mitsubishi Heavy Industries as 33B), 5
Using XIF (product number), key input terminal 1
1 to ■6, 60 types of commands can be transmitted by connecting the scan output terminals φ1 to φ5 with 71 to It is possible to transmit various kinds of commands. The command word is set to correspond to the table number in which the transmitter 1 is installed. The command word t is sent from the output terminal of the transmitter IC 38 as shown in FIG.
-x PW is output as f'L. Its transmission signal 5lj
l'W is composed of 11 pulses, and logic 0 and logic 1 are distinguished from each other by the pulse interval IC.

In the case of logic 0, the pulse interval is short, and in the case of logic 1, the pulse interval is long, and in the example shown in Fig. 6, KOK, [K21) (II) 11) 21) 31) 41)
The 10-bit code 5D6=0001010000 constitutes the transmission debt 8Gl)W. This transmission phase 8
(), l'W are the transmission activation signal 8()T1. The logic L (!: fMI T'l' R at the time of null transmission) is outputted K 2 times. Also, one pulse P1 is made up of 4 pulses of 10 (111 pulses) of 5KI (Z) as shown in Fig. 7, and the pulse width of the pulse P1 is 1,
is 2…S(・(.

Furthermore, since it is modulated by 51 (+17), the power consumption and power during transmission are reduced.

The 6 high frequency oscillation circuit 39, which is a crystal oscillation circuit, is a 4Q AI
A carrier wave with a frequency of IIZ is output, and the carrier wave is sent to the modulation circuit 40 via the output lance 4B! be lost.

To explain the modulation circuit 40, 1. The output terminal of c3B is connected to TepNp via the container 42.
trq +- is connected to the base terminal of the runno star 44, and the base terminal is grounded through the resistor 43 J'
I'm L. Transistor 44 11: The vine terminal is 1&? 513, and its collector terminal is grounded via the container 45. At its collector terminal, an air-core coil-shaped Anoana 46 and a Konoten) Su 47 are connected.
One terminal of the parallel circuit with is connected.

The carrier wave from the high frequency amplifier circuit 39 is input to the base terminal of an NPN type h transistor 49, the collector terminal of which is connected to the center tap of the antenna 46, and the emitter terminal is grounded.

Therefore, the pulse P of 5Kr-IZ of the transmission signal S OPW
1, the transistor 44 is turned on and off, and 40M
B Z ty)
49; 7% ON and OFF, and the antenna 46 outputs a pulse P1 of 5KI-IZ at 40 A as shown in FIG.
A transmission radio wave E modulated with a carrier wave of 4J(-Z) is emitted.

Next, the receiver 50, which is placed in a place where a store clerk waits, will be explained with reference to FIGS. 9 to 11.

Transmission radio waves 13 emitted from each transmitter 1 propagate through space and are received by a receiving antenna circuit 51. Since the received signal 5ORE shown in FIG. 10(a) is weak, it is voltage amplified by the high frequency I width t [1 path 5:2. MO8 type transistors are used as the ItQ width elements of the high frequency amplifier circuit 52, which makes the input Innovecnos difficult. The amplified received signal SGR-E is attenuated by a frequency mixing circuit 53. A local oscillation circuit 54 consisting of a crystal oscillation circuit has a frequency of 1'+ (40
MH7) lower frequency “2(39.545 MHJZ
) is given to the frequency mixing circuit 53, and the frequency mixing circuit 53 receives the intermediate frequency signal carried at the intermediate frequency (1'+-r2=455KI-IZ) as shown in FIG. Outputs the signal SOx.

The intermediate frequency signal 80MF is amplified by the intermediate frequency amplification circuit 55 and applied to the detection circuits 5 and 7. The output of the intermediate frequency amplification circuit 55 is AOC (automatic gain measurement) i+7
1#%56 is fed back to the intermediate frequency amplification circuit 55 pJ, and the fluctuation of the input terminal level of the received signal 8() old': is fed back to the detection circuit 57 Ij f'
The L voltage level is prevented from fluctuating as much as possible.

The detection circuit 57 consisting of a diode detection circuit has an intermediate frequency 4q Q 5CnVI F (7) Hull 7, signal S G P 1
Perform k detection. This pulse signal 8() P i corresponds to the pulse 1'1 shown in FIG. 7, but is filled with high frequency (including intermediate frequency) noise. The pulse signal 5OP1 is applied to the limiter circuit 58, and the pulse signal 5OP1 is applied to the limiter circuit 58.
Figure 10 (tl) K 7T<11t made by waveform
It outputs the pulse signal IT S GP 2. In addition,
The limiter circuit 58 is configured using a differential amplifier (OPE-AMP). However, this pulse signal S
G,2 may include high-frequency pulse noise when the high-frequency noise voltage included in the pulse (N@8GP1) is large.Therefore, the pulse signal SG2 is
]0 to V-PASSI filter circuit 52,
Cylindrical frequency components are cut. Furthermore, Ba Ikasod (b
Bandwidth consisting of iBoad) circuit (lsAND=PA8
8>The filter circuit 6o's low and high frequency components are cut, resulting in 5Kf(Z
A filter-passed signal 80F is output.

? A buffer amplifier circuit 6 is provided after the N14 filter circuit 6o.
1 is provided to prevent the bandpass filter frequency characteristics from varying due to the influence of the load connected to the bandpass filter circuit 60. In this case, the voltage amplification degree of the buffer amplifier circuit 61 is sufficient to be 1, and the amplification degree is not set to a large degree. Therefore, the filter passing signal SOF-g (full-wave rectified in FIG. 10 (c
The rectified waveform signal S (, i+) shown in l) is input to the integrating circuit 63 (=J).
Figure 10, in which the OD is smoothed, shows the integral wave 1, which is shown in ).
S.G., 1. N, the frequency component of 51(J(Z) is removed and one pulse 1'1 shown in FIG. 6 is demodulated.
Eff'J 64 K j RI M I OIN (
It) iC As shown, the pulse signal is shaped into a wave J1 and the demodulated pulse I7S signal 5ODJ is applied to the receiver IC65.

Therefore, the receiver IC 65 has a transmission signal phase S shown in the sixth quotient.
A demodulated pulse signal 5()1 voltage similar to O1'W is input. 1 for the receiver (C65 is Tamabishi Electric M50
117X1' (product number) is used, and when the same transmission code is input twice, the reception display signal 5 (OR,
Full output. The reception display elements SU and IR are narrowed to a reception display element 66 consisting of a light emitting diode, and the reception display element 66 generates a display signal such as light. Furthermore, an interrupt signal that changes from logic 0 to logic 1 with a slight delay from the received display signal SGI is sent to the output terminal IN'l' via a pulse 1 width circuit 61 as shown in FIG. 11 (1). Signal 8GI
NT' is output.

While the interrupt signal 8GTNT is logic 1, it is +C and is transmitted from the clock input terminal CL through the pulse amplification circuit 69 as shown in FIG.
When the clock pulse Cl' shown in C) is input, the data signal 1) ATA shown in No. ++1g(d) is outputted to the output terminal SI) via the pulse amplification circuit 68 in synchronization with the sonoclock pulse CP. Ru. This data signal 1)A
i'A is a demodulated pulse signal S O1,)1° that distinguishes between logic O and 1 at pulse intervals, converted into a pulse code that distinguishes between logic O and 1 at normal voltage level. be. FIG. 11 (Data signal 1 in the example shown in (1))A
T, Jj:,1. )oDll)21)8D41)5D6
= + 011001 t).

As described above, the receiver 50 receives the transmission signals 9801 . 'W K Corresponding take command @DA
It is configured to output TA. In addition, the receiver 5
Each of the circuits 51 to 69 of 0 is operated by a +12V constant voltage electric circuit (not shown).

Next, based on the data signal DATA from the reception tA50, the number f! of the transmitted table is determined. : The display device for display will be explained according to FIGS. 12 and 15.

A light emitting element rO consisting of a light emitting diode is connected to the output terminal TN1'VC of the receiver 50, and its light emitting index 1 is connected to the output terminal TN1'VC of the receiver 50.
A light-receiving element 11 is provided opposite to the light-receiving element 11. That is, the light emitting element TO and the light receiving element 11 constitute a photocoupler. Light receiving element r1
One end (emitter) is connected to flu, the other end (collector) (
Mamicroconoputer (S Motoichi: Kizo 71Pl) 8
748 +hereinafter referred to as microcomputer) 73 Noi'FI
J included if complete] NTK I concubine 1tR,;! jl-
, so CD 1ifIJ included terminal IN'l' is connected to the top of the frust m source via a resistor 12. Follow-C1 receiver 50 output terminal J N'J'color; flJ input signal I
5OTNT force output;! n, Ruto, luminescent youngest child 70
is emitted, and the light receives >+6 elements 11 ka ON
Sah,,,Qj41 Q NopilJ included IJ No. 5 ()
rNl'i=ma(IJ' to interrupt terminal TNT of controller 13)
! : To be done. In this way, the interrupt signal 8 ('J I',
NT is configured to be transferred via the light emitting element 1o and the light receiving element γ1, and the interrupt signal 1j 5OINT
This is to remove noise components.

Similarly, the output terminal 81) of the received t$50 is connected to the light emitting element 7.
4. Light receiving element 15. It is connected to the test terminal TO of the microcomputer 13 via a resistor 76 to transfer the data signal υA'J'A. Also, the terminal D1 of the microcomputer 73
The pulse amplification circuit 171 and the light emitting element 78 . Light receiving element γ9
．． It is connected to the clock input terminal CI of the receiver 50 via a pulse amplification circuit 80 so that a clock pulse CI' can be transferred.

The microcomputer T3 sends a θ'' transmission signal 5 (3) to the interrupt terminal INi'.
When TNT is manually applied, data terminal 1)? Output a clock pulse CP from 1. 1) AT from the receiver 50 to the test terminal 1"0 of the microcomputer 13.
A is attacked by someone.

The data terminal J)2 of the microcomputer 73 is connected to the pulse amplification circuit 8.
11 light emitting element 82. Light receiving element 83. Pulse amplification circuit 84
It is connected to the notification sound generation circuit 85 via. The familiar sound generation circuit 85-1 is built in a commercially available Meloty ICf, and as described above, when the take signal 1)Ai'A is input to the test terminal 1゛0, the take terminal 1〕2
The notification sound generation signal 5 (3VC+) is outputted, the notification sound generation circuit 85 is activated, and the acoustic element 86 generates a notification sound that makes a melody.

Output ports of the microcomputer 13 - I-P10 to 1'17 and ]'
21 to 1 and 26 are connected to a display section 109.

The output '1Mo-l-]'14 to P17 of the microcomputer 73 is 441I! A take of i'1.4 is transferred to the input terminals of Tecotor drivers 87 to 90 of No. 11 [IJ1
7) Tekota driver 8 of t et al.
For 7-90, the 4-hino I- take is replaced with a 7-hino footer, and the i-reli is displayed on the four number display sections 91-94, respectively. Note that the output ports ]' 10 to ]' 13 are connected to the Tekota drivers 87 to 90, respectively, and latch signals are output from the output ports 1' 10 to 1' 13 to the output capo-1. Then, the 41)th take manually applied to each Tekota 1 to Live 81 to 90 will be 1% memorized. In addition, each of the Tekota drivers 87 to 90 is a commercially available
C1 can form a snout.

Each number display part 91 = 94 is six 7-segment members! The number display elements 95 (LED liquid crystal, etc.) are arranged in sets of two in 12 windows 96 to 107, as shown in FIG.

The 17 ports P21 to P26 of the microcomputer 73 are connected to the power supply terminals of the six number display elements 95 in each number display section 91 to 94 via the driver 10B.
The four signals from the recording ports P14 to I' 17, the latch signals from the output ports 10 to 13, and the output signals from the output ports I' 21 to J' 26 are input into the microcomputer 13. A desired number display element 95 can display a desired number by a so-called dynamic dry method in which control is performed at a direct speed using a solo drum.

When the power is turned on, the initial setting circuit 110 is set to 1 to
When the Lancisor 111 is turned on, the initial setting signal that becomes logic 0 for a predetermined time (approximately 0.4 sec) from the output terminal Q of the monostable multi-biflake (hereinafter referred to as mono-multi) and hT l f 12 is sent to the initial setting circuit of the microcomputer 73. Old ES
The microcomputer 13 is thereby initialized.

:F, T, IB force terminal Q of mono multi 112 is M at a specified time.
If the logic is 1, that signal is No IL IJ path 1.
13 to each of the Tecota drivers 87 to 90, all of the numeric display elements 95 are erased. In addition, the output port 27 of the microcomputer 73 is lm1T.
Q N01'L Circuit 113 input terminal Kl'im:n, its input terminal is connected to the power supply flush terminal via resistor fJ'G114k, and capo 1.21 is connected to #ii+1. 11j I When the number display element 95
Nosu・\te will be deleted. Also, the output of output port 21 and mono multi 112! '1-7f f-(J and IJJj are both logical IJJj At 90, the number display element 95 can display numbers.

The take terminal IJO of the microcomputer 73 is connected to the positive vehicle source terminal VC via the resistor 116 in the abnormal signal detection circuit 115, and its theta 1) () is when the microcomputer 13 is in normal operation. Logic 0's ``Tunenobuyumi, when there is an abnormality, there is no logic.''
L'l! L's Tsunenobukan Tatsumi is a monomulti 111 human power f'
i! I will visit A113. The monomulti 117 outputs a signal from the output terminal Q for a predetermined period of time (approximately 5, 2
Ins(!(outputs a signal that becomes four wheel logic 1. Its output terminal Qld is connected to the test terminal T1 of the microcomputer T3 and the input terminal of the NO circuit 118, and its NOR,
The output terminal of the circuit 118 is grounded through a series circuit of a resistor 119 and a capacitor 120. A series circuit of a low resistance 121 and a diode 122 is connected in parallel to the high resistance 119, and the potential across the capacitor 120 is applied to the initial setting circuit via the pulse amplification 1n approximately 123 and the inverter 124. The input terminal BVC of the monomulti 112 in 110 is checked. In addition, the output terminals Qid, tJiJki No I+ of the monomulti 112
, are connected to the input terminals of circuit 118.

Now, when the output terminal Q of the monomulti 11γ becomes the logic β441, the 7J3 force of the N(,) I, L appositive 11B becomes the logic J
The stored charge stored in the capacitor 120 is immediately discharged through the quartz 120 and the low resistance 121, and the voltage at both ends of the content 120 becomes OV (logic 0). . Part 1: The output of the pulse amplification circuit 123 is changed from logic 1 to logic 0, the output J of the inverter 124 is changed from logic 0 to logic tll +, and the input terminal H of the monomulti 112 is Approximately 0.1 from the mono multi 112 output terminal (Ma,
sC! The initial setting signal (which makes the logic 0 between e and
3 is initialized. In this case, the output W'M element Q of the monomulti 112 becomes one logic l, and the lid r of the number display element 95 is erased as described above. In addition, since the operation time of the L Norch 112 between H:7 (approximately f) and +S+・(・) is longer than the operation time of the monomulti 11γ (approximately 6.2m5pe), the NOR circuit 118 is
It outputs a belief with eyebrows i and 0 for a period of 1:j (approximately [1,1S+゛+: ). Output 17 of the monomulti 117] When the output terminal Q changes from logic 1 to logic 0, there is noise at the output terminal of the NOIt circuit 118, but the high resistance 119
, l]/den'lJ-120 eliminates the noise.

Mono multi 112 output terminal (J is logic 0. Output terminal (
This changes to logic 1 - then, N011. The output of the l four-way 118 becomes logic 1, and the content 120 becomes high resistance 1.
19, the output of the pulse amplification circuit 12-3] J is logic 1, and the output of the bake 124 is logic 0.
becomes.

As described above, the abnormal signal detection circuit 115 cooperates with the period setting circuit 110 to set the microcomputer 13 to the initial setting state based on the abnormal signal from the data terminal 1)0 of the microcomputer 13. In addition, the output terminal of the mono multi 117 (from J to the terminal '1'1 of the microcomputer 13!! l! I
When the signal is turned on, the microcomputer 73 turns on its own input 7]
All conditions are checked.

Now, the microcomputer 73 outputs the pano-J take signal 1) A.
'l' Take signal number 1) A based on A
i' Input A according to the 1st sequence - crm window 96, 97
．． . . . , 101 are programmed to be displayed in this order. :]:T-tete signal JJ, Ai
After a predetermined period of time has elapsed since 'A' was input, the display in the window 96 corresponding to the data signal IJAi'A is erased, and the window 96 is cleared.
7 on window 96, window 98 on window 91, etc.
....

Display f! on window 107! : Shift to the window 106 respectively.

Then, in the window 101, the undisplayed full number and month will be displayed in accordance with the input order of the take signal DAi'A. In addition, depending on the block number J, please write the remaining chief numbers in window 101 in order.
■You can also display it in reverse.

Mykonoa 3 has a central processing unit (CP[,l), a dedicated storage device (ROM), and a random access memory (AA1), all of which are built-in, for example, as shown in the 14th article, J : ') K IL0114 K 'Ae,
'eJ 'l! ;I'1. jc fl (+J l
1llll −j'D')'7'' ICU(=
Two C works.

Brokram started off with the first 1111 setting. Interrupt message from receiver 50! ″) +) + i r When the NT is input manually, the ITU states that the take signal l) A'l'A is input, and the notification sound is generated.
When the iVD is output, a t%-C melody sound is generated. 1
(・AM's back address is flanked (1='f・A(
＋ ] is a semetsusaha, it is not fl-ha, sono rtAA
4 K id Take command Q') A11A power storage 'X
” indicates that FL is not set to the specified address of ILAM.
When AI is set, the address is changed and FLA (,) is not set. Its address/data signal 1) Ai'A i
Transfer and send FLAQ f: September to the corresponding address. It also starts a timer operation corresponding to the address. Next, drive the display unit 109 to display the take signal 1) Ai'A or the stored TLI-M.
According to the address of -C1 window 9 (i, 97."...-, the table number is displayed at 11100.

Next, if the timer operation corresponding to the specified address has not finished, the timer f is clocked and the timer screen is set to 1.
′[; Finds the timer that has finished. Then, clear the address (A address) (Tate (No. 9 1) no TΔ corresponding to that timer, and (A + No. 11 Jya's Day 9)
Ai'A is sent to address A. Then, by changing the address from 1 to 1, the take signal H=51
) ATA is transferred 7, and the take signal IJ/\' of the final address is transferred.
When 1'l\ is transferred, start the timer again and search for the timer whose timer operation has ended. 'do. Note that the number of addresses in which the data signals 1 inch IJ and A'l'A are stored is greater than the number of windows 96-107. When the operation of the final timer is completed, the program returns to the program which determines whether or not the interrupt signal IN80 has been received.

2111 included signal 8INT is input! 1 must be done, h
, transitions to the program l, which displays the display r5+<109 in a short time.

This - program speed + d is controlled at high speed by the microcomputer 13 ((externally connected crystal, not shown!
Character display element 95&i Afterimage phenomenon V is always displayed -C
It looks like there is.

In addition, as shown in FIG. 12, the row circuits of the display device except the receiver 50 are operated by a constant voltage circuit of +5.

As mentioned above, in this example, when the display switch 16 of the transmitter 1 is activated, the transmitter device 1 is activated. It is possible to display the number of the finished chiffle for a predetermined period of time, which is convenient for both customers and the store.

Effects 1-Details I-As described above, the present invention provides the display switch 16.
The operating time of the display switch 16 based on the switch signal 5 (isW) generated when the switch 1' is activated is 8 W.
Trust the first timer for a sufficiently longer period of time 5GTF
The first timer circuit 18 outputs the signal p, i based on the timer signal 5OTI', and the transmission activation signal S(,3
The second timer circuit 26 which outputs 1'l(7J) and the time period during which the transmission activation signal sGi'E3- is applied
Since the antenna 46 is configured with a transmission wave emitting circuit which emits all transmission waves from the antenna 46, transmission is performed only for a predetermined period of time, regardless of the time when the display switch of the transmitter is activated. In this way, it is possible to eliminate the influence of the display switch switch, thereby ensuring reliable transmission and reducing power consumption◇

[Brief explanation of the drawing]

Figure 1 shows an embodiment of this invention in a sign display device. Figure 1 is a cross-sectional view of a transmitter, Figure 2 is a perspective view of a transmitter, and Figure 5 is a stop plate on the transmitter. Figure 4 is a partial cross-sectional view of the state in which the transmitter is turned on and off.
Figure CF! 1 to ((1) and Figures 6 to 8 are waveform diagrams of each part of the transmitter circuit, Figure 9 is a circuit diagram of the receiver, and Figure 10 (+
1) to (11) and FIGS. 11(r) to (d) are waveforms of each part of the receiving circuit, and FIG. 12 is a circuit diagram of the display device.
FIG. 3 is a perspective view showing the numeric display section, and FIG. 14 is a flowchart showing the control program of the microcomputer. Transmitter 1, transmission circuit 3, Oze circuit 13, dry battery 14, display switch 16, first timer circuit 18, second timer circuit 26, operation (auxiliary display circuit 27, transmission display element 31, transmission I
Step I (-: 3 B, frequency setting (circuit 39, modulation amount 1 heat 40, antenna 46° special, ii: f l i
trj + person stock 'A fl: "A" =
-Representative Patent Attorney Haru 1) Dr. Yoshi 1st
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Claims (1)

[Claims] 1. In a transmitter that transmits when the display switch (16) is activated, the transmitter transmits a signal based on the switch signal (8 (J8W)) generated when the display switch (16) is activated. Display switch (
16) The time (TOW) is sufficiently longer than the operating time (TOW).
The first timer circuit (1B) outputs the first timer signal (5t'ti'J-) by TF), and the first timer circuit (1B) outputs the first timer signal (801'F), which is necessary and sufficient for transmission. minimum time (1'TL)
A second timer circuit (26) outputs a transmission activation signal (sa'ra) only in the heat, and a second timer circuit (26) outputs a transmission activation signal (sa'ra) only during the time when the transmission activation signal (SGTIl) is applied ('1''1'P, , ). ) transmitting radio wave emitting circuit (38
Transmission 4-1# consisting of ゜39.40 zero). 2 an operation display circuit (21) that outputs an operation display signal (8GINDl) for the necessary sufficient and minimum time (T'1NI) based on the transmission operation signal (SGTR heat); 2. Transmitter according to claim 1, further comprising: a display element (31) for generating a display signal based on the transmitter.