JPS59124769A - Semicondutor device - Google Patents

Semicondutor device

Info

Publication number
JPS59124769A
JPS59124769A JP23375682A JP23375682A JPS59124769A JP S59124769 A JPS59124769 A JP S59124769A JP 23375682 A JP23375682 A JP 23375682A JP 23375682 A JP23375682 A JP 23375682A JP S59124769 A JPS59124769 A JP S59124769A
Authority
JP
Japan
Prior art keywords
layer
gate
electron
gallium arsenide
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23375682A
Other languages
Japanese (ja)
Inventor
Kazukiyo Tsunenobu
和清 常信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23375682A priority Critical patent/JPS59124769A/en
Publication of JPS59124769A publication Critical patent/JPS59124769A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

PURPOSE:To obtain a high electron mobility transistor with a Schottky electrode, electrostatic capacitance between gate-sources thereof is small, cut-off frequency thereof is high, high-frequency characteristics thereof are excellent and gate dielectric strength thereof is large. CONSTITUTION:An un-doped layer 31 in three layers constituting an electron supply layer 3 has a function preventing ionic scattering. A high-concentration N type layer 32 satisfies conditions in which a two-dimensional electronic gas having surface concentration of approximately 10<11>/cm<2> or more necessary and sufficent as a conductive medium of the semiconductor device is generated, but its thickness is very thin. The third, an n type layer 33 as an uppermost layer satisfies conditions necessary and sufficient for allowing the formation of a depletion layer to the lower section of a gate electrode, and has not thickness more than required. Consequently, the thickness of the electron supply layer 3 is sufficiently thin and electrostatic capacitance between the gate-source is reduced sufficiently, cut-off frequency is improved, and high-frequency characteristics are enhanced. Dielectric strength between the gate-sources is also improved because impurity concentration in the N type layer 33 has been reduced properly.

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明は半導体装置に関する○特に、ショットキ電極を
有する高電子移動度トランジスタに関する。俳に詳しく
は、かかる高電子移動度トランジスタにおいて、高周波
特性の指標の一つである遮断周波数を向上し、更に、ゲ
ート絶縁耐力を向上する改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a high electron mobility transistor having a Schottky electrode. More specifically, the present invention relates to improvements in such high electron mobility transistors that improve the cutoff frequency, which is one of the indicators of high frequency characteristics, and further improve the gate dielectric strength.

(2)#術の背景と従来技術の問題点 高電子移動度トランジスタとは電子親和力の相異なる2
種の半導体を接合することによI)形成される一つのへ
テロ接合面の近傍に滞留する電子群(二次元電子ガス)
の電子面濃度を制御電極によって制御して、この制御電
極を挾んで設けろわだ一対の入・出力電極間に上記の滞
留電子群(二次元電子ガス)をもって形成される導′市
路のインぎ−ダンスを制御する能動的半導体装置をいう
(2) Background of #technology and problems with conventional technology High electron mobility transistors have different electron affinities 2
A group of electrons (two-dimensional electron gas) that stays near one heterojunction surface formed by joining two types of semiconductors.
A control electrode is used to control the electron surface concentration of An active semiconductor device that controls energy dance.

高電子#動量トランジスタを構成しつる半導体の祁み合
わせとt「0うる半導体の柔性は、(イ)互に格子定数
が同一マあるか近似していること、c口)電子親和力の
苦が大きいこと、θうノぐンドギャップの差が犬ぎいこ
とであるから、多数存在[2、その絹み合わせの・1層
表的な数例は本特許出願の出願人の’jr L、た先の
特許出涼自(#朝明第55−82035号)等に列記し
である。
The combination of the stranded semiconductors that make up the high-electron-momentum transistor and the flexibility of the 0-value semiconductors are: (a) their lattice constants are the same or close to each other; Because of the large size and the large difference in the θ gundo gap, there are many examples [2. These are listed in the previous patent issued by Ryoji Izuru (#Chomei No. 55-82035).

又、電子親和力の太きt「半導体よ1)t「るJ−を上
層にしても下層にしても、それぞれ、特有の冬作を介、
足するかぎI]高小:子移動度トランジスタの製造は可
能である。
In addition, whether J- with a thick electron affinity is placed in the upper layer or the lower layer, through a unique winter crop,
Addition key I] High and low: It is possible to manufacture child mobility transistors.

Wlに、ノーマリオン型も、ノーマリオフ型も、それぞ
わ、特有の要件をf足すれば、剰造可蛯である。但し、
本発明は、ノーマリオン型の改良である。
Both the normally-on type and the normally-off type can be constructed by adding f to Wl with their own specific requirements. however,
The present invention is an improvement on the normally-on type.

高電子移動度トランジスタにおいては、上記の滞留電子
群(二次元電子ガス)の電子層@T#1が特に低椙にお
いて非常に大きくなることが特徴である0 高電子移動度トランジスタは、上h14のとお蔭)、高
い動作速°度が特徴であるから高周波用に適する。
A high electron mobility transistor is characterized in that the electron layer @T#1 of the above-mentioned retained electron group (two-dimensional electron gas) becomes extremely large, especially at a low temperature. (Thanks to Noto), it is characterized by high operating speed, making it suitable for high frequency applications.

2π C()S イ日 ■7、 frは遮断周波数であI)、 Gm は伝達コンダクタンスでア)1゜Oos 11 
’l−ト・ソース間等電容量である。
2π C()S iday ■7, fr is the cutoff frequency I), Gm is the transfer conductance a) 1゜Oos 11
is the isocapacitance between source and source.

をもって表」される遮断周波数の向上が望ましく、その
ためには伝達コンダクタンス〇mを大キくシ、ゲート・
ソース間静電容量を減少することが望ましい。一方、シ
ョットキゲートの絶縁耐力は必ずしも高くないので、こ
の向上も望ましい。
It is desirable to improve the cut-off frequency, which is expressed by
It is desirable to reduce source-to-source capacitance. On the other hand, since the dielectric strength of Schottky gates is not necessarily high, it is also desirable to improve this.

(3)  発明の目的 本発明の目的は、ゲート・ソース間静′釈容量が小さく
遮断周波数が高く筒周波特性がすぐれており、荀1にゲ
ート給源耐力の大きt「ショットキ′市極を有する高電
子$al’f )ランラスタを提供することにある。
(3) Object of the Invention The object of the present invention is to provide a structure having a low static capacitance between the gate and the source, a high cut-off frequency, excellent cylindrical frequency characteristics, and a Schottky electrode with a large gate source breakdown strength. The objective is to provide a high electron $al'f) run raster.

(4)  発明の構成 上記の目的は、半絶縁性の半導体基板上に形成さねた電
子親和力の相異なる2種の半導体よI)なる二重層の界
面近傍に滞留する電子群(二次元電子ガス)を導電媒体
とし、該導電媒体をもって構成される導電路のインピー
ダンスを、前記半導体二重層のいずれかの上に設けろわ
た制御電極をもって制御し2、前記導電路は前記制御電
極を挾んで設けらノまた一対の入・出力電極と接続され
てなる半導体装置において、前記半導体二重層を構成す
る#導体層のうち電子や和書の小さい層は更に2層に分
割されてお1)、電子親和力の大きい層に接している層
は高濃度にn型不紳物を含有する薄層であI)、電子親
和力の大きい層に接していない層は前記薄層よl)低濃
変のn型であI)、式イロ し 、 φは前記電子顆、和書の小さな層の表面ポテンシャル〒
あl)、 qは電子電荷であ1)、 εは前配電子麹和書の大きい層の誘電率〒あl)、 Nは前記電子親和力の大永い層のn型不純物濃度フあ番
)、 dけ前記電子親和力の犬永い層の厚さである。
(4) Structure of the Invention The above object is to eliminate a group of electrons (two-dimensional electron gas) as a conductive medium, and the impedance of a conductive path constituted by the conductive medium is controlled by a control electrode provided on either of the semiconductor double layers, and the conductive path is provided with the control electrode sandwiched therebetween. In a semiconductor device connected to a pair of input/output electrodes, the small layer of electrons and Japanese book among the # conductor layers constituting the semiconductor double layer is further divided into two layers. The layer that is in contact with the layer with high electron affinity is a thin layer containing a high concentration of n-type undesirable substances (1), and the layer that is not in contact with the layer with high electron affinity is the thin layer (1) with n-type with low concentration change. I), where φ is the surface potential of the small layer of the electronic condyle,
(al), q is the electron charge (1), ε is the dielectric constant of the layer with a large electron affinity (al), N is the n-type impurity concentration number of the layer with a long electron affinity), d is the thickness of the layer with the above electron affinity.

を満足することによI)達成される。特に、基板と電子
′?U和力和書きい層はガリウムヒ素(GaAs)−r
あI)、電子親和力の小さい層はアルミニウムガリウム
ヒ素(A/GaAs)である場合、特にすぐれた特性を
有する。滞留電子群(二次元電子ガス)が発生するため
には、上記の一つのへテロ接合面を構成する2種の半導
体のうち電子層和書の小さい半導体よI)なる層(電子
供給層)中に、上記の界面に供給される電子源の存在す
ることが必須である。
I) is achieved by satisfying the following. In particular, the substrate and electrons? The layer is gallium arsenide (GaAs)-r
(I) When the layer with low electron affinity is aluminum gallium arsenide (A/GaAs), it has particularly excellent properties. In order to generate a group of retained electrons (two-dimensional electron gas), one of the two types of semiconductors constituting one of the above-mentioned heterojunction surfaces is the smaller semiconductor layer (electron supply layer) in the electronic layer Japanese book. In addition, the presence of an electron source that is supplied to the interface is essential.

しかし、滞留電子群(二次元電子ガス)の面#変n8は
上記の電子親和力の小さな層(電子供給#)のn ff
Jj不紳物濃KNDの平方根に比例し、ns=に一β乙
の関係を満足するから、IQ”/cm2程度の二次元電
子ガス面濃度を得るためには1018/σ3程度のn型
不純物濃度を有する半導体層の厚さは6(1(X:l稈
変で十分である。
However, the surface # change n8 of the retained electron group (two-dimensional electron gas) is n ff of the above-mentioned layer with small electron affinity (electron supply #)
Jj is proportional to the square root of KND, and satisfies the relationship of 1β to ns, so in order to obtain a two-dimensional electron gas surface concentration of about IQ”/cm2, an n-type impurity of about 1018/σ3 is required. The thickness of the semiconductor layer with a concentration of 6 (1 (X:l) is sufficient.

ただ、ショットキ小:極と半導体との間には、式φは表
面ポテンシャルテアI)、 qは電子電荷であ番)、 eは半導体の誘電率であ0、 Nは半導体のn型不純物濃度であl)、dけ半導体の層
厚である。
However, Schottky small: Between the pole and the semiconductor, the formula φ is the surface potential tear I), q is the electronic charge (number), e is the dielectric constant of the semiconductor 0, and N is the n-type impurity concentration of the semiconductor. d is the layer thickness of the semiconductor.

で表視される表面ポテンシャルが誹〕)、この胤すの領
切が空乏化される。
), the territory of this seed is depleted.

したがって、電子■和書の小さい層(電子供給層)の必
要にして十分な理さは、上記の電子源としての厚さと空
乏層の厚さとの和である。
Therefore, the necessary and sufficient reason for the small layer (electron supply layer) in the electronic Japanese book is the sum of the thickness as the electron source and the thickness of the depletion layer.

ケート・ソース間静電容量008は ε ・ 5 00B  : 但し、 Cは半導体の誘電率であ番)、 Sはゲートの面積であを)、 dは半導体の/lである。The gate-source capacitance 008 is ε ・ 5 00B: however, C is the dielectric constant of the semiconductor), S is the area of the gate), d is /l of semiconductor.

をもって表現されるから、ソース・ゲート間静電答量を
減少するには電子供給層の層厚を増大すればよい。その
ためには、n型不純物濃度を減少することが有効である
が、これは伝達コンダクタンスを低下するので、本発明
にあっては、電子供給層を二分割し、電子親和力の大永
い層と接する層の不純物濃度は1018/cm3または
それ以上と高くし、かつ、その理さを60(X)または
それ以下と薄くし、一方、空乏化する領塘においては不
純物6度を10 ” /α3またはそれ以下と低くして
ゲート絶縁耐力を向上させ、あわせて、高い導電性を維
持しがつ、ゲート・ソース間静電容量aaBを小さくし
て遮断周波数を向上し、結果的に、すぐれた高周波特性
を実覗したものである。
Therefore, in order to reduce the source-gate electrostatic response, it is sufficient to increase the thickness of the electron supply layer. For this purpose, it is effective to reduce the n-type impurity concentration, but since this lowers the transfer conductance, in the present invention, the electron supply layer is divided into two parts, and the electron supply layer is divided into two parts, and the electron supply layer is divided into two parts. The impurity concentration of the layer is made as high as 1018/cm3 or more, and the density is made as thin as 60(X) or less, while in the depleted region, the impurity concentration of 6 degrees is reduced to 10''/α3 or The gate dielectric strength is improved by reducing the gate dielectric strength to less than that, and at the same time, the cutoff frequency is improved by reducing the gate-source capacitance aaB while maintaining high conductivity, resulting in an excellent high frequency. This is an actual look at its characteristics.

(5)発明の実施例 以下、図面を参照しつつ、本発明の一実施例に係る半導
体装置について、更に説明する。
(5) Embodiment of the Invention A semiconductor device according to an embodiment of the invention will be further described below with reference to the drawings.

第1図匈照 一例として、半絶縁性ガリウムヒ素(Ge、As)基板
l上ニ10147r+n3以下にn型の不純物を含み:
(、OQQ〜4.ooo(X)の厚さを有するガリウム
ヒ素(nGaAs)層2が形成されており、その上にn
型のアルミニウムガリウムヒ素(nA/GaAs)層よ
I)なる電子供給層3が形成されておl)、この電子供
給層3が3層に分割されており、最下層がアンP−プで
1o14/儂3以下にn型の不純物を含み厚さが20〜
6oCcA〕程度であるアルミニウムガリウムヒ9 (
n−A/GaAs)層31〒あI)、中間層が高濃度に
1.0187(M、3またはそれ以上にn型の不純物を
含み片さがho(X)以下であるアルミニウムガリウム
ヒ’J (n”A/GaAs) N32〒あI)、最上
層がn型の不純物を1017/σ3程度に含みIすさが
500−700 (X)であるアルミニウムガリウムヒ
素(nA/GaA日)層33フあり、その上にショット
キケート電極4と高濃度n型のガリウムヒ素(nGaA
e)層5よりなる電極コンタクト層が形成されておl)
、この電極コンタクト層5の上にンース′電極6とドレ
イン電極7とが形成さねている半導体装置について述べ
る。
As an example in Figure 1, a semi-insulating gallium arsenide (Ge, As) substrate l contains n-type impurities below 10147r+n3:
A gallium arsenide (nGaAs) layer 2 having a thickness of (, OQQ~4.ooo(X) is formed, and n
An electron supply layer 3 is formed of a type aluminum gallium arsenide (nA/GaAs) layer I), and this electron supply layer 3 is divided into three layers, and the bottom layer is an amplifier with a 1o14 /I Contains n-type impurities below 3 and has a thickness of 20~
Aluminum gallium 9 (
n-A/GaAs) layer 31〒AI), the intermediate layer is made of aluminum gallium hyaluronan with a high concentration of 1.0187 (M, 3 or more) containing n-type impurities and a fraction of ho(X) or less. J (n”A/GaAs) N32〒AI), the top layer is an aluminum gallium arsenide (nA/GaAs) layer 33 whose top layer contains n-type impurities at a ratio of about 1017/σ3 and has an I height of 500-700 (X) On top of that is a Schottkycate electrode 4 and a highly concentrated n-type gallium arsenide (nGaA).
e) an electrode contact layer consisting of layer 5 is formed;
, a semiconductor device in which a drain electrode 6 and a drain electrode 7 are formed on the electrode contact layer 5 will be described.

電子供給層3を構成する3層のうち、アンドープの層3
1はイオン散乱を防ぐ機能を有し、本発明の要旨ではな
い。ただ、隣接層から拡散するn型不純物のため、n−
型となっている。次に、高濃度n型層32が本発明の要
旨に係り、半導体装置の導電媒体として必要にして十分
な1g+1/cm2程度以上の面@度を有する二次元電
子ガスを発生する要件を満すが、その厚さは極ぬて薄い
。第三に、最上層のn型rf433はゲート電極下部に
空乏層の形成を許すに必要に十分な要件を満し、しかも
、必要以上の埋さを有しない。
Among the three layers constituting the electron supply layer 3, the undoped layer 3
1 has a function of preventing ion scattering and is not the gist of the present invention. However, due to n-type impurities diffusing from the adjacent layer, n-
It has become a type. Next, the high concentration n-type layer 32 is related to the gist of the present invention and satisfies the requirements for generating a two-dimensional electron gas having a surface density of about 1 g+1/cm2 or more, which is necessary and sufficient as a conductive medium of a semiconductor device. However, its thickness is extremely thin. Thirdly, the n-type RF433 in the uppermost layer satisfies the necessary and sufficient requirements to allow the formation of a depletion layer under the gate electrode, and is not buried more than necessary.

そのため、電子供給層3の厚さは十分薄くゲート・ソー
ス間静電容量は十分低くされ、遮断周波数は向上し、高
周波特性が改善されている。
Therefore, the thickness of the electron supply layer 3 is sufficiently thin, the gate-source capacitance is sufficiently low, the cut-off frequency is increased, and the high frequency characteristics are improved.

更に、このn型層33の不純物濃度は適度に低くしであ
るので、ゲート・ソース間絶縁耐力も向上している。
Furthermore, since the impurity concentration of this n-type layer 33 is moderately low, the gate-source dielectric strength is also improved.

第2図参照 以下、第1図に示す半導体装置を製造する工程について
神明する。
Referring to FIG. 2, the steps for manufacturing the semiconductor device shown in FIG. 1 will be explained below.

半絶縁性ガリウムヒ素(GaAs)基板1上に、101
47cm’以下にn型の不純物を含み3.000−4.
00(l Cス〕の厚さを有するガリウムヒ素(nGs
 Aθ)層2(!l−、アンP−プで〃さが20〜60
〔ス〕程度であるアルミニウムガリウムヒ素(nA/G
a、As )層31と、It)” /lv3またはそれ
D上のに?IA eにn型の不純物を含み厚さが6n〔
X)以下であるアルミニウムガリウムヒ素(n+A/G
aAR)層32と、n型不純物ヲ1010177t程9
に含み〜さが5nn −7on (X)であるアルミニ
ウムガリウムヒ素(nA/GaAs ) $ 33と2
×1018/cm3程変の高n度にn型の不純物を含み
腫さが500〜1.000[ス]稈度のガリウムヒ素(
nGaAs) $ 5を、つづけて形成する。この工程
は分子線成長法をもって形成すると便利である。上記せ
るとおl)、隣接局からの拡散のため、1ω31はn−
型となっている。
101 on a semi-insulating gallium arsenide (GaAs) substrate 1
Contains n-type impurities below 47cm' 3.000-4.
Gallium arsenide (nGs) with a thickness of
Aθ) layer 2 (!l-, amplifier with a value of 20 to 60
Aluminum gallium arsenide (nA/G
a, As ) layer 31 and It)"/lv3 or on it D?IA e contains n-type impurities and has a thickness of 6n [
Aluminum gallium arsenide (n+A/G
aAR) layer 32 and n-type impurity layer 9
Aluminum gallium arsenide (nA/GaAs) with ~5nn-7on (X) $33 and 2
Gallium arsenide (contains n-type impurities with a high degree of n of about ×1018/cm3) and has a mass of 500 to 1.000[s].
nGaAs) $5 is subsequently formed. This step is conveniently performed using molecular beam growth. As stated above, 1ω31 is n- due to the spread from neighboring stations.
It has become a type.

そして、層5はソース電極及びドレイン電極のコンタク
ト抵抗を下げるための層であり本発明の要旨受けない。
The layer 5 is a layer for lowering the contact resistance of the source electrode and the drain electrode, and is not the gist of the present invention.

第3図参照 ガリウムヒ素(nGaAB) F 5の一部領域を選択
的にエツチング除去してゲート形成領域41を形成する
。この工程はフォトリソグラフィー法とHF : F!
20□” 20= 2 : 16 : 500をエッチ
ャントとしてt「すウェットエツチング法をもってなす
ことができる。
Referring to FIG. 3, a part of the gallium arsenide (nGaAB) F 5 is selectively etched away to form a gate forming region 41 . This process uses photolithography method and HF:F!
This can be done by a wet etching method using 20□''20=2:16:500 as an etchant.

第4図参照 アルミニウム(At)膜を形成した後、ゲート上以外の
領域な茨釈的に除去してゲート4を形成する。この工程
はスパッタリング法とフォトリソグラフィー法とウェッ
トエツチング法とを用いてなすことが〒きる。
Referring to FIG. 4, after forming an aluminum (At) film, the gate 4 is formed by removing the aluminum (At) film in areas other than the gate. This step can be performed using a sputtering method, a photolithography method, and a wet etching method.

第1図参照(再参照) ソース・ドレイン領域以外なし・シスト膜(図示せず。See Figure 1 (re-reference) Nothing other than the source/drain region/Cyst film (not shown).

)をもっておおい、AuGe/Au膜を形成した後、レ
ジスト膜を除去して、ソース電極6、ドレイン電極7を
形成する。その後、450(’O〕PI4度〒熱処理を
実行してソース電極6、ドレイン電極7の下部領域の合
金化を実行して、半導体装置を完成する。
) to form an AuGe/Au film, and then remove the resist film to form a source electrode 6 and a drain electrode 7. Thereafter, heat treatment is performed at 450 ('O) PI 4 degrees to alloy the lower regions of the source electrode 6 and drain electrode 7, thereby completing the semiconductor device.

ソース電極及びドレイン電極のコンタクト抵抗を互いに
低下するために慴33のアルミニウム混晶比を次第に低
下させ、p上部においてガリウムヒ素(Ga、As)と
t「るようにしておくことは朴めで有効である。
In order to reduce the contact resistance of the source electrode and the drain electrode, it is simple and effective to gradually lower the aluminum mixed crystal ratio of the layer 33 and keep it in contact with gallium arsenide (Ga, As) in the upper part of the layer. be.

上記の実施例にあっては、ガリウムヒ素(GaAs)と
アルミニウムガリウムヒi((AZGaA8)の組み合
わせよりなる高電子移動度トランジスタについて述べで
あるが、これは−例であ)1、本発明を限定するもので
はない。また、上記の実施例にあってはゲート電極が電
子供給層上に設けられているが、これも−例〒あり、そ
の逆の層構造〒もさしつかえない。更にゲート電極はシ
ョットキに限らず、MiS型でも接合型↑も、制御′N
vN下極下較的細濃度層を空乏化できる噸構成すればよ
い。
In the above embodiment, a high electron mobility transistor made of a combination of gallium arsenide (GaAs) and aluminum gallium arsenide ((AZGaA8) is described, but this is just an example). It is not limited. Further, in the above embodiments, the gate electrode is provided on the electron supply layer, but there are other examples, and the opposite layer structure may also be used. Furthermore, the gate electrode is not limited to the Schottky type, but also the MiS type and the junction type↑.
It suffices if the structure is such that a relatively fine concentration layer at the lower end of vN can be depleted.

(6)発明の効果 以上霞明せるとお1)、本発明によれば、ゲートソース
間静電容量が小さく遮断量波数が高く高周波特性がすぐ
れてお番)、史にゲート絶縁耐力の大きな、ショットキ
電極を有する高電子移動度トランジスタを堤供すること
ができる。
(6) More than the effects of the invention 1) According to the present invention, the gate-source capacitance is small, the cut-off wave number is high, the high-frequency characteristics are excellent), and the gate dielectric strength is historically large. High electron mobility transistors with Schottky electrodes can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に伴る半導体装置(高電子移
動度トランジスタ)の断面図であり、第2乃至第4図は
その製造工程を示す断面図1ある。 1・・・基板(GaAs)、2−n−型ガリウムヒ素(
n″GaAs)層、3・・・電子供給層、31・・・ア
ンドープのアルミニウムガリウムヒ素(n−A/GaA
s) Ffjj% 32−n”アルミニウムガリウムヒ
素(n+A/GaAs)層、33・・・nアルミニウム
ガリウムヒ素(nA/GaAs)層、4・・・シロット
キゲート電極、41・・・ゲート形成領域、5、・・n
ガリウムヒ素(nGaAs)層、6・・・ソース電極、
7・・・Pレイン電杼。 符開日U39−124769  (5)第4図
FIG. 1 is a sectional view of a semiconductor device (high electron mobility transistor) according to an embodiment of the present invention, and FIGS. 2 to 4 are sectional views 1 showing the manufacturing process thereof. 1...Substrate (GaAs), 2-n-type gallium arsenide (
3... electron supply layer, 31... undoped aluminum gallium arsenide (n-A/GaAs) layer, 3... electron supply layer, 31... undoped aluminum gallium arsenide (n-A/GaAs
s) Ffjj% 32-n'' aluminum gallium arsenide (n+A/GaAs) layer, 33...n aluminum gallium arsenide (nA/GaAs) layer, 4...Shirotki gate electrode, 41...gate formation region, 5,...n
gallium arsenide (nGaAs) layer, 6... source electrode,
7...P rain electric shuttle. Opening date U39-124769 (5) Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)半絶縁性の半導体基板上に形成された電子親和力
の相異なる2種の半導体よ+−+ frる二重層の界面
近傍に滞留する電子群(二次元電子ガス)を導電媒体と
し、該導電を竿体をもって構成される導電路のインピー
ダンスを、前記半導体二重層のいずれかの上に設けられ
た制御電極をもって制御し、前記導電路は前記制御電極
を挾んで設けろわた一対の入・出力電極と接続されてな
る#導体装置において、前記半導体二重層を構成する牛
導体層のうち電子親和力の小さい層は更に2層に分割さ
れておI)、電子親和力の大入い層に接している層は高
濃度にn型不純物を含有する薄層であI)、′電子親和
力の大きい層に接していない層は制御電極下〒空乏化し
ていることを特徴をする生導体装置。
(1) A conductive medium is a group of electrons (two-dimensional electron gas) that stays near the interface of a double layer formed on a semi-insulating semiconductor substrate of two types of semiconductors with different electron affinities. The impedance of the conductive path constituted by the rod body is controlled by a control electrode provided on either of the semiconductor double layers, and the conductive path is formed by a pair of input wires provided with the control electrode in between. In the # conductor device connected to the output electrode, the layer with a low electron affinity among the conductor layers constituting the semiconductor double layer is further divided into two layers (I), which are in contact with the layer with a high electron affinity. A bioconductor device characterized in that the layer containing n-type impurities is a thin layer containing a high concentration of n-type impurities, and the layer that is not in contact with the layer having a high electron affinity is depleted under the control electrode.
(2)前記脚板と前記電子親和力の大きい層はガリウム
ヒ素〒あ()、前記電子Yl−利力0小さい層)Jアル
ミニウムガリウムヒ彎である、特許請求の範囲$1項記
爵の半導体装置。
(2) The semiconductor device according to claim 1, wherein the leg plate and the layer having a high electron affinity are gallium arsenide (a) (a), the electron Yl - a layer with a low interest rate) J aluminum gallium arsenide. .
JP23375682A 1982-12-29 1982-12-29 Semicondutor device Pending JPS59124769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23375682A JPS59124769A (en) 1982-12-29 1982-12-29 Semicondutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23375682A JPS59124769A (en) 1982-12-29 1982-12-29 Semicondutor device

Publications (1)

Publication Number Publication Date
JPS59124769A true JPS59124769A (en) 1984-07-18

Family

ID=16960083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23375682A Pending JPS59124769A (en) 1982-12-29 1982-12-29 Semicondutor device

Country Status (1)

Country Link
JP (1) JPS59124769A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0183146A2 (en) * 1984-11-19 1986-06-04 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. Semiconductor devices consisting of epitaxial material
US5060234A (en) * 1984-11-19 1991-10-22 Max-Planck Gesellschaft Zur Forderung Der Wissenschaften Injection laser with at least one pair of monoatomic layers of doping atoms
US5216260A (en) * 1984-11-19 1993-06-01 Max-Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V. Optically bistable semiconductor device with pairs of monoatomic layers separated by intrinsic layers
US5250822A (en) * 1991-03-26 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Field effect transistor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0183146A2 (en) * 1984-11-19 1986-06-04 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. Semiconductor devices consisting of epitaxial material
US5060234A (en) * 1984-11-19 1991-10-22 Max-Planck Gesellschaft Zur Forderung Der Wissenschaften Injection laser with at least one pair of monoatomic layers of doping atoms
US5216260A (en) * 1984-11-19 1993-06-01 Max-Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V. Optically bistable semiconductor device with pairs of monoatomic layers separated by intrinsic layers
US5329150A (en) * 1984-11-19 1994-07-12 Max Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V. Semiconductor photodetector devices with pairs of monoatomic layers separated by intrinsic layers
US5373186A (en) * 1984-11-19 1994-12-13 Max-Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V. Bipolar transistor with monoatomic base layer between emitter and collector layers
US5250822A (en) * 1991-03-26 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Field effect transistor

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