CN118352358A - A cascade casecode device and preparation method thereof - Google Patents

Abstract

The invention discloses a cascade casecode device and a preparation method thereof, wherein the cascade casecode device comprises: a substrate, a first conductive structure layer and a second conductive structure layer arranged on the substrate; the first electrode, the second electrode and the first grid electrode are arranged on the second conductive structure layer of the first area, and a first grid dielectric layer is arranged between the first grid electrode and the second conductive structure layer; the first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region; the third electrode is arranged on the electrode growth step and is spaced from the voltage-resistant drift layer; the second grid electrode is arranged in the grid electrode groove, and a second grid dielectric layer is arranged between the second grid electrode and the wall surface of the grid electrode groove; the fourth electrode is arranged on the second source-drain contact layer; the second electrode is electrically connected with the third electrode; the first gate electrode is electrically connected with the fourth electrode. The device of the invention has lower on-resistance and switching loss and smaller size.

Description

A cascade casecode device and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a cascade casecode device and a preparation method thereof.

Background technique

The third generation of wide bandgap semiconductors, with its advantages of high critical breakdown field strength, high electron mobility and high thermal conductivity, has shown great potential in the fields of high frequency, high power, high temperature, small size and light weight. However, the conventional HEMT working mode is depletion type, and its driving voltage is incompatible with the level of conventional driving chips, which makes the driving circuit complicated. In addition, the device will turn on under zero bias, which may cause safety hazards in power electronics applications. Therefore, the industry needs enhanced power devices.

The cascode cascade structure is an important way to realize enhancement-mode devices. The traditional cascode cascade structure adopts a common source and common gate structure, connecting the source and gate of the depletion-mode GaN transistor to the drain and source of the enhancement-mode Si transistor respectively, and the enhancement-mode Si MOSFET controls the switching state to achieve a higher threshold voltage and output power. However, due to the large series resistance between the two devices, the current cascode cascade structure has high power consumption and low efficiency.

Summary of the invention

Therefore, in order to solve the problem of the cascode cascade structure in the above-mentioned prior art, the present invention provides a cascade casecode device formed by cascading a MOS tube and a HEMT integrated on the same substrate, and provides a method for preparing the cascade casecode device.

To this end, according to a first aspect, the present invention provides a cascaded casecode device, comprising:

A substrate and a first conductive structure layer and a second conductive structure layer disposed on the substrate, wherein a heterojunction is formed between the first conductive structure layer and the second conductive structure layer; and the first conductive structure layer and the second conductive structure layer both have a first region and a second region spaced apart from each other;

A first electrode, a second electrode and a first gate are arranged on the second conductive structure layer in the first region, the first gate is located between the first electrode and the second electrode, and a first gate dielectric layer is arranged between the first gate and the second conductive structure layer;

The first source-drain contact layer, the withstand voltage drift layer, the inversion layer, and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region; the third electrode growth region in the second region is provided with an electrode growth step, and the electrode growth step runs through the second source-drain contact layer, the inversion layer, and the withstand voltage drift layer; the gate position region in the second region is provided with a gate groove, and the gate groove runs through the second source-drain contact layer and the inversion layer;

A third electrode is disposed on the electrode growth step and is spaced apart from the voltage-withstand drift layer;

A second gate is disposed in the gate groove, and a second gate dielectric layer is disposed between the second gate and a wall surface of the gate groove;

a fourth electrode, disposed on the second source-drain contact layer, and located on both sides of the second gate electrode together with the third electrode;

The second electrode is electrically connected to the third electrode; the second gate is the gate terminal of the cascade casecode device, the first electrode is a current terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode as another current terminal of the cascade casecode device.

In an optional embodiment, the first source-drain contact layer, the voltage-withstand drift layer, and the second source-drain contact layer are all N-type doped layers, and when the inversion layer is a P-type doped layer, the first electrode is the drain terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the source terminal of the cascade casecode device.

In an optional embodiment, the first source-drain contact layer, the voltage-withstand drift layer, and the second source-drain contact layer are all P-type doped layers, and when the inversion layer is an N-type doped layer, the first electrode is the source terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the drain terminal of the cascade casecode device.

In an optional embodiment, the first gate dielectric layer and the second gate dielectric layer are the same insulating layer, and the insulating layer further covers the first surface of the cascade casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode.

According to a second aspect, the present invention provides a method for preparing a cascaded casecode device, comprising the following steps:

Growing a first conductive structure layer, a second conductive structure layer, a first source-drain contact layer, a voltage-withstand drift layer, an inversion layer, and a second source-drain contact layer on the substrate in sequence to form a device substrate;

An isolation region is formed in the middle of the device substrate to separate the first conductive structure layer and the second conductive structure layer into a first region and a second region;

The second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the third electrode growth region in the second region and the entire first region are removed; at this time, an electrode growth step exposing the first source-drain contact layer is formed in the third electrode growth region in the second region;

removing the first source-drain contact layer in the first region;

Etching the voltage-resistant drift layer, the inversion layer and a portion of the second source-drain contact layer in the gate position region in the second region to form a gate groove;

Growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer in the gate position region in the first region and in the gate groove respectively;

A first electrode, a second electrode, a first gate, a third electrode, a fourth electrode, and a second gate are grown; the first gate is grown on the first gate dielectric layer, the first electrode and the second electrode are both grown on the second conductive structure layer of the first region, and are respectively located on both sides of the first gate; the third electrode is grown on the electrode growth step, the second gate is grown on the second gate dielectric layer, the fourth electrode is grown on the second source-drain contact layer, and is respectively located on both sides of the second gate electrode with the third electrode;

The second electrode is electrically connected to the third electrode, and the first gate is electrically connected to the fourth electrode; the second gate is the gate terminal of the cascade casecode device, the first electrode is a current terminal of the cascade casecode device, and the electrically connected first gate and fourth electrode are another current terminal of the cascade casecode device.

In an optional embodiment, the step of growing the first gate dielectric layer and the second gate dielectric layer on the second conductive structure layer in the gate position region in the first region and in the gate groove respectively comprises:

Growing an insulating layer on the first surface of the fabricated device;

The insulating layers in the first electrode position region, the second electrode position region, the third electrode position region and the fourth electrode position region are etched away; at this time, the insulating layer in the gate position region in the first region is the first gate dielectric layer, and the insulating layer in the gate groove is the second gate dielectric layer.

In an optional embodiment, the first source-drain contact layer, the voltage-withstand drift layer, and the second source-drain contact layer are all N-type doped layers, and when the inversion layer is a P-type doped layer, the first electrode is the drain terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the source terminal of the cascade casecode device.

In an optional embodiment, the first source-drain contact layer, the voltage-withstand drift layer, and the second source-drain contact layer are all P-type doped layers, and when the inversion layer is an N-type doped layer, the first electrode is the source terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the drain terminal of the cascade casecode device.

The technical solution provided by the present invention has the following advantages:

The cascade casecode device provided by the present invention forms a quasi-vertical enhancement MOS with a shorter current path and a lower on-resistance of a better conductive channel by separating a first region and a second region of a heterojunction structure layer (a first conductive structure layer and a second conductive structure layer) on the same substrate, and further arranges a first gate dielectric layer, a first electrode, a second electrode and a first gate in the first region to form a depletion-type HEMT, and further arranges a first source-drain contact layer, a withstand voltage drift layer, an inversion layer, and a second source-drain contact layer in the second region, and further arranges a second gate dielectric layer, a third electrode, a fourth electrode and a second gate to form a quasi-vertical enhancement MOS with a shorter current path and a better conductive channel, and finally achieves the low on-resistance and low switching loss performance requirements of the cascade casecode device formed by electrically connecting the electrodes of the two. At the same time, since the quasi-vertical enhancement MOS and the depletion-type HEMT have a smaller electron migration length and device size, the cascade casecode device also has a higher integration and a smaller size.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the structure of a cascaded casecode device provided in Embodiment 1 of the present invention;

FIG2 is a schematic diagram of a cascaded casecode device when the device corresponding to the second region provided by Embodiment 1 of the present invention in FIG1 is an NMOS;

FIG3 is a schematic diagram of a cascade casecode device when the device corresponding to the second region provided by Embodiment 1 of the present invention in FIG1 is a PMOS;

FIG4 is a flow chart of a method for preparing a cascade casecode device provided in Example 2 of the present invention;

5 to 10 are device structure diagrams obtained during the implementation of a method for preparing a cascaded casecode device provided in Example 2 of the present invention.

Detailed ways

The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

Example 1

The present embodiment provides a cascade casecode device, as shown in FIG1 , the cascade casecode device includes a substrate, a first conductive structure layer, a second conductive structure layer, a first gate dielectric layer, a first electrode (shown in the figure as electrode one), a second electrode (shown in the figure as electrode two), a first gate (shown in the figure as gate one), a first source-drain contact layer, a withstand voltage drift layer, an inversion layer, a second source-drain contact layer, a second gate dielectric layer, a third electrode (shown in the figure as electrode three), a fourth electrode (shown in the figure as electrode four) and a second gate (shown in the figure as gate two).

As shown in the figure, the first conductive structure layer and the second conductive structure layer are sequentially arranged on the substrate, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer, and both the first conductive structure layer and the second conductive structure layer have a first region and a second region separated from each other.

As shown in FIG1 , the first electrode, the second electrode and the first gate are all arranged on the second conductive structure layer of the first region, the first gate is located between the first electrode and the second electrode, and the first gate dielectric layer is arranged between the first gate and the second conductive structure layer.

As shown in the figure, the first source-drain contact layer, the voltage-resistant drift layer, the inversion layer and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region; the third electrode growth region in the second region is provided with an electrode growth step, which runs through the second source-drain contact layer, the inversion layer and the voltage-resistant drift layer; the gate position region in the second region is provided with a gate groove, which runs through the second source-drain contact layer and the inversion layer.

Among them, as shown in Figure 1, the third electrode is arranged on the electrode growth step and is spaced apart from the voltage-resistant drift layer; the second gate is arranged in the gate groove, and the second gate dielectric layer is arranged between the second gate and the wall of the gate groove; the fourth electrode is arranged on the second source-drain contact layer, and is located on both sides of the second gate electrode respectively with the third electrode.

1, the second electrode is electrically connected to the third electrode, and the first gate is electrically connected to the fourth electrode. For the cascade casecode device in this embodiment, the second gate is its gate terminal, the first electrode is its one current terminal, and the first gate is electrically connected to the fourth electrode to form its other current terminal.

In specific implementation, the quasi-vertical enhancement MOS corresponding to the second region in this embodiment can be NMOS or PMOS; when it is NMOS, the first source-drain contact layer, the withstand voltage drift layer and the second source-drain contact layer are all N-type doped layers, and the inversion layer is a P-type doped layer, and at this time, as shown in Figure 2, the first electrode is the drain terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the source terminal of the cascade casecode device; when it is PMOS, the first source-drain contact layer, the withstand voltage drift layer and the second source-drain contact layer are all P-type doped layers, and the inversion layer is an N-type doped layer, and at this time, as shown in the figure, the first electrode is the source terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the drain terminal of the cascade casecode device.

In specific implementation, GaN material with high electron mobility, high saturation drift velocity, high breakdown electric field strength and high thermal conductivity can be used as the structural layer material of the casecode device in this embodiment, so that the casecode device has more advantages in high-frequency and high-power applications. At this time, the first conductive structure layer and the second conductive structure layer can be a GaN layer and an AlGaN layer respectively; at the same time, when the quasi-vertical enhancement MOS corresponding to the second region is NMOS, the first source-drain contact layer, the withstand voltage drift layer, the inversion layer and the second source-drain contact layer can be the first N-GaN layer, the N-GaN drift layer, the P-GaN layer and the second N-GaN layer in sequence; when the quasi-vertical enhancement MOS corresponding to the second region is PMOS, the first source-drain contact layer, the withstand voltage drift layer, the inversion layer and the second source-drain contact layer can be the first P-GaN layer, the P-GaN drift layer, the N-GaN layer and the second P-GaN layer in sequence.

In a specific implementation, the first N-GaN layer, the N-GaN drift layer, and the second N-GaN layer in NMOS can be obtained by doping Si elements in GaN, and the Si doping concentration of each layer can be different; the P-GaN layer in NMOS can be obtained by doping Mg elements in GaN. In a specific implementation, the specific Si doping concentration of each layer can be set according to the threshold voltage and on-current density of the device in the application scenario.

In a specific implementation, the first P-GaN layer, the P-GaN drift layer, and the second N-GaN layer in the PMOS can be obtained by doping Mg elements in GaN, and the Mg doping concentration of each layer can be different; the N-GaN layer in the PMOS can be obtained by doping Si elements in GaN. In a specific implementation, the specific Mg doping concentration of each layer can be set according to the threshold voltage requirements of the device in the application scenario.

In a specific implementation, in order to improve the quality of the first conductive structure layer disposed on the substrate, as shown in the figure, a buffer layer can be disposed between the substrate and the first conductive structure layer. Specifically, when the first conductive structure layer is a GaN layer, the buffer layer can be correspondingly configured as a GaN buffer layer.

In a specific implementation, the materials of the first gate dielectric layer and _{the second gate dielectric layer can be one or more of SiN, SiO2, Al2O3, HfO2, ZrO2, La2O3 , HfAlOX , HfSiOX , HfLaOX} , HfZrOX, HfSiON, etc. In addition, those skilled in the art should understand that FIG1 is based on an example of the first gate dielectric layer and the second gate dielectric layer being the same insulating layer, which can be prepared at the same time to reduce the device preparation cost. However, in actual applications, the first gate dielectric layer and the second gate dielectric layer can be set as different dielectric layers according to the requirements of specific application scenarios.

In a specific implementation, the upper surface of the cascaded casecode device in this embodiment when in the state shown in FIG. 1 is taken as the first surface. Then,

If the first gate dielectric layer and the second gate dielectric layer are made of different materials, the first gate dielectric layer may be provided first:

First, a first gate dielectric is grown on the first surface of the casecode device. After that, all the remaining first gate dielectrics except the gate position region in the first region can be etched away to complete the arrangement of the first gate dielectric layer located only between the first gate and the second conductive structure layer. Alternatively, only the first gate dielectrics in the first electrode position region, the second electrode position region, the third electrode position region and the fourth electrode position region can be etched away so that the first gate dielectric layer also covers the first surface of the cascaded casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode, thereby playing a role in passivation and reducing interface states.

Then set the second dielectric layer:

First, a second gate dielectric is grown on the first surface of the casecode device. After that, all the second gate dielectrics except the gate groove can be etched away to complete the arrangement of the second gate dielectric layer located only between the second gate and the wall of the gate groove. Alternatively, only the second gate dielectrics in the first electrode position region, the second electrode position region, the third electrode position region and the fourth electrode position region can be etched away so that the second gate dielectric layer also covers the first surface of the cascaded casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode, and plays a role in passivation and reducing interface states (alone or in cooperation with the first gate dielectric layer).

If the first gate dielectric layer and the second gate dielectric layer are made of the same material, an insulating material is grown on the first surface of the casecode device. After that, all the remaining insulating materials except the gate position area and the gate groove in the first region can be etched away to complete the arrangement of the first gate dielectric layer located only between the first gate and the second conductive structure layer and the second gate dielectric layer located only between the second gate and the gate groove wall. Alternatively, only the insulating materials in the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area can be etched away to obtain an insulating layer that not only serves as the first gate dielectric layer and the second gate dielectric layer, but also covers the first surface of the cascade casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode (this situation is shown as an example in FIG. 1 ).

In summary, the cascaded casecode device in this embodiment forms a depletion-type HEMT by separating the first region and the second region by a heterojunction structure layer (a first conductive structure layer and a second conductive structure layer) on the same substrate, and further arranges a first gate dielectric layer, a first electrode, a second electrode and a first gate in the first region, and further arranges a first source-drain contact layer, a voltage-resistant drift layer, an inversion layer, and a second source-drain contact layer in the second region, and further arranges a second gate dielectric layer, a third electrode, a fourth electrode and a second gate, so as to form a quasi-vertical enhancement MOS with a shorter current path and a better conductive channel and a lower on-resistance, and finally achieves the low on-resistance and low switching loss performance requirements of the cascaded casecode device formed by electrically connecting the electrodes of the two; at the same time, since the quasi-vertical enhancement MOS and the depletion-type HEMT have a smaller electron migration length and device size, the cascaded casecode device also has a higher integration and a smaller size.

Example 2

This embodiment provides a method for preparing a cascaded casecode device, which is the method for preparing the cascaded casecode device in the above-mentioned embodiment 1, so the specific scheme of this embodiment can be understood with reference to the content of embodiment 1. As shown in FIG4 , the method includes the following steps:

S401: sequentially growing a first conductive structure layer, a second conductive structure layer, a first source-drain contact layer, a voltage-withstand drift layer, an inversion layer, and a second source-drain contact layer on a substrate to form a device substrate.

FIG5 is a schematic diagram of the device structure obtained through this step.

S402: forming an isolation region in the middle of the device substrate to separate the first conductive structure layer and the second conductive structure layer into a first region and a second region.

FIG6 is a schematic diagram of the device structure obtained through this step.

In specific implementation, the first region and the second region may be defined by a hard mask or photoresist, and then an isolation region may be formed by etching an isolation groove or performing ion implantation between the two (FIG. 6 takes the isolation groove as an example).

In a specific implementation, when a buffer layer is grown between the substrate and the first conductive structure layer, as shown in FIG6 , the isolation region reaches the surface of the buffer layer; when the first conductive structure layer is directly grown on the substrate, the isolation region reaches the surface of the substrate.

S403: removing the second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the third electrode growth region in the second region and the entire first region.

At this time, as shown in FIG. 7 , an electrode growth step is formed at the third electrode growth region in the second region, exposing the first source-drain contact layer.

In specific implementation, photolithography or electron beam exposure or other processes may be used to etch away the second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the first region and to form an electrode growth step.

Those skilled in the art should understand that, based on the need for a gap between the third electrode grown on the first source-drain contact layer and the withstand voltage drift layer grown on the first source-drain contact layer, the length of the electrode growth step in this step is greater than the length of the third electrode. In specific implementation, when the first gate dielectric layer and/or the second gate dielectric layer also cover the first surface of the cascade casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode, the bottom surface of the electrode growth step except the third electrode and the side surface of the electrode growth step are also covered, which can further achieve the isolation of the third electrode and the withstand voltage drift layer.

S404: removing the first source-drain contact layer in the first region.

During specific implementation, the first source-drain contact layer in the first region may also be removed by etching using processes such as photolithography or electron beam exposure.

S405: etching the voltage-withstand drift layer, the inversion layer and a portion of the second source-drain contact layer in the gate position region in the second region to form a gate groove.

FIG8 is a schematic diagram of the device structure obtained through this step.

S406: Growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer in the gate position region in the first region and in the gate groove respectively.

In a specific implementation, the materials of the first gate dielectric layer and _the second gate dielectric layer can be one or more of SiN, _SiO2 , _Al2O3 , _HfO2 , _ZrO2 , _La2O3 , _HfAlOX , HfSiOX, HfLaOX, HfZrOX, HfSiON and the like.

In the specific implementation, in order to reduce the production and preparation cost, it can be set as the same insulating layer. Specifically, the insulating layer can be first grown on the first surface of the prepared device by chemical vapor deposition or other processes (as shown in Figure 9), and then the insulating layer in the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area can be etched and removed. Then, the part of the insulating layer located in the gate position area in the first area is the first gate dielectric layer, and the part located in the gate groove is the second gate dielectric layer. At this time, on the basis of completing the first gate dielectric layer and the second gate dielectric layer at the same time, the other insulating layer parts also realize the surface passivation of the device.

S407: growing a first electrode, a second electrode, a first gate electrode, a third electrode, a fourth electrode and a second gate electrode.

As shown in Figure 10, the first gate is grown on the first gate dielectric layer, the first electrode and the second electrode are both grown on the second conductive structure layer of the first region, and are respectively located on both sides of the first gate; the third electrode is grown on the electrode growth step, the second gate is grown on the second gate dielectric layer, and the fourth electrode is grown on the second source and drain contact layer, and is respectively located on both sides of the second gate electrode with the third electrode.

In a specific implementation, the first electrode, the second electrode, the third electrode and the fourth electrode can be made of the same metal material, and thus can be grown synchronously. For example, the regions corresponding to the four electrodes can be defined by photolithography, and then a metal stack of titanium/aluminum/nickel/gold can be continuously deposited by electron beam evaporation or other processes, and then the metal outside the regions corresponding to the four electrodes can be stripped, and annealing can be performed to form an alloy ohmic contact, thereby completing the growth of the four electrodes.

In specific implementation, the first gate and the second gate can be made of the same metal material, and thus can be grown synchronously. For example, the regions corresponding to the two gates can be defined by photolithography, and then a nickel/gold metal layer can be grown by physical vapor deposition or other processes, and then excess metal can be stripped off to complete the growth of the first gate and the second gate.

S408: electrically connecting the second electrode to the third electrode, and electrically connecting the first gate to the fourth electrode.

In this embodiment, as shown in FIGS. 1 to 3 , the second gate is a gate terminal of the cascaded casecode device, the first electrode is a current terminal of the cascaded casecode device, and the electrically connected first gate and fourth electrode are another current terminal of the cascaded casecode device.

In specific implementation, the electrical connection between the second electrode and the third electrode and between the first gate and the fourth electrode can be completed by growing a metal layer. For example, photoresist can be firstly spin-coated on the first surface of the prepared device, and then the cascade region of the second electrode and the third electrode and the cascade region of the first gate and the fourth electrode can be defined by electron beam exposure, and then a nickel/gold metal layer is grown by physical vapor deposition and other processes to form contact, so as to realize the electrical connection between the second electrode and the third electrode and the electrical connection between the first gate and the fourth electrode.

Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims (8)

1. A cascaded casecode device, comprising: A substrate and a first conductive structure layer and a second conductive structure layer disposed on the substrate, wherein a heterojunction is formed between the first conductive structure layer and the second conductive structure layer; and the first conductive structure layer and the second conductive structure layer both have a first region and a second region spaced apart from each other; A first electrode, a second electrode and a first gate are arranged on the second conductive structure layer in the first region, the first gate is located between the first electrode and the second electrode, and a first gate dielectric layer is arranged between the first gate and the second conductive structure layer; A first source-drain contact layer, a withstand voltage drift layer, an inversion layer, and a second source-drain contact layer are sequentially arranged on the second conductive structure layer in the second region; an electrode growth step is arranged in the third electrode growth region in the second region, and the electrode growth step runs through the second source-drain contact layer, the inversion layer, and the withstand voltage drift layer; a gate position region in the second region is arranged with a gate groove, and the gate groove runs through the second source-drain contact layer and the inversion layer; a third electrode, disposed on the electrode growth step and spaced apart from the voltage-withstand drift layer; A second gate is disposed in the gate groove, and a second gate dielectric layer is disposed between the second gate and a wall surface of the gate groove; a fourth electrode, disposed on the second source-drain contact layer, and located on both sides of the second gate electrode together with the third electrode; The second electrode is electrically connected to the third electrode; the second gate is the gate terminal of the cascade casecode device, the first electrode is a current terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode as another current terminal of the cascade casecode device. 2. The cascaded casecode device according to claim 1, characterized in that the first source-drain contact layer, the withstand voltage drift layer and the second source-drain contact layer are all N-type doped layers, and when the inversion layer is a P-type doped layer, the first electrode is the drain terminal of the cascaded casecode device, and the first gate is electrically connected to the fourth electrode to serve as the source terminal of the cascaded casecode device. 3. The cascade casecode device according to claim 1, characterized in that the first source-drain contact layer, the withstand voltage drift layer and the second source-drain contact layer are all P-type doped layers, and when the inversion layer is an N-type doped layer, the first electrode is the source terminal of the cascade casecode device, and the first gate is electrically connected to the fourth electrode to serve as the drain terminal of the cascade casecode device. 4. The cascade casecode device according to any one of claims 1 to 3, characterized in that the first gate dielectric layer and the second gate dielectric layer are the same insulating layer, and the insulating layer further covers the first surface of the cascade casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode. 5. A method for preparing a cascaded casecode device, comprising the following steps: Growing a first conductive structure layer, a second conductive structure layer, a first source-drain contact layer, a voltage-withstand drift layer, an inversion layer, and a second source-drain contact layer on the substrate in sequence to form a device substrate; forming an isolation region in the middle of the device substrate to separate the first conductive structure layer and the second conductive structure layer into a first region and a second region; The second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the third electrode growth region in the second region and the entire first region are removed; at this time, an electrode growth step is formed in the third electrode growth region in the second region, exposing the first source-drain contact layer; removing the first source-drain contact layer in the first region; Etching the withstand voltage drift layer, the inversion layer and a portion of the second source-drain contact layer in the gate position region in the second region to form a gate groove; Growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer in the gate position region in the first region and in the gate groove respectively; Growing a first electrode, a second electrode, a first gate, a third electrode, a fourth electrode, and a second gate; the first gate is grown on the first gate dielectric layer, the first electrode and the second electrode are both grown on the second conductive structure layer of the first region, and are respectively located on both sides of the first gate; the third electrode is grown on the electrode growth step, the second gate is grown on the second gate dielectric layer, the fourth electrode is grown on the second source-drain contact layer, and is respectively located on both sides of the second gate electrode with the third electrode; The second electrode is electrically connected to the third electrode, and the first gate is electrically connected to the fourth electrode; the second gate is a gate terminal of the cascade casecode device, the first electrode is a current terminal of the cascade casecode device, and the electrically connected first gate and fourth electrode are another current terminal of the cascade casecode device. 6. The method for preparing a cascade casecode device according to claim 5, characterized in that the step of growing the first gate dielectric layer and the second gate dielectric layer on the second conductive structure layer in the gate position region in the first region and in the gate groove respectively comprises: Growing an insulating layer on the first surface of the fabricated device; The insulating layer in the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area is etched away; at this time, the insulating layer in the gate position area in the first area is the first gate dielectric layer, and the insulating layer in the gate groove is the second gate dielectric layer. 7. The method for preparing a cascaded casecode device according to claim 5, wherein the first source-drain contact layer, the withstand voltage drift layer and the second source-drain contact layer are all N-type doped layers, and when the inversion layer is a P-type doped layer, the first electrode is the drain terminal of the cascaded casecode device, and the first gate is electrically connected to the fourth electrode to serve as the source terminal of the cascaded casecode device. 8. The method for preparing a cascaded casecode device according to claim 5, wherein the first source-drain contact layer, the withstand voltage drift layer and the second source-drain contact layer are all P-type doped layers, and when the inversion layer is an N-type doped layer, the first electrode is the source terminal of the cascaded casecode device, and the first gate is electrically connected to the fourth electrode to serve as the drain terminal of the cascaded casecode device.