CN118352358A - Cascade casecode device and preparation method thereof - Google Patents
Cascade casecode device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a cascade casecode device and a preparation method thereof, wherein the cascade casecode device comprises: a substrate, a first conductive structure layer and a second conductive structure layer arranged on the substrate; the first electrode, the second electrode and the first grid electrode are arranged on the second conductive structure layer of the first area, and a first grid dielectric layer is arranged between the first grid electrode and the second conductive structure layer; the first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region; the third electrode is arranged on the electrode growth step and is spaced from the voltage-resistant drift layer; the second grid electrode is arranged in the grid electrode groove, and a second grid dielectric layer is arranged between the second grid electrode and the wall surface of the grid electrode groove; the fourth electrode is arranged on the second source-drain contact layer; the second electrode is electrically connected with the third electrode; the first gate electrode is electrically connected with the fourth electrode. The device of the invention has lower on-resistance and switching loss and smaller size.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a cascade casecode device and a preparation method thereof.
Background
The third generation wide bandgap semiconductor has the advantages of high critical breakdown field strength, high electron mobility, high thermal conductivity and the like, and has great potential in the fields of high frequency, high power, high temperature, miniaturization and light weight. However, the conventional HEMT operation mode belongs to a depletion mode, and its driving voltage is not compatible with the level of the conventional driving chip, resulting in a complicated driving circuit. In addition, the device will conduct under zero bias, which may raise a safety hazard in power electronics applications. Thus, there is a need in the industry for enhanced power devices.
The Cascade architecture is an important implementation of the enhancement mode device. The traditional cascode structure adopts a common-source common-gate structure, the source electrode and the grid electrode of the depletion type GaN transistor are respectively connected with the drain electrode and the source electrode of the enhancement type Si transistor, and the enhancement type Si MOSFET controls the switch state so as to realize higher threshold voltage and output power. However, the serial resistance between the two devices is larger, so that the power consumption and the efficiency of the current Cascade structure are larger.
Disclosure of Invention
Therefore, in order to solve the problem of the Cascade structure in the prior art, the invention provides a cascade casecode device formed by cascading a MOS tube and a HEMT, which are integrated on the same substrate, and a preparation method of the cascade casecode device.
To this end, according to a first aspect, the present invention provides a cascode casecode device comprising:
The device comprises a substrate, a first conductive structure layer and a second conductive structure layer, wherein the first conductive structure layer and the second conductive structure layer are arranged on the substrate, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer; the first conductive structure layer and the second conductive structure layer are respectively provided with a first area and a second area which are spaced;
the first electrode, the second electrode and the first grid electrode are arranged on the second conductive structure layer of the first area, the first grid electrode is positioned between the first electrode and the second electrode, and a first grid dielectric layer is arranged between the first grid electrode and the second conductive structure layer;
the first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region; an electrode growth step is arranged in a third electrode growth area in the second area and penetrates through all of the second source-drain contact layer, the inversion layer and the withstand voltage drift layer; a gate groove is formed in the gate position area in the second area, and penetrates through the second source-drain contact layer and the inversion layer;
The third electrode is arranged on the electrode growth step and is spaced from the voltage-resistant drift layer;
the second grid electrode is arranged in the grid electrode groove, and a second grid dielectric layer is arranged between the second grid electrode and the wall surface of the grid electrode groove;
The fourth electrode is arranged on the second source-drain contact layer and is respectively positioned at two sides of the second gate electrode with the third electrode;
the second electrode is electrically connected with the third electrode; the second gate is a gate terminal of the cascode casecode device, the first electrode is one current terminal of the cascode casecode device, and the first gate is electrically connected with the fourth electrode to serve as the other current terminal of the cascode casecode device.
In an alternative embodiment, the first source-drain contact layer, the voltage-withstanding drift layer and the second source-drain contact layer are all N-doped layers, when the inversion layer is a P-doped layer, the first electrode is the drain terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode and then serves as the source terminal of the cascode casecode device.
In an alternative embodiment, the first source-drain contact layer, the voltage-withstanding drift layer and the second source-drain contact layer are P-doped layers, when the inversion layer is an N-doped layer, the first electrode is a source terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode and serves as a drain terminal of the cascode casecode device.
In an alternative embodiment, the first gate dielectric layer and the second gate dielectric layer are the same insulating layer, and the insulating layer also covers the first surface of the cascade casecode device except for the first electrode, the second electrode, the third electrode, and the fourth electrode.
According to a second aspect, the invention provides a method for manufacturing a cascade casecode device, comprising the steps of:
Sequentially growing a first conductive structure layer, a second conductive structure layer, a first source-drain contact layer, a voltage-withstanding drift layer, an inversion layer and a second source-drain contact layer on a substrate to form a device substrate;
Forming an isolation region in the middle of the device substrate to separate the first conductive structure layer and the second conductive structure layer into a first region and a second region;
Removing the second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the third electrode growth region in the second region and all the first regions; at the moment, an electrode growth step exposing the first source-drain contact layer is formed at the third electrode growth area in the second area;
removing the first source-drain contact layer of the first region;
etching the voltage-resistant drift layer, the inversion layer and part of the second source-drain contact layer in the gate position area in the second area to form a gate groove;
Respectively growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer and the gate groove in the gate position area in the first area;
Growing a first electrode, a second electrode, a first grid electrode, a third electrode, a fourth electrode and a second grid electrode; the first grid electrode grows on the first grid dielectric layer, and the first electrode and the second electrode are both grown on the second conductive structure layer of the first area and are respectively positioned at two sides of the first grid electrode; the third electrode grows on the electrode growth step, the second grid electrode grows on the second grid dielectric layer, the fourth electrode grows on the second source-drain contact layer, and the fourth electrode and the third electrode are respectively positioned on two sides of the second grid electrode;
electrically connecting the second electrode with the third electrode, and electrically connecting the first grid with the fourth electrode; the second gate is a gate end of the cascade casecode device, the first electrode is one current end of the cascade casecode device, and the first gate and the fourth electrode after being electrically connected are cascaded casecode device and the other current end.
In an alternative embodiment, the step of growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer in the gate position region and in the gate trench in the first region, respectively, specifically includes:
Growing an insulating layer on a first surface of the device;
Etching to remove the insulating layers of the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area; at this time, the insulating layer in the gate position region in the first region is the first gate dielectric layer, and the insulating layer in the gate trench is the second gate dielectric layer.
In an alternative embodiment, the first source-drain contact layer, the voltage-withstanding drift layer and the second source-drain contact layer are all N-doped layers, when the inversion layer is a P-doped layer, the first electrode is the drain terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode and then serves as the source terminal of the cascode casecode device.
In an alternative embodiment, the first source-drain contact layer, the voltage-withstanding drift layer and the second source-drain contact layer are P-doped layers, when the inversion layer is an N-doped layer, the first electrode is a source terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode and serves as a drain terminal of the cascode casecode device.
The technical scheme provided by the invention has the following advantages:
According to the cascade casecode device provided by the invention, a heterojunction structure layer (a first conductive structure layer and a second conductive structure layer) on the same substrate is separated into a first area and a second area, a first gate dielectric layer, a first electrode, a second electrode and a first grid electrode are further arranged in the first area to form a depletion type HEMT, a first source-drain contact layer, a voltage-resistant drift layer, an inversion layer and a second source-drain contact layer are further arranged in the second area, a second gate dielectric layer, a third electrode, a fourth electrode and a second grid electrode are further arranged, so that a quasi-vertical enhancement type MOS with a shorter current path and a better conductive channel and lower on resistance is formed, and finally the low on resistance and low switching loss performance requirements of the cascade casecode device formed by electrically connecting the electrodes of the first gate dielectric layer and the second electrode can be realized; meanwhile, the cascaded casecode device also has higher integration and smaller size because the quasi-vertical enhancement mode MOS and depletion mode HEMT have smaller electron transfer length and device size.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a cascaded casecode device provided in embodiment 1 of the present invention;
Fig. 2 is a schematic diagram of a cascaded casecode device when the second region corresponding device provided in embodiment 1 of the present invention is an NMOS device;
Fig. 3 is a schematic diagram of a cascaded casecode device when the second region corresponding device provided in embodiment 1 of the present invention is PMOS;
fig. 4 is a flow chart of a method for preparing a cascade casecode device according to embodiment 2 of the present invention;
Fig. 5 to fig. 10 are block diagrams of devices prepared in the implementation process of the preparation method of the cascade casecode device provided in embodiment 2 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
The present embodiment provides a cascade casecode device, as shown in fig. 1, where the cascade casecode device includes a substrate, a first conductive structure layer, a second conductive structure layer, a first gate dielectric layer, a first electrode (shown as electrode one in the figure), a second electrode (shown as electrode two in the figure), a first gate (shown as gate one in the figure), a first source-drain contact layer, a voltage-withstanding drift layer, an inversion layer, a second source-drain contact layer, a second gate dielectric layer, a third electrode (shown as electrode three in the figure), a fourth electrode (shown as electrode four in the figure), and a second gate (shown as gate two in the figure).
The first conductive structure layer and the second conductive structure layer are sequentially arranged on the substrate as shown in the figure, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer. And the first conductive structure layer and the second conductive structure layer each have first and second regions that are spaced apart.
As shown in fig. 1, the first electrode, the second electrode and the first gate are all disposed on the second conductive structure layer in the first region, the first gate is located between the first electrode and the second electrode, and the first gate dielectric layer is disposed between the first gate and the second conductive structure layer.
The first source-drain contact layer, the voltage-resistant drift layer, the inversion layer and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region as shown in the figure; the third electrode growth area in the second area is provided with an electrode growth step which penetrates through all of the second source-drain contact layer, the inversion layer and the withstand voltage drift layer; a gate groove is arranged in the gate position area in the second area, and penetrates through the second source-drain contact layer and the inversion layer.
The third electrode is arranged on the electrode growth step and is spaced from the voltage-resistant drift layer as shown in fig. 1; the second grid electrode is arranged in the grid electrode groove, and the second grid dielectric layer is arranged between the second grid electrode and the wall surface of the grid electrode groove; the fourth electrode is arranged on the second source-drain contact layer and is respectively positioned at two sides of the second gate electrode with the third electrode.
As shown in fig. 1, the second electrode is electrically connected to the third electrode, and the first gate is electrically connected to the fourth electrode. For the cascode casecode device in this embodiment, the second gate is its gate terminal, the first electrode is its one current terminal, and the first gate is its other current terminal after being electrically connected to the fourth electrode.
In specific implementation, the quasi-vertical enhancement MOS corresponding to the second region in this embodiment may be NMOS or PMOS; when the device is NMOS, the first source-drain contact layer, the voltage-withstanding drift layer and the second source-drain contact layer are all N-type doped layers, the inversion layer is a P-type doped layer, and at this time, as shown in FIG. 2, the first electrode is the drain end of the cascade casecode device, and the first gate is electrically connected with the fourth electrode and then serves as the source end of the cascade casecode device; when the device is a PMOS, the first source-drain contact layer, the voltage-withstanding drift layer, and the second source-drain contact layer are all P-doped layers, the inversion layer is an N-doped layer, and at this time, as shown in the figure, the first electrode is the source terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode and then serves as the drain terminal of the cascode casecode device.
In specific implementation, a GaN material with high electron mobility, high saturation drift velocity, high breakdown field strength and high thermal conductivity may be used as a material of a structural layer of the casecode device in this embodiment, so that the casecode device has advantages in high-frequency and high-power applications, where the first conductive structural layer and the second conductive structural layer may be a GaN layer and an AlGaN layer, respectively; meanwhile, when the quasi-vertical enhancement type MOS corresponding to the second region is NMOS, the first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer can be sequentially a first N-GaN layer, an N-GaN drift layer, a P-GaN layer and a second N-GaN layer; when the quasi-vertical enhancement type MOS corresponding to the second region is a PMOS, the first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer may be a first P-GaN layer, a P-GaN drift layer, an N-GaN layer and a second P-GaN layer in this order.
In the implementation, the first N-GaN layer, the N-GaN drift layer and the second N-GaN layer in the NMOS can be obtained by doping Si element in GaN, and the Si doping concentrations of the layers can be different; the P-GaN layer in the NMOS can be obtained by doping Mg element in GaN. In the implementation, specific Si doping concentration of each layer can be set according to the requirements of threshold voltage and on-current density of the device in an application scene.
In the implementation, the first P-GaN layer, the P-GaN drift layer and the second N-GaN layer in the PMOS can be obtained by doping Mg element in GaN, and the Mg doping concentrations of the layers can be different; the N-GaN layer in PMOS can be obtained by doping Si element in GaN. In the implementation, specific Mg doping concentrations of each layer can be set according to the requirement of the threshold voltage of the device in the application scene.
In practice, a buffer layer may be disposed between the substrate and the first conductive structure layer as shown in the figure in order to improve the quality of the first conductive structure layer disposed on the substrate. Specifically, when the first conductive structure layer is a GaN layer, the buffer layer may be correspondingly provided as a GaN buffer layer.
In the implementation, the materials of the first gate dielectric layer and the second gate dielectric layer may be one or more materials such as SiN、SiO2、Al2O3、HfO2、ZrO2、La2O3、HfAlOX、HfSiOX、HfLaOX、HfZrOX、HfSiON. In addition, it should be understood by those skilled in the art that fig. 1 illustrates a case where the first gate dielectric layer and the second gate dielectric layer are the same insulating layer, which can be manufactured simultaneously, thereby reducing the manufacturing cost of the device, but in practical application, the first gate dielectric layer and the second gate dielectric layer may be configured as different dielectric layers according to the requirements in a specific application scenario.
In implementation, the upper surface of the cascade casecode device in the state shown in fig. 1 in this embodiment is taken as the first surface. Then the first time period of the first time period,
If the first gate dielectric layer and the second gate dielectric layer are made of different materials, the first gate dielectric layer may be first set:
Firstly, growing a first gate dielectric on the first surface of the casecode device, and then, etching and removing all the first gate dielectrics except for a gate position area in the first area to finish the arrangement of a first gate dielectric layer only between the first gate and a second conductive structure layer, and also, etching and removing the first gate dielectrics only in a first electrode position area, a second electrode position area, a third electrode position area and a fourth electrode position area to enable the first gate dielectric layer to also cover the first surface of the cascade casecode device except for the first electrode, the second electrode, the third electrode and the fourth electrode, thereby playing a role in passivation and interface state reduction;
and a second dielectric layer is arranged:
And firstly growing a second gate dielectric on the first surface of the casecode device, and then etching and removing all the second gate dielectrics except the gate groove to finish the arrangement of a second gate dielectric layer only between the second gate and the wall surface of the gate groove, and also etching and removing only the second gate dielectrics of the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area, so that the second gate dielectric layer also covers the first surface of the cascade casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode (singly or cooperatively with the first gate dielectric layer) to play a role of passivation and interface state reduction.
If the first gate dielectric layer and the second gate dielectric layer are made of the same material, then an insulator is grown on the first surface of the casecode device, and then all the insulators except for the gate position area and the gate trench in the first area can be etched and removed, so that the arrangement of the first gate dielectric layer only between the first gate and the second conductive structure layer and the second gate dielectric layer only between the second gate and the gate trench wall surface can be completed, and also the insulators only in the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area can be etched and removed, so that the insulator not only serves as the first gate dielectric layer and the second gate dielectric layer, but also covers the insulator layers of the first surfaces except for the first electrode, the second electrode, the third electrode and the fourth electrode of the cascade casecode device (in fig. 1, this is shown by way of example).
In summary, in the cascade casecode device in this embodiment, by separating the heterojunction structure layer (the first conductive structure layer and the second conductive structure layer) on the same substrate into the first region and the second region, and further disposing the first gate dielectric layer, the first electrode, the second electrode and the first gate electrode in the first region to form a depletion HEMT, first disposing the first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer in the second region, and further disposing the second gate dielectric layer, the third electrode, the fourth electrode and the second gate electrode in the second region, a quasi-vertical enhancement type MOS with a shorter current path and a better conductive channel and a lower on-resistance is formed, so as to finally realize the low on-resistance and low switching loss performance requirements of the cascade casecode device formed by electrically connecting the electrodes of the two. Meanwhile, the cascaded casecode device also has higher integration and smaller size because the quasi-vertical enhancement mode MOS and depletion mode HEMT have smaller electron transfer length and device size.
Example 2
The present embodiment provides a method for manufacturing a cascade casecode device, which is the method for manufacturing a cascade casecode device in the above embodiment 1, so that the specific scheme of the present embodiment can be understood with reference to the content of embodiment 1. As shown in fig. 4, the method comprises the steps of:
S401: and sequentially growing a first conductive structure layer, a second conductive structure layer, a first source-drain contact layer, a voltage-withstanding drift layer, an inversion layer and a second source-drain contact layer on the substrate to form a device substrate.
Fig. 5 is a schematic diagram of the structure of the device obtained by this step.
S402: an isolation region is formed in the middle of the device substrate to separate the first conductive structure layer and the second conductive structure layer into a first region and a second region.
Fig. 6 is a schematic diagram of the structure of the device obtained by this step.
In the embodiment, the first region and the second region may be defined by a hard mask, a photoresist, or the like, and then an isolation trench is etched or ion implantation is performed between the first region and the second region to form an isolation region (the isolation trench is shown in fig. 6 as an example).
In the implementation, when a buffer layer is further grown between the substrate and the first conductive structure layer, as shown in fig. 6, the isolation region reaches the surface of the buffer layer; the isolation region reaches the substrate surface when the first conductive structure layer is grown directly on the substrate.
S403: and removing the second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the third electrode growth region in the second region and all the first region.
At this time, as shown in fig. 7, an electrode growth step exposing the first source-drain contact layer is formed at the third electrode growth region in the second region.
In the specific implementation, the second source-drain contact layer, the inversion layer and the voltage-resistant drift layer of the first region can be etched and removed by adopting photoetching or electron beam exposure and other processes, and an electrode growth step is formed.
It should be understood by those skilled in the art that the length of the electrode growth step in this step is longer than the length of the third electrode based on the following requirement of having a space between the third electrode grown on the first source-drain contact layer and the voltage-resistant drift layer grown on the first source-drain contact layer. In the specific implementation, when the first gate dielectric layer and/or the second gate dielectric layer described below also cover the first surfaces of the cascade casecode device except the first electrode, the second electrode, the third electrode and the fourth electrode, the part except the third electrode in the bottom surface of the electrode growth step and the side surface of the electrode growth step are also covered, so that the isolation between the third electrode and the voltage-resistant drift layer can be further realized.
S404: the first source-drain contact layer of the first region is removed.
In the implementation, the first source-drain contact layer of the first region can be removed by etching through photolithography or electron beam exposure.
S405: and etching the withstand voltage drift layer, the inversion layer and part of the second source-drain contact layer in the gate position area in the second area to form a gate groove.
Fig. 8 is a schematic diagram of the structure of the device obtained by this step.
S406: and respectively growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer in the gate position area in the first area and the gate groove.
In the implementation, the materials of the first gate dielectric layer and the second gate dielectric layer may be one or more materials such as SiN、SiO2、Al2O3、HfO2、ZrO2、La2O3、HfAlOX、HfSiOX、HfLaOX、HfZrOX、HfSiON.
In particular, the same insulating layer may be provided in order to reduce the manufacturing cost. Specifically, an insulating layer (as shown in fig. 9) may be grown on the first surface of the prepared device by adopting a chemical vapor deposition process or the like, and then the insulating layers of the first electrode position region, the second electrode position region, the third electrode position region and the fourth electrode position region are removed by etching, so that a portion of the insulating layer located in the gate position region in the first region is a first gate dielectric layer, a portion located in the gate groove is a second gate dielectric layer, and at this time, on the basis of completing the first gate dielectric layer and the second gate dielectric layer simultaneously, other insulating layer portions also realize surface passivation of the device.
S407: the first electrode, the second electrode, the first gate electrode, the third electrode, the fourth electrode, and the second gate electrode are grown.
As shown in fig. 10, the first gate is grown on the first gate dielectric layer, and the first electrode and the second electrode are both grown on the second conductive structure layer of the first region and are respectively located at two sides of the first gate; the third electrode grows on the electrode growth step, the second grid electrode grows on the second grid dielectric layer, the fourth electrode grows on the second source-drain contact layer, and the fourth electrode and the third electrode are respectively positioned on two sides of the second grid electrode.
In particular, the first electrode, the second electrode, the third electrode and the fourth electrode may be made of the same metal material, and thus may be grown simultaneously. For example, the regions corresponding to the four electrodes may be defined by photolithography, then a metal stack of titanium/aluminum/nickel/gold is continuously deposited by using processes such as electron beam evaporation, and then the metal outside the regions corresponding to the four electrodes is stripped and annealed to form an alloy ohmic contact, thereby completing the growth of the four electrodes.
In particular, the first gate and the second gate may be made of the same metal material, and thus may be grown simultaneously. For example, the regions corresponding to the two gates may be defined by photolithography, then a metal layer of nickel/gold is grown by using a process such as physical vapor deposition, and then the excess metal is stripped to complete the growth of the first gate and the second gate.
S408: the second electrode is electrically connected to the third electrode, and the first gate electrode is electrically connected to the fourth electrode.
In this embodiment, as shown in fig. 1-3, the second gate is a gate terminal of the cascode casecode device, the first electrode is one current terminal of the cascode casecode device, and the first gate and the fourth electrode after being electrically connected are cascaded casecode with another current terminal of the device.
In practice, the electrical connection between the second electrode and the third electrode and between the first gate electrode and the fourth electrode may be accomplished by growing a metal layer. For example, photoresist may be spin-coated on the first surface of the fabricated device, then a cascade region of the second electrode and the third electrode, and a cascade region of the first gate and the fourth electrode may be defined by electron beam exposure, and then a metal layer of nickel/gold may be grown by using a physical vapor deposition process to form a contact, so as to realize electrical connection between the second electrode and the third electrode, and electrical connection between the first gate and the fourth electrode.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While obvious variations or modifications are contemplated as falling within the scope of the present invention.
Claims (8)
1. A cascode casecode device, comprising:
The device comprises a substrate, and a first conductive structure layer and a second conductive structure layer which are arranged on the substrate, wherein a heterojunction is formed between the first conductive structure layer and the second conductive structure layer; the first conductive structure layer and the second conductive structure layer are provided with a first area and a second area which are spaced;
the first electrode, the second electrode and the first grid electrode are arranged on the second conductive structure layer of the first region, the first grid electrode is positioned between the first electrode and the second electrode, and a first grid dielectric layer is arranged between the first grid electrode and the second conductive structure layer;
The first source-drain contact layer, the voltage-withstanding drift layer, the inversion layer and the second source-drain contact layer are sequentially arranged on the second conductive structure layer of the second region; an electrode growth step is arranged in a third electrode growth area in the second area and penetrates through all of the second source-drain contact layer, the inversion layer and the withstand voltage drift layer; a gate groove is formed in the gate position area in the second area, and penetrates through the second source-drain contact layer and the inversion layer;
a third electrode arranged on the electrode growth step and spaced from the voltage-resistant drift layer;
the second grid electrode is arranged in the grid electrode groove, and a second grid dielectric layer is arranged between the second grid electrode and the wall surface of the grid electrode groove;
the fourth electrode is arranged on the second source-drain contact layer and is respectively positioned at two sides of the second gate electrode with the third electrode;
the second electrode is electrically connected with the third electrode; the second gate is a gate terminal of the cascode casecode device, the first electrode is one current terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode and then serves as the other current terminal of the cascode casecode device.
2. The device of claim 1, wherein the first source-drain contact layer, the voltage-resistant drift layer, and the second source-drain contact layer are all N-doped layers, and wherein the first electrode is a drain terminal of the device of the cascade casecode when the inversion layer is a P-doped layer, and wherein the first gate is electrically connected to the fourth electrode to serve as a source terminal of the device of the cascade casecode.
3. The cascode casecode device according to claim 1, wherein the first source-drain contact layer, the voltage-resistant drift layer, and the second source-drain contact layer are P-doped layers, and wherein when the inversion layer is an N-doped layer, the first electrode is a source terminal of the cascode casecode device, and the first gate is electrically connected to the fourth electrode to serve as a drain terminal of the cascode casecode device.
4. The cascode casecode device according to any one of claims 1-3, wherein said first gate dielectric layer and said second gate dielectric layer are the same insulating layer, said insulating layer also encapsulating a first surface of said cascode casecode device other than said first electrode, said second electrode, said third electrode and said fourth electrode.
5. A method of fabricating a cascade casecode device comprising the steps of:
Sequentially growing a first conductive structure layer, a second conductive structure layer, a first source-drain contact layer, a voltage-withstanding drift layer, an inversion layer and a second source-drain contact layer on a substrate to form a device substrate;
Forming an isolation region in the middle of the device substrate to separate the first conductive structure layer and the second conductive structure layer into a first region and a second region;
Removing the second source-drain contact layer, the inversion layer and the withstand voltage drift layer in the third electrode growth region in the second region and all of the first region; at the moment, an electrode growth step exposing the first source-drain contact layer is formed at a third electrode growth area in the second area;
Removing the first source-drain contact layer of the first region;
Etching the voltage-resistant drift layer, the inversion layer and part of the second source-drain contact layer in the gate position area in the second area to form a gate groove;
A first gate dielectric layer and a second gate dielectric layer are respectively grown on the second conductive structure layer in the gate position area in the first area and in the gate groove;
Growing a first electrode, a second electrode, a first grid electrode, a third electrode, a fourth electrode and a second grid electrode; the first grid electrode is grown on the first grid dielectric layer, and the first electrode and the second electrode are both grown on the second conductive structure layer of the first region and are respectively positioned at two sides of the first grid electrode; the third electrode grows on the electrode growth step, the second grid electrode grows on the second grid dielectric layer, the fourth electrode grows on the second source-drain contact layer and is respectively positioned on two sides of the second grid electrode with the third electrode;
Electrically connecting the second electrode with the third electrode, and electrically connecting the first gate with the fourth electrode; the second gate is a gate end of the cascade casecode device, the first electrode is one current end of the cascade casecode device, and the first gate and the fourth electrode after being electrically connected are the other current end of the cascade casecode device.
6. The method for fabricating a cascode casecode device according to claim 5, wherein the step of growing a first gate dielectric layer and a second gate dielectric layer on the second conductive structure layer and in the gate trench, respectively, in the gate position region in the first region specifically includes:
Growing an insulating layer on a first surface of the device;
etching to remove the insulating layers of the first electrode position area, the second electrode position area, the third electrode position area and the fourth electrode position area; at this time, the insulating layer in the gate position area in the first area is the first gate dielectric layer, and the insulating layer in the gate groove is the second gate dielectric layer.
7. The method of claim 5, wherein the first source-drain contact layer, the voltage-resistant drift layer, and the second source-drain contact layer are all N-doped layers, and the first electrode is a drain terminal of the cascade casecode device when the inversion layer is a P-doped layer, and the first gate is electrically connected to the fourth electrode to serve as a source terminal of the cascade casecode device.
8. The method of claim 5, wherein the first source-drain contact layer, the voltage-resistant drift layer, and the second source-drain contact layer are P-doped layers, and the first electrode is a source terminal of the cascade casecode device when the inversion layer is an N-doped layer, and the first gate is electrically connected to the fourth electrode to serve as a drain terminal of the cascade casecode device.
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