JPS59123330A - Error detecting system - Google Patents
Error detecting systemInfo
- Publication number
- JPS59123330A JPS59123330A JP23164682A JP23164682A JPS59123330A JP S59123330 A JPS59123330 A JP S59123330A JP 23164682 A JP23164682 A JP 23164682A JP 23164682 A JP23164682 A JP 23164682A JP S59123330 A JPS59123330 A JP S59123330A
- Authority
- JP
- Japan
- Prior art keywords
- data
- frequency
- output
- exclusive
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明はｎＢ１Ｐ（偶パリティ）符号において、フレー
ム同期をとらずにＰ（パリティ）パルスのエラーを検出
する方式に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for detecting errors in P (parity) pulses without frame synchronization in nB1P (even parity) codes.
（２）従来技術と問題点
従来、ｎＢ１Ｐ、即ち最大ｎ個のデータを有する１フレ
ーム毎にＰ（パリティ）パルスによりエラーを検出する
方式では、フレーム同期をとることによりＰパルスのエ
ラーを検出していた。(2) Conventional technology and problems Conventionally, in nB1P, that is, a method that detects errors using P (parity) pulses for each frame containing a maximum of n pieces of data, errors in P pulses are detected by synchronizing frames. was.
しかし、フレーム同期をとるために回路が複雑となりか
つ大規模になるという問題点があった。However, there is a problem in that the circuit becomes complicated and large-scale in order to achieve frame synchronization.
（３）発明の目的
本発明の目的は、データの直流分の変化をとり出すこと
によりエラーを検出し、エラー検出回路を簡単にするこ
とにある。(3) Purpose of the Invention An object of the present invention is to detect errors by extracting changes in the DC component of data, thereby simplifying the error detection circuit.
（４）発明の構成
本発明によれば、偶パリティのｎＢ１Ｐ形式のデータエ
ラーを検出する方式において、データを分周器により分
周し、該分周されたデータを低域フィルタ並びに比較器
を介して直流分の変化を取り出し、更に該変化分を排他
的オアダートへ、遅延回路を介して入力させると共に直
接に入力させ、該排他的オアゲートの出力からｎＢ１Ｐ
形式のデータエラーを検出することを特徴とするエラー
検出方式が提供される。(4) Structure of the Invention According to the present invention, in a method for detecting data errors in even parity nB1P format, data is frequency-divided by a frequency divider, and the frequency-divided data is passed through a low-pass filter and a comparator. The change in DC component is extracted through the exclusive OR gate, and the change is input to the exclusive OR gate via a delay circuit as well as directly, and nB1P is input from the output of the exclusive OR gate.
An error detection scheme is provided that features detecting data errors of the form.
（５）発明の実施例 以下、本発明を実施例によシ添伺図面を参照し。(5) Examples of the invention DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
で活１明する。I'm going to live a long time.
第１し［は本発明に係るエラー検出方式の構成図である
。本発明方式に採用したデータ（１：送形式にＬｎＢＩ
Ｐ形式、例え＋ｄ：ブータの最大ｎ２１０個こと（２＋
’Ｓ ２しｊの１，２・・・ｌＯ）にパリティパルス（
第２図のＰ）を検出し、（偶・々ルデ＋）、データのエ
ラーを発見するようになっている。The first diagram is a configuration diagram of an error detection method according to the present invention. Data adopted in the method of the present invention (1: LnBI is used as the transmission format)
P format, e.g. +d: Maximum n210 booters (2+
'S 2j's 1, 2...lO) and the parity pulse (
It detects P) in Fig. 2 and discovers data errors (even/evenly).
先ず入力端子ＩＮからデータ（肴）２し」（１））が入
力すると、分周器１（フリップフロップにより構成され
ている）によ’） １．／２／Ｉ″Ｊ周する（第２図（
２）、）。First, when data (appetizer) 2 (1)) is input from the input terminal IN, it is input to the frequency divider 1 (consisting of flip-flops).1. /2/I″J goes around (Fig. 2 (
2),).
偶パリティであるから、エラーＥが発生しておシ、時間
軸をｎ）ｉめると第２図（３）の波形となる。Since the parity is even, an error E occurs, and when the time axis is incremented by n), the waveform shown in FIG. 2 (3) is obtained.
ｎＢＩＰ （偶パリティ）形式においては ｔｔ ｌＩ
＋のデータが必らず偶数個あることになシ、一旦エラー
が発生ずると、Ｐパルスの時間位置でのフリップフロッ
プ１の出力ｄ、反転状態を維持する。In nBIP (even parity) format, tt lI
Although there is not necessarily an even number of + data, once an error occurs, the output d of the flip-flop 1 at the time position of the P pulse maintains an inverted state.
この出力を低域フィルタ２に通しく第２図（４））、直
流分を取造出し、更に比較器３によシ直流分の変化を検
出する（第２図（５））。This output is passed through a low-pass filter 2 (FIG. 2 (4)), a DC component is produced, and a change in the DC component is detected by a comparator 3 (FIG. 2 (5)).
比較器３の出力を遅延回路４を介し、かつ直接に排他的
メアクー゛−ト５に入力させれば、出カψ１ｉｌｉ子Ｏ
ＵＴ ７５” ラ工５ Ｆを表わす信号がイ０られる
（第２図（Ｅ）） ）。If the output of the comparator 3 is input directly to the exclusive circuit 5 via the delay circuit 4, the output ψ1ili
A signal representing UT 75'' RA 5F is set to 0 (FIG. 2(E))).
（６）発明の効果
本発明によれは、データの直流分の変化をとシ出すこと
によりエラーの有無が検出できるので、エラー検出回路
が簡単になる。(6) Effects of the Invention According to the present invention, the presence or absence of an error can be detected by detecting changes in the DC component of data, thereby simplifying the error detection circuit.
第１図は本発明方式の構成図、第２図は第１図の各部の
波形図である。
１・・・フリップフロップ、２・・・低域フィルタ、３
・・比較器、４・・・遅延回路、５・・・排他的オアゲ
ート。
！１）π１出庇（人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士西舘和之
弁理士 内 １）幸 男
弁理士 山 １」 昭 之FIG. 1 is a block diagram of the system of the present invention, and FIG. 2 is a waveform diagram of each part of FIG. 1. 1...Flip-flop, 2...Low pass filter, 3
...Comparator, 4...Delay circuit, 5...Exclusive OR gate. ! 1) π1 Extrusion (Patent Attorney Akira Aoki, Patent Attorney Kazuyuki Nishidate, Patent Attorney Fujitsu Ltd. 1) Yukio Patent Attorney Yama 1” Akiyuki Aki
Claims (1)
式において、データを分周器により分周し、該分周され
たデータを低域フィルタ並びに比較器を介して直流分の
変化を取シ出し、更に該変化分を排他的オアゲートヘ、
遅延回路を介して入力させると共に直接に入力させ、該
排他的オアゲートの出力から、ｎＢ１Ｐ形式のデータエ
ラーを検出することを特徴とするエラー検出方式。In the method of detecting data errors in the even parity nB1P format, data is frequency-divided by a frequency divider, the frequency-divided data is passed through a low-pass filter and a comparator, and a change in the DC component is extracted. The change amount to exclusive or gate,
An error detection method characterized by detecting an nB1P format data error from the output of the exclusive OR gate by inputting it through a delay circuit as well as directly inputting it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23164682A JPS59123330A (en) | 1982-12-29 | 1982-12-29 | Error detecting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23164682A JPS59123330A (en) | 1982-12-29 | 1982-12-29 | Error detecting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59123330A true JPS59123330A (en) | 1984-07-17 |
Family
ID=16926755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23164682A Pending JPS59123330A (en) | 1982-12-29 | 1982-12-29 | Error detecting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59123330A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147430A (en) * | 1998-05-25 | 2000-11-14 | Denso Corporation | Stator of AC generator for vehicle |
-
1982
- 1982-12-29 JP JP23164682A patent/JPS59123330A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147430A (en) * | 1998-05-25 | 2000-11-14 | Denso Corporation | Stator of AC generator for vehicle |
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