JPS59123247A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the conveyance system for tests and markings without needing the supply in alignment according to the parts feeder as well as to prevent the deterioration of the plating parts on external leads by a method wherein a long frame is used. CONSTITUTION:Tie bar parts 6 are separated by cutting in the tie bar cutting process after the processes of foil-coating and die-bonding, wire-bonding, molding and solder dipping. A long frame is severed in the standard length, two out of three external leads are separated by cutting from a frame 7, and each of the severed frames is set as a semiconductor device series. Regarding the length to cut the long frame in the specified length, the degree that fifty pieces of semiconductor elements are included each strip is the optimum. In the test-marking process, elements are supplied to the tester in the unit of the semiconductor device strips and the positioning for the measuring is carried out using guide holes 81. The positions on the water are kept in the unit of the semiconductor device strip and each element can be dealt with relating with other elements, resulting in enabling to prevent the deteriorating of plating on the armored leads without using the parts feeder.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and in particular provides a rational method of manufacturing a semiconductor device that has been assembled.

[Prior art]

Taking a transistor as an example, the conventional manufacturing method of a semiconductor device uses a so-called frame (1) as shown in Fig. 1, and heat-seals a semiconductor element (not shown) to this pad portion (2). Then, the semiconductor element and the finger portion (3) of the frame (1) are connected by a known thermocompression bonding method using a thin gold wire (not shown).
Obtain an electrical connection.

Thereafter, in order to protect the semiconductor element and the thin gold wire inside, they are surrounded and molded using epoxy resin or the like. The molding is carried out in the area shown by the dashed line in FIG. 1, and this becomes the epoxy resin (5) shown in FIG. 2.

After that, the tie bar part (6) (shown as a shaded area in Figure 2) and the slightly upper part of the frame (7) are removed.
Cut and separate from the area indicated by line B, and connect the external lead wire (4)
The exterior is plated with a solder material or the like to obtain a transistor as shown in FIG. The steps up to this point are the so-called conventional method for assembling a transistor.

Thereafter, the cut and separated transistors are arranged using a so-called parts feeder, and an automatic sorter is used to sort them according to their good or bad characteristics, as well as their direct current amplification factor (hpE), and if necessary, their breakdown voltage. Generally, about 5 to 10 classifications are made depending on other electrical characteristics. After the classification, a parts feeder is used to stamp the model name and hFE for each classification.
Displays the classification contents such as, and the manufacturing loft number. Furthermore, if necessary, in order to facilitate device assembly on the printed circuit board, external lead wires (4) are formed, packaged, and shipped.

Such conventional transistor manufacturing methods have the following irrationality or drawbacks.

(1) It is necessary to align the parts using a parts feeder each time after assembly, such as sorting, stamping, and forming external lead wires.

(2) Alignment using a parts feeder applies stress to the transistors due to mutual vibration, which adversely affects the plating of the external lead wires.

(3) Alignment of transistors by parts feeder,
Supply (this requires experience in manufacturing and adjusting the supply system, and is essentially difficult to automate or unmanned.

(4) Conventional frames have a short-nh shape and generally have a length equivalent to about 250 tiger 7 jiffs, and require functions for supplying and discharging frames during assembly.

Furthermore, a considerable portion of the assembly machine's stoppage is controlled by this mechanism.

[Summary of the invention]

In order to eliminate the drawbacks enumerated here, the present invention uses a long frame that is almost infinitely far away from the conventional frame length, and is equivalent to 100,000 to 1 million transistors. The present invention aims to provide a novel method for manufacturing a semiconductor device.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and the manufacturing steps will be sequentially explained below using the same diagram.

For foil material/guipondani process (10), long frames,
A so-called hoop-shaped frame is supplied to the foil/die bonder section, and the semiconductor element is placed on the pad section (2) of the frame. In the wire bonding step (11), the finger portions (3) of the frame and the semiconductor element are connected using a wire bonder. Furthermore, in a molding step f121, sealing is performed with an epoxy resin (5) in the same manner as shown in FIG. 2. In the deburring step 03), so-called deburring is performed using a deburring machine to remove deburrs generated by the mold. In the solder dip process (14), exterior plating is applied to the external lead (4) using a solder dip device, and then in the tie bar cut process (15), the tie bar part t6) shown in FIG. 2 is cut.
>N' cleavage separation. The steps up to this point are the Sl process in which long pieces are processed consistently, and the next step is Section 2.

In the second step, the frame cutting step (]6), this long frame is cut into regular lengths. The length of this standard cut is
Generally, it is optimal to include 50 semiconductor elements.

At the same time as or after this cutting to a specified length, in the third step of cutting and forming external leads (I7), as shown by hatching in FIG.
Up to two of the wooden external lead wires (4) are cut and separated from the frame (7) to obtain the semiconductor device series shown in FIG. In this embodiment, the length is equivalent to 50 semiconductor devices.

The subsequent processing will be carried out directly in units of 50 semiconductor devices. Then, in the fourth step, the test mark step 081, the hemiplane % W series is supplied to the tester, and the position for measurement is determined by the guide hole (81).
It is extremely easy to configure the line using lines, and this embodiment is also configured in the same way. In addition, in general, it is possible to obtain well-equalized characteristics of semiconductor elements that are present in the vicinity of the wafer. The same is true for the DC current amplification rate, which is a characteristic for classifying transistors, and one semiconductor device is composed of a single DC current amplification rate. Become. As described above, in the method of this embodiment, it is possible to save the position on the wafer in units of semiconductor devices and process them in association with each other, and the efficiency in transportation is greatly improved. This also prevents deterioration of the exterior lead plating. Furthermore, in this embodiment, whether the tester determines that the
If the DC current amplification rate is out of line with the item, cut the other external lead (the one connected to the frame (7)) and classify these as belonging to a separate building. I can do it.

The semiconductor devices that have been tested are moved to the marking section, where the model name, symbol representing the DC current amplification rate, and symbol representing the manufacturing loft period are stamped, and then packaged and shipped in the packaging step 09). At the time of stamping, since the DC current increase rate of 9 current is fixed in accordance with the semiconductor device operation, the stamping mechanism can be simplified.

In addition, whether the above embodiment discloses a transistor or not,
It is clear that similar actions and effects can be obtained with semiconductor integrated circuits.

〔Effect of the invention〕

As described above, according to the present invention, testing and marking are simplified, and there is no need to align and supply semiconductor devices using a parts tweeter, which was conventionally used for testing and marking. Prevents deterioration of the lead wire plating part

[Brief explanation of drawings]

This is an enlarged view of the main parts of the semiconductor device welcome. 00) ~ (15)...Foil material/diaponder mite processing, wire ponder mite processing, molding process, deburring process, solder dip process, tie bar cutting process (first process), 06)
... Frame cutting process (second process), 0η... External lead cutting and forming process (third process), (I8)... Test mark process (fourth process), (4)...・External lead wire. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 2 11, 4

Claims (2)

[Claims] (1) A first step in which a plurality of semiconductor devices are continuously arranged on the same plane using a long frame, and the long frame is cut into a fixed length for each predetermined number of semiconductor devices. a second step of separating the standard length semiconductor packaging speed; a third step of collectively cutting and shaping the external lead portions of the standard length semiconductor packaging speed; A method for manufacturing a semiconductor device, comprising a fourth step of inspecting and stamping the semiconductor device in units. (2) The semiconductor device according to claim 1, characterized in that the batch cutting of the external lead portions in the β-th step is performed for each semiconductor device for one less than the number of external lead wires. Production method.