JPS59122185A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent the generation of fixed pattern noise by providing a shift register storing defective picture element position of a horizontal line to each defective line and generating a defect display signal to make noise in an output signal of each picture element constant. CONSTITUTION:Shift registers 25, 26, 27 having a horizontal sweep width and storing a defective picture element position on a horizontal line are provided at each horizontal line having a defective picture element, switches 22, 23, 24 are driven by a binary signal representing a defective line number outputted from a counter 6 and select a shift register corresponding to the defective line. A data set by a clock signal inputted to the CP of a shift register is transferred and an output signal representing a picture element defective position is outputted from a terminal 0. Since the noise corresponding to the level change of the clcok signal is applied uniformly to each picture element, the fixed pattern noise to be a longitudinal stripe on the picture is not generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device, and more particularly to a circuit for compensating for a defect in a solid-state imaging device.

In recent years, solid-state imaging devices equipped with solid-state imaging devices such as CCD and MOS have been increasingly used in place of image pickup tubes. pixel defects may occur in some pixels.Elements with a large number of pixel defects will be defective, but
Even if there are defects, elements with a small number of defects can often be used in imaging devices depending on the purpose.

Some imaging devices using solid-state imaging devices with such pixel defects compensate for one pixel defect. As a method for this compensation, the position of the defective pixel is checked in advance, and a signal indicating the existence of a pixel defect (hereinafter referred to as a defect indication signal) is generated in the phase in which the signal of the defective pixel is output. When this signal is generated, signals from one or more pixels near the defective pixel are often combined to create a signal for the defective pixel.

FIG. 1 shows an example of a conventional circuit configuration for generating such a defect indication signal. In the figure, the counter 4 is reset by the vertical synchronization signal input to the clear terminal CL through the terminal 2 at the beginning of the frame, and the horizontal synchronization signal input to the clock terminal CP through the terminal 1 is counted. The number is count output terminal Q
It is output as a binary signal to O to Q8. The presence or absence of a pixel defect in each horizontal line is written as data in the memory 5 using the horizontal line number as an address, and the scan data is input from the count output terminals QO to Q8 of the counter 4 to the address input terminals AO to B. A signal indicating that each horizontal line has a defective pixel (hereinafter referred to as a defective line display signal) is output from the data output terminal in accordance with a signal indicating the line number in the horizontal line.

The counter 6 is reset by the vertical synchronizing signal input to the terminal CL at the beginning of the frame, and
The defective line display signal input to P is counted,
A binary signal indicating the number of horizontal lines with pixel defects that existed from the beginning of the frame to the point in time during scanning is output to count output terminals QO-Q2. The memory 7 stores in advance the horizontal position of each pixel defect as data in binary code, using the number of the horizontal line with the pixel defect (hereinafter referred to as defective line number) assigned in the order of scanning from the beginning of the frame as an address. The address input terminal A is written from the counter 6.

Depending on the signal input to ~A2, a binary signal indicating the horizontal position of each pixel defect is sent to the data output terminals DO~D.
8 is output.

The counter 9 is reset by a horizontal synchronizing signal inputted to the terminal CL, counts a clock signal inputted to the terminal CP through the terminal 3 and whose period is the signal output period of one pixel, and reads out the pixel signal by scanning. A binary signal indicating the horizontal position of the pixel being scanned (hereinafter referred to as the pixel being scanned) is output to the count output terminals Q o -Q s. The gate 8 receives a binary signal indicating the horizontal position of the pixel defect input from the memory 7 and a counter 9.
The gate is gated with a binary signal indicating the horizontal position of the pixel being scanned which is input from the gate 11, and further gated by the defective line display signal output from the memory 5 at the gate 11, so that the defect display signal is sent to the terminal. 12 is output. The circuit shown in this figure can compensate for up to seven pixel defects, but by increasing the number of bits of the counter 6 and the capacity of the memory 7, it is possible to compensate for a larger number of pixel defects.

The first method for generating such a defect indication signal is
Although there are configurations other than those shown, all of them are equipped with a counter that generates a binary signal indicating the horizontal position of the pixel being scanned, and this counter is constantly operated. However, if these binary signals are generated during the video signal output period, frequency division noise is added to the video signal when the level of the binary signal changes, and the quality of the resulting image deteriorates due to the noise. Ta.

FIGS. 2(a) to 2(f) are time charts showing noise components added to the binary signal and video signal in FIG. 1. In the figure, a clock signal (FIG. 2(a)) whose cycle is the signal output period of one pixel is a binary signal QO
~Q8 is input to the counter 9 which generates the signal QO~Q8 (Fig. 2(b)~
(e)), and when the levels of these clock signals and frequency-divided signals change, noise components (see Figure 2) are added to the video signal.

The magnitude of this noise component changes depending on the number of signals whose levels change among the clock signal and branch signals, and since each horizontal line has the same waveform, fixed pattern noise with vertical stripes occurs in the resulting image, resulting in poor image quality. The disadvantage was that it decreased.

An object of the present invention is to generate a defect display signal using a shift register that transfers data using a clock signal so as to compensate for a pixel defect in a signal output from a pixel having a single pixel defect. It is an object of the present invention to provide a solid-state imaging device equipped with a pixel defect compensation circuit that makes noise added to the image uniform, prevents the occurrence of fixed pattern noise resulting in vertical stripes, and obtains an image without deterioration in image quality.

The solid-state imaging device of the present invention includes a solid-state imaging device in which a plurality of pixels are arranged on each of a plurality of horizontal lines arranged on a plane, and a defect in each pixel of the solid-state imaging device. A memory for storing a position signal indicating the position of a defective horizontal line in which a pixel is included; and for each defective horizontal line read from this memory, the presence or absence of a pixel defect is set for all pixels in that horizontal line, and A plurality of shift registers in which transfer is performed in accordance with a predetermined clock signal during a period in which a horizontal line is scanned, a selection circuit that selects one of these shift registers to perform transfer and signal output, and an output from this selection circuit. and a compensation circuit that compensates the imaging signal for the defective position of the signal.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 3 is a configuration diagram of the defect display signal generation circuit in the pixel defect compensation circuit of an embodiment of the solid-state imaging device according to the present invention. In the figure, terminals 1-3 and 12. Counters 4 and 6. The memory 5 performs the same operation as the circuit shown in FIG. 1, and the memory 7, gates 8, 11 . Switch circuits 22 to 24 instead of counter 9. shift register 2
A 5-27° gate 21 and a differentiating circuit 20 are used. At the gate 21, a gate is applied to the clock signal inputted from the terminal 3 by the defective line display signal applied from the memory 5, and the clock signal is outputted only during the period when a horizontal line having a pixel defect is scanned.

The defective line display signal is differentiated in the differentiating circuit 20,
A signal is output during a horizontal blanking period that precedes the period during which the horizontal line with the defective pixel is scanned. switch 2
2 to 24 are electronic switch circuits that are driven in response to a binary signal indicating the defective line number outputted from the counter 6; A signal is selected to be input to a predetermined shift register among the shift registers 25 to 27, and the switch 24 selects the output signal output from the output terminal 0 of the corresponding shift register and supplies it to the output terminal 12.

The shift registers 25 to 27 each have a horizontal sweep width, and are, for example, 512-stage shift registers, and when a signal is input to each setting terminal, all bits are initialized to indicate the position of a pixel defect on that horizontal line. It is used to set data as a value, and is constituted by, for example, a shift register with a ROM. Clock input terminal CP of this shift register
The data set by the clock signal input to is transferred and outputted from the output terminal O as an output signal indicating the pixel defect location. This output data can record the presence or absence of a pixel defect in each shift register for all pixels in the horizontal line with a pixel defect, and the pixel defect of the pixel whose signal is being read out by scanning using the signal output from the output terminal O. The presence or absence of is indicated.

In this embodiment, the only signal whose level changes during the video signal output period is the clock signal input from the terminal 3. Therefore, the noise generated in the defect compensation circuit and added to the video signal is only the noise corresponding to the level change of the clock signal, and the noise corresponding to the level change of the clock signal is uniformly added to each pixel of the horizontal line. Therefore, the resulting image does not have fixed pattern noise such as vertical stripes, and there is no deterioration in image quality.

Furthermore, in the circuit shown in FIG. 1, since the horizontal position of the pixel defect is written in the memory 7 in binary code,
The number of pixel defects that can be compensated for is only one per horizontal line. However, in this embodiment, since the presence or absence of a pixel defect can be set in the shift register for all pixels in a horizontal line having a pixel defect, it is possible to compensate even if there are a plurality of pixel defects in a -horizontal line.

Although this embodiment shows a case where defect compensation for three horizontal lines is performed using three shift registers, it is clear that increasing the number of shift registers increases the number of horizontal lines that can be compensated for defects.

As described above, the solid-state imaging device of the present invention uses a clock signal whose cycle is the signal output period of one pixel in a circuit that compensates for pixel defects when some pixels of the solid-state imaging device are defective. By generating a defect display signal using a shift register that performs transfer, the noise added to the output signal of each pixel of the solid-state image sensor is made uniform.
It is possible to prevent the generation of fixed pattern noise, which is vertical stripes, and to obtain an image without deterioration in image quality.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a defect display signal generation circuit of a pixel defect compensation circuit of a conventional solid-state imaging device, Fig. 2 (a) to (f) are time charts showing the branching operation of Fig. 1, and Fig. 3 is the main FIG. 2 is a block diagram of an embodiment of the invention. In the figure, 1, 2.3.12... input/output terminals, 4, 6...
- counter, 5... memo IJ, 20... song differentiation circuit, 21... song gate, 22-24... song switch, 25-27... song shift register.

Claims (1)

[Claims] A solid-state image sensor in which a plurality of pixels are arranged on each of a plurality of horizontal lines arranged on a plane, and a position of a defective horizontal line containing a defective pixel among each pixel of this solid-state image sensor. A memory for storing a position signal, and for each defective horizontal line read from the memory, the presence or absence of a pixel defect is set for all pixels of the horizontal line, and a predetermined clock signal is set during the scanning period of the defective horizontal line. A selection circuit that selects one of these shift registers for transfer and signal output, and compensation of the imaging signal for the defective position of the output signal from this selection circuit. A solid-state imaging device including a compensation circuit that performs.