JPS59122019A - Level detecting circuit - Google Patents

Abstract

PURPOSE:To speed up level detection by performing the level detection without using a smoothing circuit which may causes detection time to become longer. CONSTITUTION:The output of a voltage comparator 2 is connected to the reset terminal R of a counting circuit 5, so when the output of the voltage comparator 2 goes up to a level ''H'' before the counter counts up to seven, the output 7 of an NAND gate is held at the level ''H''. Then, a signal to be detected is inputted to an input terminal 1 of the voltage comparator 2 and a reference voltage V from a reference voltage source 3 is set to the crest value V of a detection level point; a reset pulse is inputted at every period of the signal to be detected when the crest value is higher than the reference voltage V and the reset pulse is not inputted when not. Therefore, when the level of the signal to be detected varies from the high state wherein the reset pulse is outputted from the voltage comparator 2 to the low state, and when it varies reversely, the state changes are discriminated within a time of a period less than twice the period of the input signal respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a level detection circuit ζζ that detects the level of a sinusoidal signal to be detected, and particularly to a level detection circuit ζζ that detects the level of a signal to be detected in the form of a sine wave. The present invention relates to a level detection circuit.

(bl Prior Art and Problems The conventional level detection circuit has a sine wave-like detected f
After leveling g@, it is smoothed, and each smoothed signal is compared with a predetermined level to detect the level of the detected signal. That is, when the smoothed signal drops below the predetermined level, it is detected that the level of the detected signal has dropped.

However, such conventional level detection circuits have the following drawbacks. In other words, the conventional level detection circuit has a smoothing circuit for obtaining a DC voltage fluctuation equivalent to the level of the detected signal after fully rectifying the signal to be detected, but such a smoothing circuit has a time constant Therefore, high-speed level detection could not be performed.

Note that in order to speed up level detection, the time constant of the smoothing circuit may be made small, but if the time constant is made small, ripples increase and level detection becomes impossible.

(C1 Purpose of the Invention The present invention has been made in view of the drawbacks of the conventional level detection circuit,
High-speed level detection 1. The purpose of this invention is to provide a level detection circuit that can increase the

(d) Structure of the Invention In order to achieve the objective 8, a level detection circuit for detecting the level of a sinusoidal signal to be detected includes:
A counting means that inputs a clock of a predetermined period and counts up to a predetermined number, and outputs the counted values sequentially, compares the level of the detected signal with a predetermined level, and compares the level of the detected signal with a predetermined level. When the predetermined level is exceeded, the count (i
Comparing means for outputting a reset signal for resetting t, and configured to detect that the level of the detected signal has decreased when the count value of the counting means reaches the predetermined number. That is.

tal Embodiment of the Invention Hereinafter, an embodiment of the level detection circuit of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of one embodiment of the inventive level detection circuit. In the diagram ζ, 1 is the $1lIj multiplier input terminal (
2 is a voltage comparator.

3 is a reference voltage source, 4 is a clock input terminal, 5 is a counting circuit, 6 is a Nandt gate, and 7 is an output terminal.

FIG. 2 is an explanatory diagram of the operation of FIG. When the clock pulses shown in Fig. 2 (cl) are counted 7, the outputs of the Q2 and Q3 terminals are all at the "H" level. Therefore, the output of the Nantes gate 7 is at the "L" level. Since the output of the Nant gate 7 is connected to the enable terminal E of the counting circuit 5, the count state of 7 is maintained even if 8 or more clock pulses are applied.

- Since the output of the voltage comparator 2 is connected to the reset terminal R of the counting circuit 5, if the output of the voltage comparator 2 reaches the "H" level before 7 counts, the Nant gate output cuff always maintains the ``H'' level. here,
The detected signal is input to the input terminal lζ of the voltage comparator 2, and the reference voltage from the reference voltage source 3 is set to the peak value V at the detection level point.
When the peak value of the input signal is higher than the reference voltage V, a reset pulse is input to the reset terminal R of the counting circuit 5 every cycle of the detected signal, and the peak value is higher than the reference voltage V. If it is low, no reset pulse is input. Therefore, when the level of the detected signal changes from a high state where a reset pulse is output from the voltage comparator 2 to a low state, the level of the detected signal changes within twice the input signal period. In the case of a transition from a low state to a high state, the change in state can be determined within a period of the input signal.

The series of operations described above is shown in FIG.

FIG. 3 is a block diagram of another embodiment of the level detection circuit of the present invention. In the figure, parts with the same numbers as in FIG. 1 indicate the same circuits, and 8 is a full-wave rectifier circuit. Another embodiment of the present invention shown in FIG.
The point is that a full-wave rectified waveform that has been full-wave rectified is applied. According to this embodiment, the detection time is 17 in the embodiment of FIG.
It can be shortened to 2.

lfJ Effects of the Invention As explained in detail above, the level detection circuit of the present invention (
Accordingly, the level detection time can be extended and the level detection can be performed without using the smoothing circuit which is the cause of "g", so that the level detection can be performed at high speed.

[Brief explanation of drawings]

Fig. 1 is an illustration of an example of the uninvented θ) level detection circuit, Fig. 2 is an explanatory diagram of the operation of Fig. 1, and Fig. 3 is an example of the level detection circuit of the present invention. In the figure, l is an input terminal, 2 is a voltage comparator, 3 is a reference voltage source, 4 is a clock input terminal, 5 is a binary number circuit, 6 is a sand gate, 7 is an output terminal, and 8 is a It is a full wave rectifier circuit.

Claims (1)

[Claims] A level detection circuit that detects the level of a sinusoidal signal to be detected has a function of inputting a clock of a predetermined period and counting up to a predetermined number, and an argument means for sequentially outputting the counted value; the level is compared with a predetermined level, and when the level of the detected signal exceeds the predetermined level, the comparison means outputs a reset signal for resetting the count value of the counting means, the count value of the counting means 1. A level detection circuit configured to detect a decrease in the level of the detected signal when the signal reaches the predetermined number.