JPS59121861A - Substrate for placing semiconductor element - Google Patents

Substrate for placing semiconductor element

Info

Publication number
JPS59121861A
JPS59121861A JP57234740A JP23474082A JPS59121861A JP S59121861 A JPS59121861 A JP S59121861A JP 57234740 A JP57234740 A JP 57234740A JP 23474082 A JP23474082 A JP 23474082A JP S59121861 A JPS59121861 A JP S59121861A
Authority
JP
Japan
Prior art keywords
alloy
thermal conductivity
substrate
layer
alloy containing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57234740A
Other languages
Japanese (ja)
Inventor
Nobuo Ogasa
小笠 伸夫
Akira Otsuka
昭 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP57234740A priority Critical patent/JPS59121861A/en
Publication of JPS59121861A publication Critical patent/JPS59121861A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a substrate material which has preferable thermal conductivity by covering at least part or the surface of a base metal formed of Mo or W alloy containing special amount of Cu in a thickness of the prescribed range with the film layer of the Cu or the Cu alloy containing special thermal conductivity or higher, thereby controlling the thermal expansion coefficient. CONSTITUTION:A film layer of Cu or Cu alloy having 0.03cal/cm.sec. deg.C or higher of thermal conductivity is covered on at least part of the surface of a base metal formed of W alloy containing 5-20wt% of Cu or Mo alloy containing 5-30wt% of Cu. It is in this case preferred to form a Cu or Cu alloy film layer which does not become thermal resistance with preferable soldability on the entire suface or prescribed part of the CuW, CuMo alloy surface. If the thickness if 0.5mum or less, the effect is less, and if 10.0mum or larger, the effect is saturated. If the thermal conductivity of the layer is 0.3cal/cm.sec. deg.C or less, the layer becomes a thermal resistance layer.

Description

【発明の詳細な説明】 この発明は集積回路装置等の半導体素子搭載用基板に関
するもので、塔載した半導体素子より発生する熱を効率
よく放熱しうるとともに、基板材料本来の特性である半
導体素子および他の外囲器材料と熱膨張係数が近似して
いるという性質も具ヒH1する優れた半導体素子搭載用
基板を提供せんとするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate for mounting semiconductor elements such as integrated circuit devices, which is capable of efficiently dissipating heat generated from mounted semiconductor elements, and which is capable of efficiently dissipating heat generated by semiconductor elements mounted on the substrate. Another object of the present invention is to provide an excellent substrate for mounting a semiconductor element, which also has the property of having a coefficient of thermal expansion similar to that of other envelope materials.

半導体素子搭載用の基板材料としては、従来がら半導体
素子との熱膨張係数が近似していることを重視したコバ
ール(29%Ni−17%Co−Fe)、4・2アロイ
(4= 24Ni −Fe ) 11どのNi合金やア
ルミナ、フォルステライトなどの七ラミック材料が用い
られており、特に高熱放散性を要求される場合には、各
種Cu合金が用いられてきている。
As substrate materials for mounting semiconductor elements, Kovar (29%Ni-17%Co-Fe), 4.2 alloy (4 = 24Ni - Hepteramic materials such as Fe) 11, Ni alloys, alumina, and forsterite are used, and various Cu alloys have been used especially when high heat dissipation properties are required.

しかしながら近年にふ・ける半導体産業の目覚しい発展
は、半導体素子の大型化や発熱量の増加を推進し、熱膨
張係数と熱放散性の両特性?共に満足する基板材料の必
要性がますます増大しつつある。
However, the remarkable development of the semiconductor industry in recent years has led to the increase in the size and heat generation of semiconductor elements, and the improvement of both the thermal expansion coefficient and heat dissipation properties. There is an ever-increasing need for substrate materials that are compatible.

こうした状態の中で、上述の両特性を満足する材料とし
てタングステン、モリブデンやベリリアが提案されてき
た。
Under these circumstances, tungsten, molybdenum, and beryllia have been proposed as materials that satisfy both of the above characteristics.

しかしながら後者は公害の問題から事実上使用不可能で
あり、また前二者は熱膨張係数が半導体素子Siとはよ
く合致するものの、外囲器材料としてしばしば用いられ
るアルミナの熱膨張係数との差が大きいこと、また半導
体素子とし”て最近その使用量が増加しつつあるGaA
sとは熱膨張係数の差が大きいこと、さらにはこのタン
グステンやモリブデンは熱放散性の面ではべりリアより
劣り、パッケージ設計上の制約が太きいなどの問題点を
有しているのである。
However, the latter is practically unusable due to pollution problems, and although the former two have thermal expansion coefficients that closely match those of the semiconductor element Si, there is a difference in thermal expansion coefficient from alumina, which is often used as an envelope material. GaA has a large amount of carbon dioxide, and its usage has been increasing recently for semiconductor devices.
s has a large difference in coefficient of thermal expansion, and furthermore, tungsten and molybdenum are inferior to Berria in terms of heat dissipation, and have severe restrictions on package design.

本発明者らは上記したような従来の半導体素子搭載用基
板の欠点を解消して熱膨張係数を制御するとともに、熱
伝導性良好な基板材料を得るべく検討の結果、この発明
に至ったものである。
The present inventors have developed the present invention as a result of their studies in order to eliminate the above-mentioned drawbacks of conventional substrates for mounting semiconductor elements, control the coefficient of thermal expansion, and obtain a substrate material with good thermal conductivity. It is.

即ち、この発明は、その熱膨張係数が半導体素子および
他の外囲器材料のそれに近似した数値を示し、かつ熱伝
導性にすぐれた半導体素子搭載用基板であって、Cuを
5〜2Qwt%含有したW合金又はCuを5〜30wt
%含有したMO合金からなるベースメタルの少なくとも
表面の一部にCLI又は熱伝導率がQ、3calΔ・S
eC・°C以上のCu合金の被覆層が0.5〜]、 0
.0μm被覆されていることを特徴とする半導体素子搭
載用基板である。
That is, the present invention provides a substrate for mounting a semiconductor element, which has a coefficient of thermal expansion similar to that of semiconductor elements and other envelope materials, and has excellent thermal conductivity, and which contains 5 to 2 Qwt% of Cu. 5 to 30 wt of W alloy or Cu containing
At least a part of the surface of the base metal made of MO alloy containing % CLI or thermal conductivity is Q, 3calΔ・S
Coating layer of Cu alloy of eC・°C or more is 0.5~], 0
.. This is a substrate for mounting a semiconductor element characterized by being coated with a thickness of 0 μm.

この発明において、WまたはMo中へのCuの含有量を
夫々5〜20.5〜30重量係とするのは、Slの熱膨
張係数とG a A sや池の外囲器材料である焼結ア
ルミナの熱膨張係数の双方にできるだけ近似させて、熱
膨張の不整合に起因する応力の影響を出来るだけ小さく
すると共に、できるだけ大きな熱伝導度を得るためであ
り、この範囲を越えると熱膨張の差による割れや熱放散
性の低下による半導体素子の破損が生ずる。
In this invention, the reason why the content of Cu in W or Mo is set to be 5 to 20.5 to 30 by weight, respectively, is due to the coefficient of thermal expansion of Sl, Ga As, and the sintering of the pond envelope material. The purpose is to approximate the coefficient of thermal expansion of crystalline alumina as much as possible, to minimize the influence of stress caused by thermal expansion mismatch, and to obtain as high thermal conductivity as possible. The difference in temperature causes cracks and damage to the semiconductor element due to a decrease in heat dissipation.

ベースメタルは粉末冶金法により製造することが好まし
い。
Preferably, the base metal is produced by powder metallurgy.

溶融法ではCu 、 W、 Moの融点および比重差に
より製造が困難であるからである。粉末冶金法として汎
用の粉末冶金法によればよく、なかでも焼結法、溶浸法
などが好ましい。
This is because production using the melting method is difficult due to the difference in melting point and specific gravity of Cu, W, and Mo. As the powder metallurgy method, a general-purpose powder metallurgy method may be used, and among them, a sintering method, an infiltration method, etc. are preferable.

またW中に存在するCuはW中に均一に存在しているこ
とが好ましい。加熱時のソリ等の特性上のバラツキを防
止する為であり、W粉末として粒径0.5〜10.0μ
mの範囲の粉末を用いるとよい。
Further, it is preferable that Cu present in W be uniformly present in W. This is to prevent variations in properties such as warping during heating, and the particle size of W powder is 0.5 to 10.0μ.
It is preferable to use a powder in the range of m.

力、所定量のCLI以外にW、 Moの骨格を作る為の
鉄族元素やその他諸特性を改善する為の添加物及び不可
避的な不純物は多少入っていても差し支えないが、2w
t4以下であることが好ましい。
In addition to the predetermined amount of CLI, there may be some iron group elements to form the skeleton of W and Mo, additives to improve various properties, and unavoidable impurities, but 2w
It is preferable that it is t4 or less.

この発明において、ベースメタルの表面に銅又は熱伝導
率が0.3 cal /(yH・sec ・”C以上の
銅合金の被ffl 層を設けているのは以下の如き理由
による。
In this invention, the reason why an ffl layer of copper or a copper alloy having a thermal conductivity of 0.3 cal/(yH·sec·''C or higher) is provided on the surface of the base metal is as follows.

即ち、W、 Moを母材とするベースメタル、特に粉末
焼結体の表面状態は粗度も大きく、表面研磨等の仕上加
工を施しても骨格を為すW、 Moがもともと難加工材
であることから、表面粗度を半導1イζ基板材料として
使用するまで改善することは技術的にもコスト的にもむ
つかしい。一方、本基板と能の外囲器材料であるAIJ
 203士ラミック等のろう付性による接合や、該基板
上への半導体素子搭載の際のチップボンディング性能改
善の為のAllメッキを施す上で表面状態の安定化は密
着性の向」−1所要量分Fi1mlの低減の両面から非
常に重要な問題である。
In other words, the surface condition of base metals made of W and Mo as base materials, especially powder sintered bodies, has a large degree of roughness, and W and Mo, which form the skeleton, are inherently difficult to process even after surface polishing and other finishing treatments are applied. Therefore, it is difficult both technically and cost-wise to improve the surface roughness to the point where it can be used as a material for semiconductor substrates. On the other hand, AIJ, which is the envelope material for this substrate and Noh,
203 Stabilizing the surface condition is necessary for adhesion when bonding with lamic etc. by brazing, and when applying Al plating to improve chip bonding performance when mounting semiconductor elements on the substrate. This is a very important issue from the standpoint of reducing the amount of Fi 1 ml.

コノ様f(/、−−スでは、従来がらベースメタル表面
にNノコ−ティング層を設けることが、しばしば試みら
れているが、N1ではそれ自体熱伝導塵がベースメタル
に比して悪い」二にCuW、 CuMo  合金中のC
uとの間でCuNi合金層を形成して、熱抵抗層を生じ
たり表面に強固な酸化膜を生成して密着性を低下させる
ことがある。この為、本発明では、ろう付性良好で熱抵
抗体とならないCLI又はC11合金の被覆層をCuW
、 CuMo合金表面の全面又は所要部分に設けること
により、上記問題点を解決した。
In Kono-sama f(/, ---s, it has often been attempted to provide an N coating layer on the surface of the base metal, but in N1, the thermal conductive dust itself is worse than that of the base metal.) Second, C in CuW and CuMo alloys
A CuNi alloy layer may be formed between U and U, resulting in a heat resistance layer or a strong oxide film on the surface, which may reduce adhesion. Therefore, in the present invention, the coating layer of CLI or C11 alloy which has good brazing properties and does not become a heat resistor is replaced with CuW
, the above problem was solved by providing it on the entire surface of the CuMo alloy or on a required part.

ここで、Cu又はCLI合金肢覆層の厚さを05〜] 
0. Ottm と限定したのは、05μm以下では効
果が小さく、]、 0.0 am以」二は効果が飽和し
ているからである又被覆層の熱伝導率を0.3 cat
/、671・sec・°C以上と限定したのは、これ以
下ではこの被覆層が熱抵抗層となる為である。
Here, the thickness of the Cu or CLI alloy limb covering layer is 05~]
0. The reason for limiting the thermal conductivity of the coating layer to Ottm is that the effect is small below 0.05 μm, and the effect is saturated below 0.0 am.
/, 671·sec·°C or more because below this, the coating layer becomes a heat resistance layer.

lr’r) 、チップポンディング部のAuメッキ層と
、Cu  との相互拡散が問題となる場合には、CLI
被覆層の上に更に拡散バリアーとしてのNi被覆層を形
成するとよい。この場合は下地のCu被覆層により母材
の表面状態が十分に改善されている為にNl 層の厚さ
を1μm以下と熱抵抗の而からほとんど無視できる厚さ
にすることができる。従って直接Niを被覆する場合最
低でも2μmの厚膜が必要であるのに比して熱伝導性が
明らかに向上する。
lr'r), if interdiffusion between the Au plating layer in the chip bonding part and Cu is a problem, CLI
It is preferable to further form a Ni coating layer as a diffusion barrier on the coating layer. In this case, since the surface condition of the base material is sufficiently improved by the underlying Cu coating layer, the thickness of the Nl layer can be reduced to 1 μm or less, which is almost negligible in terms of thermal resistance. Therefore, the thermal conductivity is clearly improved compared to the case where Ni is directly coated, which requires a thick film of at least 2 μm.

以上の基板において、電気的な絶縁性が必要な時には、
無機または有機の絶縁体からなる薄層コーティングを基
板の表面に施すことにより、従来セラミックが用いられ
ていた用途にも使用することも可能である。
When electrical insulation is required for the above board,
By applying a thin coating of an inorganic or organic insulator to the surface of the substrate, it is also possible to use it in applications for which ceramics have traditionally been used.

無機絶縁体の例としてはBN、 A−g 203. A
−eN。
Examples of inorganic insulators include BN, A-g 203. A
-eN.

S i 3N4. Y2O3,2Mg0. S i(h
、ダイヤモンド等又はこれらの積層体があり、厚さは0
.1〜2011mがよい。
S i 3N4. Y2O3,2Mg0. S i(h
, diamond, etc. or a laminate of these, and the thickness is 0.
.. 1 to 2011 m is good.

以上述べたように、この発明の基板を用いることにより
今後ますます増大する高密度かつ大型化の半導体素子に
対処でき、またSi素子に加えて実用化が進みつつある
GaAs素子用基板としても使用できる。
As mentioned above, by using the substrate of this invention, it is possible to handle higher density and larger semiconductor devices that will continue to increase in the future, and it can also be used as a substrate for GaAs devices, which are becoming more and more practical, in addition to Si devices. can.

以下この発明の詳細な説明する。This invention will be explained in detail below.

実施例 タングステン−0,5wt%ニッケルの混合粉末ヲ11
00X100X5の大きさに型押しした後、14.00
°CH2ガス中で焼結し28係の気孔率を有する中焼結
体を得た。この焼結体にH2ガス中にて12QQ’Cで
銅と溶浸させて、l 5Wt4  CuW合金を作製し
た。この後、表面粗度が2μmとなるまで表面仕上加工
を行ない、更に表面に通常のビロリン酸銅メッキ浴を用
いて、厚さ4・μmの銅メッキ層を形成した。
Example tungsten-0.5wt% nickel mixed powder No. 11
After stamping to size 00X100X5, 14.00
A medium sintered body having a porosity of 28 was obtained by sintering in °CH2 gas. This sintered body was infiltrated with copper using 12QQ'C in H2 gas to produce a l5Wt4CuW alloy. Thereafter, surface finishing was performed until the surface roughness was 2 μm, and a copper plating layer with a thickness of 4 μm was formed on the surface using a normal birophosphate copper plating bath.

この様にして得られた材料は、熱膨張係数が6.5xl
O−6tyn/cm・°c、熱伝導率が0.6Ca1/
/Cm・SeC・°Cで且つ他の外囲器材料たるAff
l 203  セラミックスとの銀ろう付性も極めて良
好であった。
The material thus obtained has a coefficient of thermal expansion of 6.5xl
O-6tyn/cm・°c, thermal conductivity 0.6Ca1/
/Cm・SeC・°C and other envelope material Aff
Silver brazing properties with l 203 ceramics were also extremely good.

同様の方法にて、4. wt % Cu−W合金、6w
ttll)CLI−W合金、]、 3 wt % Cu
−W合金、23wt%Cu−W合金、4. wt 4 
Cu −Mo合金、5 wt % Cu −Mo合金、
28 wtg3cu−Mo合金、33 wt%cu−へ
4o合金についても実験した結果、6wt%、18wt
%cu−W合金、Q wt係、Q Bwt係C[I−M
O合金の場合この発明の効果が得られることを確認した
In the same manner, 4. wt% Cu-W alloy, 6w
ttll) CLI-W alloy, ], 3 wt % Cu
-W alloy, 23wt% Cu-W alloy, 4. wt 4
Cu-Mo alloy, 5 wt% Cu-Mo alloy,
As a result of experiments on 28wtg3cu-Mo alloy and 33wt%cu-4o alloy, 6wt%, 18wt
%cu-W alloy, Q wt ratio, Q Bwt ratio C[I-M
It was confirmed that the effect of this invention can be obtained in the case of O alloy.

以上述べた如く、この発明は今後ますます増大すると思
われる高速・高密度IC用の基板として効果が大きい。
As described above, this invention is highly effective as a substrate for high-speed, high-density ICs, which are expected to increase further in the future.

Claims (1)

【特許請求の範囲】 (11Cu を5〜20wt4含有したW合金又はCI
を5〜30W1%含有したMo合金からなるベースメタ
ルの少くとも表面の一部にCu又は熱伝導率が0.3 
caI/z−5ec−’C以上のCu合金の被覆層が0
.5〜10.0 ltm被覆されていることを特徴とす
る半導体素子搭載用基板。 (2)ベースメタルが粉末焼結体であることを特徴とす
る特許請求範囲第(1)項記載の半導体素子搭載用基板
[Claims] (W alloy containing 5 to 20 wt4 of 11Cu or CI
At least a part of the surface of the base metal made of a Mo alloy containing 5 to 30W1% of Cu or a thermal conductivity of 0.3
Coating layer of Cu alloy of caI/z-5ec-'C or higher is 0
.. 5 to 10.0 ltm coated substrate for mounting a semiconductor element. (2) The substrate for mounting a semiconductor element according to claim (1), wherein the base metal is a powder sintered body.
JP57234740A 1982-12-27 1982-12-27 Substrate for placing semiconductor element Pending JPS59121861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57234740A JPS59121861A (en) 1982-12-27 1982-12-27 Substrate for placing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57234740A JPS59121861A (en) 1982-12-27 1982-12-27 Substrate for placing semiconductor element

Publications (1)

Publication Number Publication Date
JPS59121861A true JPS59121861A (en) 1984-07-14

Family

ID=16975611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57234740A Pending JPS59121861A (en) 1982-12-27 1982-12-27 Substrate for placing semiconductor element

Country Status (1)

Country Link
JP (1) JPS59121861A (en)

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