JPS59121421A - バルク制御方式 - Google Patents

バルク制御方式

Info

Publication number
JPS59121421A
JPS59121421A JP22725182A JP22725182A JPS59121421A JP S59121421 A JPS59121421 A JP S59121421A JP 22725182 A JP22725182 A JP 22725182A JP 22725182 A JP22725182 A JP 22725182A JP S59121421 A JPS59121421 A JP S59121421A
Authority
JP
Japan
Prior art keywords
data
bus
disk device
counter
delivered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22725182A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0430061B2 (enrdf_load_stackoverflow
Inventor
Shoji Nishioka
西岡　昇次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22725182A priority Critical patent/JPS59121421A/ja
Publication of JPS59121421A publication Critical patent/JPS59121421A/ja
Publication of JPH0430061B2 publication Critical patent/JPH0430061B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP22725182A 1982-12-28 1982-12-28 バルク制御方式 Granted JPS59121421A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22725182A JPS59121421A (ja) 1982-12-28 1982-12-28 バルク制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22725182A JPS59121421A (ja) 1982-12-28 1982-12-28 バルク制御方式

Publications (2)

Publication Number Publication Date
JPS59121421A true JPS59121421A (ja) 1984-07-13
JPH0430061B2 JPH0430061B2 (enrdf_load_stackoverflow) 1992-05-20

Family

ID=16857882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22725182A Granted JPS59121421A (ja) 1982-12-28 1982-12-28 バルク制御方式

Country Status (1)

Country Link
JP (1) JPS59121421A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5533279A (en) * 1978-08-31 1980-03-08 Fujitsu Ltd Magnetic tape control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5533279A (en) * 1978-08-31 1980-03-08 Fujitsu Ltd Magnetic tape control system

Also Published As

Publication number Publication date
JPH0430061B2 (enrdf_load_stackoverflow) 1992-05-20

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