JPS59121378A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a display device using CRT, liquid crystal, plasma, or the like.

TECHNICAL BACKGROUND OF THE INVENTION AND PROBLEMS THEREOF Generally, in a display device, there are cases where it is desired to display certain characters among the characters on the same screen in an emphasized manner. Conventionally, as such a highlighting method, methods such as inverted display of displayed characters, blinking display, and brightness change display have been adopted. In all of these cases, the size of the displayed characters remains the same and is not particularly emphasized.

In this regard, although there are some devices in which specific display characters are displayed by enlarging the basic characters twice as much in the horizontal direction, there are no devices in which the basic characters are displayed by enlarging them in the vertical direction.

Purpose of the Invention The present invention has been made in view of the above points, and an object of the present invention is to provide a display device that can enlarge any character vertically and highlight it, making it easier to see the displayed content. shall be.

SUMMARY OF THE INVENTION By providing a vertical enlargement display circuit, the present invention can highlight vertically enlarged characters mixed with normal basic characters on the same screen, and in combination with a horizontal enlargement display circuit. It is constructed so that it can arbitrarily display characters 7 of 4 $i sizes, including letters, basic characters, vertically enlarged characters, horizontally enlarged characters, and vertically and horizontally enlarged characters.

Examples of the invention An embodiment of the present invention will be described based on the drawings.

This embodiment is applied to a CRT display device, and first, its basic configuration and operation will be explained with reference to FIGS. 1 to 3. FIG. 1 is a timing chart showing the specifications of a CRT display device, where A (horizontal deflection time) = 42.02
μs, B (horizontal effective display time) = 29.7 μs.

C (horizontal synchronization position) = 29.7 μs, D (horizontal synchronization width)
= 12.36μs, E (vertical deflection time) =
23.03m5, F (vertical effective display time) = 21
．． 51m5, G (vertical synchronization position) = 10.76
m5, I (vertical synchronization width) = 0.672 m5 b Also, assume that the screen displays 40 characters horizontally and 20 lines vertically, and the dot configuration of one character is (horizontal 16 dots) x ( 24 vertical dots).

In FIG. 2, the horizontal synchronizing signal and vertical synchronizing signal necessary to drive the CR1 display section (1) are output from the CRT controller (2).
The T controller (2) is programmed by a CPU (not shown) via data buses DO to D7. In addition, the oscillation frequency of the crystal oscillator (3) is B =
29.7μS, so 297μs/(16 dots x 40 characters) = 46.4025ns (= 21.5
488MHz) is found9, and this time becomes the display time of one dot. 46.402 from this crystal oscillator (3)
A synchronous counter (4) (for example, 748163) to which a 5 ns clock signal CP is input has a memory (power (8
) output data latch timing, shift register (
I: Timing to load the output data of the 1-h character generator circle, display time for one character in the horizontal direction given to the clock CLK terminal of the CFLT controller (2) 4
It generates signals such as 6.4062ns x 16 dots and 742.5ns, and functions to create QB, QCI, and QD. Here, 臥=2CP, QB=4CP, QC28CP, QD=16CP, and a NAND game (t14) is provided which takes these as inputs, and its output is determined by the memory output data latch timing and shift. This is the load timing pulse for register 0 (to). CRT controller (2) l"l:/' 0tsuku CL
MAO to MA with a maximum delay of 160ns from the falling edge of the K terminal
At the same time as outputting the display address to 99% A child,
□ Line counters RAO to RA4 indicating which line of 24 vertical dots is being scanned are also output. Here, MAO
-MA9 are counted up every falling edge of the pulse input to the clock CLK terminal, but line counters RAO-RA4 do not count up until the scanning of one line is completed. In addition, the CRT controller (
2) MAO to MA9 output from the data selector (
5), the CPU address information AO to A9 is given to the input of this data selector (5), and the signal given to the clock CLK terminal of the cRT controller (2) is given to the input of the data selector (5). Address information from the CPU is AO to A9 when it is at L level, and MAO to M when it is at H level.
A9 is given to AO to A9 of the video memory (7) and index memory (8) in a time-sharing manner, respectively. Here, when MAO to MA9 are input to the video memory (7) and index memory (8), the two memories (7) and (8) are always chip-selected, and the addresses AO to A9 from the CPU are input. Chip selection is performed only when the output of the memory decoder (6) is at L level. And from CPU to memory (7) (8)
When reading/writing to C, since the CPU and QD of the synchronous counter (4) are completely asynchronous,
When the read/write pulse is output from the PU to the memory (power (8)), a Not Ready (Not Ready) signal is sent to the CPU.
Ready) must be output and held until the synchronous counter (4) rises. By the way, the video memory (7) is for storing the codes of display characters for (40 characters in the horizontal direction) x (20 lines in the vertical direction), and the index memory (8) is for specifying horizontal enlargement of the display characters. This is a memory for specifying vertical enlargement in bit correspondence. The access time of such memories (7) (8) (up to 150 ns
), when the memory output data is certain, NAND
Output data is latched into latches (9) and (10) by the output of gate I, and becomes address input to character generator αυ. Here, the character generator αυ
has a 16-bit output, but most of the output is usually 8-bit, so the left half and right half of the character are stored in separate ICs and output. Then, after the access time (450 ns) of character generator αυ, the 16 bits output from character generator αη are loaded into shift register 0, and are output as serial data from the QH terminal of shift register α4 every time a clock signal is input. 1). As a result, basic characters are displayed.

Therefore, the horizontal enlargement display circuit uS and the vertical enlargement display circuit (16
) are provided which can be freely selected and synthesized, and the specific circuit configurations are shown in FIGS. 4 and 6, respectively. Here, all display character enlargement specifications are stored in the index memory (8 bits), and these are 3 bits in total, namely: ■ Vertical expansion designation bit (sets H level when enlargement is specified), ■ Vertical expansion character bit These are a pit that specifies the upper half and lower half of the image (the upper half is set to L level and the lower half is set to H level), and (1) horizontal expansion designation bit (set to H level when enlargement is specified).

Now let's think about horizontal expansion. Latte α [When the horizontal expansion designation bit is output at H level, the horizontal expansion display circuit (1
In 51, the reset of element (17) (using 74L874) is released, and the select terminal of element (using 74L8157 t-) also becomes H level, so the output terminals IY and 2Y of this element end are changed from those by IA and 2A. IB
, 2B -0 The outputs IY and 2Y of this element α~ are respectively supplied to the clock CLK terminal and shift/load SH/LO terminal of shift register 0, and the horizontal expansion designation bit is at H level. As a result, the period of both the dot clock and shift/load clock becomes half that of the basic character. As a result, the displayed characters are displayed as horizontally enlarged characters that are twice the size of the basic characters in the horizontal direction. FIG. 5 is a timing chart showing such an operation. The part indicated by the dotted line in FIG. 5(2) is the load pulse of the shift register (13i) that occurs in the case of basic characters.

Next, let's think about vertical expansion. First, the specific circuit configuration of the vertical enlargement display circuit (LE9) is as follows.
LS157) and element CA (74L8283)
The outputs RMAO1-RMA31 from each element and the output ELMA41 from the gate circuit are set to be input to AO-A4 of the character generator αυ. Here, the output pasteboard 41 is the lower 8 of the 24 vertical dots of one character.
This allows the dots to become spaces. Now, if the vertical expansion designation bit is not at H level, element 04 will not be selected, so the line addresses HMA01 to RMA41 input to AO-A4 of the character generator circle are C
Line counter output RA from RT controller (2)
The ones based on O1-RA41 are for basic characters.

Therefore, when the vertical expansion designation bit is output at H level from latch α[α2, the select terminal of element R (22) becomes Hv level due to this vertical expansion designation bit, so that the AO of character generator (11) The line address RM&01-RMA41 input to ~A4 is the line counter RAOI~M4 from the CRT controller (2).
The output of seven elements Φ instead of 1 is adopted. As a result, the input terminals A1 to A4 of element (21) are different in the lower half of the vertically enlarged display character. The contents of input B are input. That is, the vertically enlarged character occupies two lines compared to the basic character, and the constituent elements of the character are separated into upper line and lower line. At this time, Regardless of whether it is a vertically enlarged character or a basic character, the lowest dot rows are arranged on the same line. It is the same as in the case of 8 bits.

The enlarged characters are corrected and decomposed by the correction circuit CD in consideration of such space. In the vertical enlarged display, the line counter is counted up only after two horizontal scanning lines have been scanned, and the vertical display dots are doubled and enlarged.

Now, as a specific example, let us consider the case where the character ``j'' is displayed in parallel as a basic character and a vertically enlarged character, as shown in Figure 7.In order to include such vertically enlarged characters,
+1) will occupy two lines. First, Motoko Ren
According to the line address RMAOI to RMA41 for the upper half of the wound j based on the contents of the A input, the lower half of the wound is enlarged and displayed as shown in FIG. 7 (-) when n lines are scanned. . At this time, if it is a basic character, it will be displayed from the top of the 16 dot x 24 dot frame surrounded by a square.
As mentioned above, since the correction circuit (Jl) performs the correction, it can be seen that in the case of vertically enlarged characters, a space for 8 dots is also secured at the top. Then, when the scan moves to the (n+x)th line, the lower half of "Wound" is enlarged and displayed in parallel with the basic characters based on the B input of element -, and the basic characters for two lines and the vertically enlarged characters are mixed. The display is as shown in the same figure ('').As shown in Figure 7, the lowest dots of the vertically enlarged characters are aligned with the lowest dots of the basic characters, resulting in a clear display. .

Note that the line n at which the vertically enlarged display starts may be an even numbered line or an odd numbered line, and it is sufficient to take into account that the vertically enlarged character occupies two lines.

Furthermore, if both the horizontal expansion designation bit and the vertical expansion designation bit are set to H level, the horizontal expansion display circuit (151) and the vertical expansion display circuit μyama operate simultaneously, their outputs are combined, and the vertical and horizontal expansion characters are also displayed. Therefore,
According to this embodiment, characters of four different sizes, ie, basic characters, horizontally enlarged characters, vertically enlarged characters, and vertically and horizontally enlarged characters, can be displayed in a mixed manner, and appropriate highlighting can be performed.

Effects of the Invention Since the present invention is provided with a vertically enlarged display circuit as described above, it is possible to highlight vertically enlarged characters mixed with normal basic characters on the same screen. 9. Also, since it is combined with a horizontal enlargement display circuit, it is possible to display basic characters, vertically enlarged characters,
It is possible to arbitrarily display four types of bold characters: horizontally enlarged characters and vertically and horizontally enlarged characters.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a timing chart, FIG. 2 is a block diagram, FIG. 3 is a timing chart, FIG. 4 is a circuit diagram, FIG. 5 is a timing chart, and FIG. The figure is a circuit diagram, and Figure 7 (α) is an explanatory diagram showing an example of the display.
People Tokyo Electric Co., Ltd.

Claims (1)

[Scope of Claims] 1. A display device characterized by being provided with a vertical enlargement display circuit for displaying characters which are vertically enlarged basic characters mixed with basic characters on the same screen. 2. A vertical enlargement display circuit for displaying characters that are enlarged in the vertical direction of the basic characters mixed with the basic characters on the same screen is provided, and a horizontal enlargement display circuit for displaying the characters that are enlarged in the horizontal direction for the basic characters is installed on the same screen. A display device characterized by being provided with an enlarged display circuit that can be freely selected and combined.