JPS59119873A - Punch-through type constant-voltage element - Google Patents

Punch-through type constant-voltage element

Info

Publication number
JPS59119873A
JPS59119873A JP22790482A JP22790482A JPS59119873A JP S59119873 A JPS59119873 A JP S59119873A JP 22790482 A JP22790482 A JP 22790482A JP 22790482 A JP22790482 A JP 22790482A JP S59119873 A JPS59119873 A JP S59119873A
Authority
JP
Japan
Prior art keywords
layer
junction
punch
depletion
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22790482A
Other languages
Japanese (ja)
Inventor
Kazuo Yamagishi
和夫 山岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP22790482A priority Critical patent/JPS59119873A/en
Publication of JPS59119873A publication Critical patent/JPS59119873A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To generate a punch-through extending over the whole region of a depletion layer, and to obtain low stable voltage characteristics by forming a junction between one conduction type layer under a reverse bias contributing to a punch-through phenomenon and the other conduction type layer into a torus shape. CONSTITUTION:The lateral fringe of an n<-> layer 10 is surrounded by a torus- shaped p<+> layer 15 in impurity concentration equal to a P<+> layer 8 so that the spreads of depletion layers in the lateral section 10'' of the n<-> layer 10 and the p<+> layer 8 are made the same as a section 10' immediately under the junction. When an electrode 13 is brought to positive poatential and an electrode 9 to negative potential in the punch-through type constant-voltage element constituted in this manner, the p-n junction 6 between a p<+> layer 11 and the n<-> layer 10 is brought to a forward bias, and the depletion layer 17 of the junction is narrowed. On the other hand, the p-n junction 18 among the torus-shaped p<+> layer 15 and the p<+> layer 8 and the n<-> layer 10 is brought to a reverse bias, a depletion layer 19 expands, the section 10' immediately under the junction on the n<-> layer 10 side and the lateral section 10'' are extended remarkably more than the p<+> layer 8, and the punch-through phenomenon is generated particularly in a region of the lateral section 10''. Accordingly, currents relaxed to uniform density are flowed, and low voltage is easily controlled particularly by stable breakdown voltage.

Description

【発明の詳細な説明】 技術分野 この発明は、構造がトランジスタに類似しているサンド
イッチ形PN構造を有するパンチスルー型定電圧素子の
定電圧特性改善に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to improving the constant voltage characteristics of a punch-through type constant voltage element having a sandwich-type PN structure whose structure is similar to a transistor.

背景技術 従来より定電圧素子としては、周知のように、PN接合
の空乏層に量子力学的トンネル効果による陥伏現象を起
させる、いわゆるツエーナダイオードが実用化されてい
る。しかしこのツエーナダイオードでは、逆方向の降伏
電圧が比較的高い範囲でしか定電圧特性が得られず、低
い定電圧が得られたとしても、動作抵抗が大きくなりそ
の結果PN接合の温度上昇が起りしかもノイズを発生さ
せる欠点がある。そこで、上述のツエーナダイオードに
替り、欠点是正を図る定電圧素子として第1図に示すよ
うに2層1上に9層2を形成し、式らに9層2の中に2
層3を選択拡散させて、pnpサンドインチ形構造とし
た素子が提案されている。
BACKGROUND ART Conventionally, as a constant voltage element, a so-called Zener diode, which causes a collapse phenomenon due to a quantum mechanical tunnel effect in a depletion layer of a PN junction, has been put into practical use. However, with this Zener diode, constant voltage characteristics can only be obtained in a range where the reverse breakdown voltage is relatively high, and even if a low constant voltage can be obtained, the operating resistance increases and the temperature of the PN junction increases. However, it also has the disadvantage of generating noise. Therefore, instead of the above-mentioned Zener diode, nine layers 2 are formed on two layers 1 as shown in FIG.
A device has been proposed in which layer 3 is selectively diffused to form a pnp sandwich-inch structure.

この素子は、パンチスルー型定電圧素子と称されるもの
で、n〜2のベース伽W全数μmと薄く、かつ9層2の
比抵抗を高く設定することにより、2層1’)正、2層
3を負にバイアスした時に、逆バイアスされるpn接合
4近傍の空乏層5を、nj曽2内で拡張させて正ノくイ
アスのpn接合6の空乏層ワ′\到達させてし1うノぐ
ンチスル−現象を希1」用したものである。ところカー
、このノぐンチスル−型定電圧素子にも次に述べる問題
点力;ある。すなわち、一般にn層2内におけるP層j
3直下音IS2′と横部2”とては、広がり抵抗が不均
等であるために、空乏層5においても直下対応部5′と
1黄ス4元、音IS5“とで1)ム張度合が異り、十分
低い安定した電圧特惺ミカ;得着かったのである0 発明の開示 この発明は、以上の事情に61み提案されたもので、以
前よりの7ぜンチスル−型定電圧素子の出1順点解決の
ために、ノくンチスル−現象に寄与する逆バイアスの一
導電刑層と他導電型層との接合を、円環状に設定するこ
とを特徴として(/する。した力量ってこの発明によれ
ば、空乏層全域に亘る)ぐンチスルーが起り低い安定し
た電圧特性力;得られることは勿論、動作時の電流集中
が極力緩和されpn接合が電流集中による局所的破壊防
d二にも貢献できる長所がある。
This element is called a punch-through type constant voltage element, and is as thin as the total number of μm in the base case W of n~2, and by setting the resistivity of the nine layers 2 to be high, the two layers 1') positive, When the second layer 3 is negatively biased, the depletion layer 5 near the reverse biased pn junction 4 is expanded within nj so 2 and reaches the depletion layer of the positive pn junction 6. This is a unique use of the ``Unogunchisuru'' phenomenon. However, this constant voltage constant voltage element also has the following problems. That is, generally the P layer j in the n layer 2
Since the spread resistance is uneven between the sound IS2' directly below 3' and the horizontal part 2', the corresponding part 5' and the sound IS5' directly below the depletion layer 5 are Disclosure of the Invention This invention was proposed in response to the above circumstances, and is a 7-point through-type constant voltage that is different from the previous one. In order to solve the problem of the device's output, the junction between the layer of one conductivity type and the layer of the other conductivity type with reverse bias, which contributes to the phenomenon of "no-kunchi-through", is set in an annular shape. According to this invention, this invention provides stable voltage characteristics that are low and do not cause "gunchi-through" (over the entire depletion layer). It also has the advantage of contributing to D2 defense.

発明を実施するための最良の彫態 第2(2)は、この考案の一実施例を示すノぐンチスル
ー型定電圧素子の断面図で、pip型サンすイッチ構造
である点では、従来の素子と同様であるが、逆バイアス
されるPN接合構造及びノ〈イアスの向きが異っている
。第2図におl/へて、8は、その裏面に負側電極9を
形成したP+14.10はP“層8上にエピタキシャル
成、長させた万一層、11はn一層10中に拡散させた
P 層である。12は、表面の絶縁保護を行っている酸
化膜、そして13は、酸化膜12のP+層11対応部を
窓開けして2層11と接続させた正側電極である。さて
、ここで、負側(バイアスされるp+111gは、酸化
膜12及び正側電極13を除去した状態の平面を示した
第3図から明確な様に、n一層10の横WIIO″とP
層8とにおける空乏層14の拡がりが、直下部10’に
おける場合と同等となるように、ni@loの横方向周
縁は、P+層8と等しい不純1物濃度の円環4火P+層
15により囲まれている。
The best embodiment for carrying out the invention No. 2 (2) is a cross-sectional view of a switch-through type constant voltage element showing an embodiment of the invention, which is different from the conventional one in that it has a pip-type switch structure. The device is similar to the device, but the reverse biased PN junction structure and the direction of the noise are different. In Figure 2, 8 is a P+14 layer with a negative electrode 9 formed on its back surface, 10 is a layer epitaxially grown and grown on the P'' layer 8, and 11 is an N layer diffused into the layer 10. 12 is an oxide film that provides insulation protection on the surface, and 13 is a positive electrode that is connected to the second layer 11 by opening the part of the oxide film 12 corresponding to the P+ layer 11. Now, as is clear from FIG. 3, which shows the plane with the oxide film 12 and the positive electrode 13 removed, the negative side (biased p+111g) is the lateral WIIO'' of the n layer 10. P
In order to spread the depletion layer 14 in the layer 8 to the same extent as in the directly lower part 10', the lateral edge of the ni@lo is formed by forming a ring 4 P+ layer 15 with an impurity concentration equal to that of the P+ layer 8. surrounded by

したがって上記構成としたノマンチスル−型定電圧素子
は、電極13を正電位に、電極9を負電位にすれば、P
+層11とn一層10とのPN接合161″1.順バイ
アスとなりその空乏層17は狭く、逆に円環状P+層1
5及びP″一層8とn一層1.0とのPN接合18は逆
バイアスとなり、空乏層19は、拡張し、P層8に比べ
n一層lO側の直下部IQ’及び横部lO“における伸
びが著しくなり特にイItJ部10//の領域にてパン
チスルー現象が起り降伏状態と同様な状況になる。この
ような状況になる根拠・は、次の説明により了解できる
であろう。すなわち、この素子は、n一層10の横部l
o yが、円環状P+層15て囲まれるから、第3図に
おいて微小扇形区仙120を想定して、その中のpH1
5の面積S1と7q%lOの而+8S2を比較すると、
常K ’ S+ > 82の関係にあり、しかも不純物
濃度は当然n一層中の横部lO″が低いので、横部コ、
 o//は、PN接合表面近傍部の耐圧全強化するいわ
ゆるベベル構造となり、空乏層19の伸びが顕著となる
′からである。よってこのパンチスルー型定電圧素子で
は、第2図及び第3図に矢印細線21,21.・・・・
 で示すように、均一な密度に緩和された電流が流れる
ことにもなり安定した降伏電圧で特に低電圧の制御が容
易でありしかも電流集中によるホットスポット全土じる
ことがない良好な特性が得られる。
Therefore, in the nomanthyl constant voltage element having the above structure, if the electrode 13 is set to a positive potential and the electrode 9 is set to a negative potential, P
PN junction 161″1 between the + layer 11 and the n layer 10 becomes forward biased, and its depletion layer 17 is narrow, and conversely, the annular P+ layer 1
The PN junction 18 between the 5 and P'' layer 8 and the n layer 1.0 becomes reverse biased, and the depletion layer 19 expands, and the depletion layer 19 expands, compared to the P layer 8, at the immediate lower part IQ' and the lateral portion lO'' on the n layer lO side. The elongation becomes significant, and a punch-through phenomenon occurs particularly in the region of the ItJ section 10//, resulting in a situation similar to a yield state. The basis for this situation can be understood from the following explanation. That is, this element has n layers 10 and lateral portions l.
Since o y is surrounded by the annular P+ layer 15, assuming a minute fan-shaped area 120 in FIG.
Comparing the area S1 of 5 and the area +8S2 of 7q%lO,
There is a constant relationship K' S+ > 82, and since the impurity concentration is naturally lower in the lateral part lO'' in the n layer, the lateral part
This is because o// forms a so-called bevel structure in which the withstand voltage in the vicinity of the PN junction surface is fully strengthened, and the elongation of the depletion layer 19 becomes remarkable. Therefore, in this punch-through type constant voltage element, thin arrow lines 21, 21 .・・・・・・
As shown in Figure 2, a relaxed current flows in a uniform density, making it easy to control particularly low voltages with a stable breakdown voltage, and good characteristics are obtained in which hot spots do not spread all over due to current concentration. It will be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来よりのパンチスルー型定電圧素子の断面
図、第2図は、この発明の一実施例を示すパンチスルー
型定電圧素子の縦断面図、第3図1はその電極、酸化膜
を除去した場合の横断面図である。 8・・ P 胤(−導電型)、 lO・・・・・ n一層(他導電型)、11・・・・ 
P+層(=導電型)、−15・・・・・円環状P+層。 特許出願人  新日本電気株式会社
FIG. 1 is a cross-sectional view of a conventional punch-through type constant voltage element, FIG. 2 is a longitudinal cross-sectional view of a punch-through type constant voltage element showing an embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view when an oxide film is removed. 8... P seed (- conductivity type), lO... n single layer (other conductivity type), 11...
P+ layer (=conductive type), -15... annular P+ layer. Patent applicant ShinNippon Electric Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 一導電型層上K (m導を型層を形成し、さら如イ9(
導電型層上に一導電型層を形成して、サンドインチ構゛
造とし、サンドイッチ構造のベース領域となる他導電型
層中でバンチスルー現象を起させるものに関して、パン
チスルー現象に寄与する逆バイアスの一導電型層上(l
f4導電型層との接合を、円環状に設定したことを特徴
と1゛るパンチスルー型定電圧素子。
Form a type layer on the one conductivity type layer, and then
A layer of one conductivity type is formed on a layer of one conductivity type to form a sandwich structure, and with respect to the layer that causes the bunch-through phenomenon in the layer of the other conductivity type that serves as the base region of the sandwich structure, the reverse effect that contributes to the punch-through phenomenon is On one conductivity type layer of bias (l
1. A punch-through type constant voltage element characterized in that the junction with the f4 conductivity type layer is set in an annular shape.
JP22790482A 1982-12-27 1982-12-27 Punch-through type constant-voltage element Pending JPS59119873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22790482A JPS59119873A (en) 1982-12-27 1982-12-27 Punch-through type constant-voltage element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22790482A JPS59119873A (en) 1982-12-27 1982-12-27 Punch-through type constant-voltage element

Publications (1)

Publication Number Publication Date
JPS59119873A true JPS59119873A (en) 1984-07-11

Family

ID=16868121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22790482A Pending JPS59119873A (en) 1982-12-27 1982-12-27 Punch-through type constant-voltage element

Country Status (1)

Country Link
JP (1) JPS59119873A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455873A (en) * 1987-08-27 1989-03-02 Matsushita Electronics Corp Semiconductor integrated circuit having surge protecting function

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110580A (en) * 1974-02-08 1975-08-30
JPS5532035A (en) * 1978-08-29 1980-03-06 Fujitsu Ltd Electrophotographic type plural color electrostatic recording system
JPS57126170A (en) * 1981-01-27 1982-08-05 Toshiba Corp Semiconductor constant voltage device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110580A (en) * 1974-02-08 1975-08-30
JPS5532035A (en) * 1978-08-29 1980-03-06 Fujitsu Ltd Electrophotographic type plural color electrostatic recording system
JPS57126170A (en) * 1981-01-27 1982-08-05 Toshiba Corp Semiconductor constant voltage device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455873A (en) * 1987-08-27 1989-03-02 Matsushita Electronics Corp Semiconductor integrated circuit having surge protecting function

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