JPS59119656U - stereo demodulator - Google Patents
stereo demodulatorInfo
- Publication number
- JPS59119656U JPS59119656U JP1983013005U JP1300583U JPS59119656U JP S59119656 U JPS59119656 U JP S59119656U JP 1983013005 U JP1983013005 U JP 1983013005U JP 1300583 U JP1300583 U JP 1300583U JP S59119656 U JPS59119656 U JP S59119656U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- stereo
- stereo demodulator
- composite signal
- subcarrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は一般的なＦＭ受信機の構成図、第２図は従来の
ステレオ復調器の回路構成図、第３図は第２図の動作を
説明する波形図、第４図は本考案の一実施例を示す回路
構成図、第５図はその動作を示す波形図、第６図は第４
図の回路に用いるリニア掛算器の一例を示す回路構成図
である。
８・・・サブキャリア信号発生回路、１３・・・フィル
タ、１４・・・リニア掛算器、１５．１６・・・マトリ
クス回路。Fig. 1 is a block diagram of a general FM receiver, Fig. 2 is a circuit block diagram of a conventional stereo demodulator, Fig. 3 is a waveform diagram explaining the operation of Fig. 2, and Fig. 4 is a diagram of a conventional stereo demodulator. A circuit configuration diagram showing one embodiment, FIG. 5 is a waveform diagram showing its operation, and FIG.
FIG. 3 is a circuit configuration diagram showing an example of a linear multiplier used in the circuit shown in the figure. 8... Subcarrier signal generation circuit, 13... Filter, 14... Linear multiplier, 15.16... Matrix circuit.
Claims (1)
の基本周波数成分とを、面入力レベルの変化に対して出
力レベルが直線的に変化するリニア掛算器に入力してス
テレオ複合信号中に含まれるサブ信号を復調するように
構成したことを特徴とするステレオ復調器。The FM-detected stereo composite signal and the fundamental frequency component of the subcarrier signal are input to a linear multiplier whose output level changes linearly with changes in the surface input level to calculate the subcarrier signal contained in the stereo composite signal. A stereo demodulator configured to demodulate a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983013005U JPS59119656U (en) | 1983-02-01 | 1983-02-01 | stereo demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983013005U JPS59119656U (en) | 1983-02-01 | 1983-02-01 | stereo demodulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59119656U true JPS59119656U (en) | 1984-08-13 |
| JPH048679Y2 JPH048679Y2 (en) | 1992-03-04 |
Family
ID=30144399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983013005U Granted JPS59119656U (en) | 1983-02-01 | 1983-02-01 | stereo demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119656U (en) |
-
1983
- 1983-02-01 JP JP1983013005U patent/JPS59119656U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH048679Y2 (en) | 1992-03-04 |
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