JPS59119445A - Parallel multiplier circuit - Google Patents

Abstract

PURPOSE:To enable widening of range of variation of input signal that can cope with keeping time of multiplication as it is by providing a digit shifting circuit in the I/O section of a multiplier. CONSTITUTION:When the magnitude of input signals 101 and 103 exceeds input range of the multiplier 100, it is shifted down in shifting down circuits 102, 104 until it comes within the range and inputted to the multiplier 100 as new input signals 105, 106. At the same time, shifting down signals 107, 108 that indicate number of digits shifted down are outputted and inputted to a shifting up signal generating circuit 110. Input signals 105 and 106 are multiplied in the multiplier 100 and a product 109 is outputted. Signals 107 and 108 are added in the circuit 110, and outputted as a shifting up signal 112. The product 109 and shifting up signal 112 are inputted to a shifting up circuit 111, and shifted up by the number of digits indicated by the signal 112 and outputted anew as a product 113.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital multiplication circuit, and particularly to a parallel multiplication circuit required for high-speed calculation.

[Technical background of the invention and its problems]

Multiplier circuits are often required in digital signal processing, and parallel multiplier circuits are often used especially when performing high-speed multiplication. However, this circuit has the drawback of requiring many elements. For example, multiplication of (ψXn) pits requires approximately mn full adders.

Therefore, when dealing with a signal input to a multiplier as a multiplier or a multiplicand with a wide variation range, the circuit size will be significantly increased.

On the other hand, some signals that are often handled have a wider variation range than the number of effective digits. For example, the range of change is 2
Even though there are 11 bits (7 to 23), the number of effective digits of the signal is only 7 bits. Specifically, 2~
This is a case where the magnitude of an input signal is changed within a range of 2 to 2 with 7-pit accuracy. If this control is performed only with a multiplier, a 7-bit (@) x 11-bit (control) multiplier is required, which not only requires a large amount of circuitry but also has poor efficiency as it involves calculations that exceed the number of significant digits. There is a problem in that it takes more calculation time than necessary.

[Purpose of the invention]

The present invention was developed in view of this point, and its purpose is to provide a digital multiplier that can substantially expand the range of input signal changes that can be handled by the multiplication time by simply adding a small number of circuits to the conventional parallel multiplier. The purpose of the present invention is to provide a multiplication circuit.

[Summary of the invention]

The present invention provides a digit shift circuit in at least one input section of a multiplier, detects the magnitude of a signal input therein, performs digit shift based on this, and inputs the signal to the multiplier, - On the output side, the multiplier output signal is shifted by digits so as to cancel out the digit shift performed on the input side. Note that the digit shift in the input section changes the magnitude of the input signal so that the input signal falls within a predetermined range of the multiplier input. [Effect of the Invention] According to the present invention, the multiplier By providing a digit shift circuit in the input/output section of the digit shift circuit, it is possible to expand the range of change in signals that can be effectively multiplied. The effects are as follows:

First, compared to increasing the multiplication range by using the wavelength of the multiplier itself, it is possible to significantly reduce the amount of circuitry required.

Second, the calculation time is considerably reduced compared to expanding the multiplication range by using the multiplier itself as a wavelength.

Third, by adding the above-mentioned digit shift circuit to the general-purpose multiplier, the multiplication range can be set to any wavelength.

Note that the circuit scale and calculation time will be mentioned in the next section while explaining an embodiment.

[Embodiments of the invention]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

In FIG. 1, it is assumed that the number of bits of input signals 101 and 103 is greater than the number of input bits of multiplication 6100.

The human input signal 101 is input to the downscaling circuit 102, and if the magnitude of the value exceeds the predetermined input range of the multiplier 1oo, the human input signal 101 is downscaled until it falls within the predetermined input range of the multiplier 1oo, and a new input signal 105 is sent to the multiplier 100. is input. At this time,
A down-down signal 107 indicating how many down-downs have been performed is output.

The input signal 103 is similarly input to the downscaling circuit 104,
A new input signal 106 and a carry down signal 108 are output.

Multiplier 100 multiplies input signals 105 and 106,
The product 109 is output. , indentation 1 word 107 and 108
is input to the carry signal generation circuit 110. Here, the total number of carry downs performed in the carry down circuits 102 and 103 is calculated by adding the 10871c-to the 10871c-down signal, and outputs it as carry 1g signals 112 and 1-. The product 109 and the carry 1δ number 112 are input to the carry circuit 111, and the product 10 is
9 is carried and a new product 113 is output.

The above is a general overview of the present invention. Note that when performing a carry down operation on only one input word, for example, the input signal 101, the carry down circuit 104 and the carry 1d number generation circuit 110 are not necessary.

A specific example of the configuration of each circuit will be described below. First, the number of bits and range of each signal in the embodiment described here are shown in the following table.

Therefore, this is an example in which a multiplier 100 with an input of 5.times.5 bits and an output of 10 pits is used to perform multiplication of an input variation range of 7.times.7 bits and an output variation range of 14 bits. Of course, the number of effective digits of each signal is uniquely determined by the performance of the multiplier 100.

FIG. 2 is a diagram showing a specific example of the configuration of the carry down circuit 102.・In addition, in FIG. 2, the carry down circuit 103 probably has the same configuration as this, the carry down circuit 102 is composed of a digit shift circuit 201 and a carry down signal generation circuit 202,
With these, the magnitude of the input signal 1.01 (2' to 25) is detected, and a digit is lowered so that it falls within the multiplier 1000 input range of 2 to 2. Specifically, the 21.2 degree digit of the input signal 101 is input to the down-down signal generation circuit 202, and the down-down signal 107 (203
゜204.205).

The digit downshift signal 107 is output to the external jl( and is also input to the digit shift circuit 201. The digit shift circuit 201 is
Consists of five 3to1 data selectors.

These have input No. 16 101 of O bits and 1 bit, respectively.
The focus is input with a 2-bit shift (downward).
When the 1-i down signal 203 is 1, a 2-bit not signal is selected, when the signal 204 is 1, a 1-bit shifted signal is selected, and when the signal 205 is 1, a 0-pitch I shifted signal is selected, and multiplication is performed. It is output as a device input signal 105 (2'' to 2''). With this operation, the magnitude of the input signal 101 is 2 digits when A') is ≧21, 1 digit when 2') A'≧2°, and 0 digits when A'<2°, respectively. lowered 7
No. 18 105 falling within the range of L, 2-1 to 2-5 is output.

Referring to FIG. 1, multiplier input signals 105 and 106 are multiplied by multiplier 100, and product t's 109 (2-2) is output. Multiplier 100 is a normal parallel multiplier. On the other hand, the carry down signals 107 and 108 are provided by the carry signal generation circuit 11.
Input to 0. Figure 3 shows the carry number 18 generation circuit 110.
It is a diagram showing the (tY arrangement of .

Outside, the lowering signals 301, 302, 303 are the f previous number 203, 204, 205 in the lower number 1 word 107.
, and each corresponds to the case where the input signal 103 is 2
This means that the digit has been lowered by one digit, one digit, or zero digit. The function of the carry signal generation circuit 110 is to generate the carry down signal 107,1.
The contents of 08 are added, the total number of carry downs performed by the carry down circuits 102 and 104 is calculated, and this is outputted as a carry signal 112.

The gate configuration shown in FIG.
The total number of digits carried out is 4°3.2 and 1.
0, the signal 304 constituting the carry signal 112
, 305, 306, 307, and 308 each become 111.

In FIG. 1, product signal 109 (2-2) and carry signal 112 are input to carry circuit 11.1. FIG. 4 is a diagram showing the configuration of carry circuit 111. The pumping circuit 111 is composed of 0114 5to1 data selectors. FIG. 5 is a diagram showing the internal configuration of the data selector 401. These 5 (D input IM No. 402 (D
O~IJ4)'a=5 selections f, ff11403(8
0-84) and obtains an output signal 404 (Y). In FIG. 4, the manually input product signal 109 (2-2)
4 data inputs 1) O to I) 4K are input in the form of shifted (carried) 0 bits and 1 bits to 4 bits, respectively. Here, since the product signal 109 of the IO pits is converted into the output signal 113 of 14 pits with the number of effective digits unchanged, Iol is input into the empty digits. On the other hand, the carry signal 1 is applied to the selection terminals SO to S4 of the data selector 401.
Twelve signals 304-308 are input. With this circuit configuration, as many product signals 1 t as indicated by the carry signal 112'
) 9 (2' to 2-10) is carried and output signal 1
13 (2 to 2). The above is a description of a specific example of the configuration of each circuit.

Next, we will discuss the circuit scale. In this example, 5×
The total number of gates of the circuits added to the 5-bit multiplier 100 (drop circuits 101, 103, carry signal generation circuit 110, carry circuit 111) is about 150. On the other hand 5
×5-bit parallel multiplier has 300 to 400 gates 7×7
It is safe to use a bit parallel multiplier with approximately 700 gates.

Therefore, compared to the method of expanding the multiplier itself from 5×5 to 7×7 bits, the circuit size can be significantly reduced. In particular, it is a very effective circuit for multiplication of one word in which the required number of significant digits is constant and the variation range is large. However, the amount of circuit savings increases as the number of bits of the signal handled increases. As described above, according to the present invention, even when integrating various digital circuits using multipliers into ICs, costs can be reduced by saving circuits.

Regarding the calculation time, the 11j down circuit 102 has a delay of up to 4 games as shown in FIG. 2, and the carry circuit 111 has a delay of 2 games as shown in FIGS. 4 and 5. Since there are two delayed daughters, the time required for calculation in addition to the multiplication time in the 5×5 bit multiplication unit 100 is at most 6 gates. This corresponds to the delay amount for one stage of 1/2 circuits. On the other hand, when expanding 100 stages of multipliers from 5 × 5 to 7 × 7 bits, when ripple-chart addition is used for partial product addition, This results in an increase in the computation time for six stages of full adders. In this way, by performing multiplication exceeding the required number of significant digits, the calculation time increases considerably, and in the above embodiment, the difference is as much as five stages of full adders. This difference increases as the number of focuses increases. Therefore, according to the present invention, effective multiplication time can be shortened and performance can be improved.

Next, the parallel multiplier circuit of the present invention is connected to an ACC (Automatic CoLor Coordinator) that controls the gain of color signals.
An example applied to a (ntrol) circuit will be described in detail.

Conventionally, all signal processing in television receivers has been performed by analog signal processing, but there have been problems that need to be improved, particularly in signal processing after the video stage, as described below. In other words, in terms of performance, it is a problem caused by processing performance on the time axis, which is considered to be a general weakness of analog signal processing.Specifically, it is a problem caused by the processing performance on the time axis, which is considered to be a general weakness of analog signal processing. These include separation performance, various image quality improvement performance, and synchronization performance. On the other hand, there are problems in terms of cost and production, even if the circuit is integrated into an IC, there are many external parts and adjustments.

In order to solve these problems, it is being considered to completely digitalize the signal processing up to the demodulation of primary color signals or color difference signals after the video stage.

By the way, in television receivers, the gain of the color signal is controlled so that the color burst in the color signal always has a constant amplitude in response to changes in the amplitude of the color signal due to the characteristics of the transmission path from the transmitting station to the receiver. An ACC circuit is required. The ACC control procedure is normally as follows.

First, one input color word is multiplied by a signal (referred to as an AC'C signal) for controlling the gain of this signal.

Next, the amplitude of the color burst in the gain-controlled color signal is detected, and an error of 100 degrees, which is the difference between this magnitude and a separately determined target value, is calculated. Finally, pass the error number 1g through an appropriate low-pass filter and send this output to the previous A
Multiplication is performed again with the color signal as the CC signal. By repeating the above operations repeatedly, the gain of the color 1 signal is controlled so that the amplitude of the color burst reaches the target value. This control procedure is the same for digital television receivers.

However, when realizing this operation with a digital circuit, the circuit scale of the multiplier becomes large, and out of the entire ACC circuit,
A considerable portion will be occupied by multipliers. This is due to the following reason.

First, in a digital television receiver, the video signal e A/D! When converting, the sampling frequency fs is fs = 4fsc (fsc is the color subcarrier frequency. For N TSC signal, fsc = 3.58MHz,
, 7'5=14.3fviHz) VC is often set, and therefore the color signal entering the multiplier also has a bit rate of fS, so high-speed multiplication by parallel multipliers is required.

Second, in order to obtain a sufficient variable gain range and precision for the ACC, the word length of the ACC signal input to the parallel multiplier becomes considerably long, which further increases the circuit scale of the multiplier. For example, the input color signal is expressed in two's complement,
The ACC signal is an 8-bit signal with a variation range of +2 to -2 (the minimum quantization step is 2 = 1/128), and the ACC signal is an 11-bit signal with a variation range of 16 to 0 (the same minimum quantization step as the color signal). ), the multiplier is 8
A ×11 bit parallel multiplier is required. This is 11
The other parts of the ACC circuit, which require 00 to 1300 gates, such as the width N width detection circuit, the error calculation circuit, and the low-pass filter, can be constructed with several hundred gates.

As described above, the proportion of multipliers in the ACC circuit is quite high, and reducing this is an important point in realizing a digital ACC circuit. On the other hand, looking at the ACC signal, if the variable range is 16 to 0 as mentioned above, the total number of bits in this range is 11 bits, taking into account the accuracy of ACC, but the value of a certain ACC signal Seven bits is sufficient for the necessary effective number of bits. However, using an 11-bit multiplier tT machine, we can convert this to 1,
Calculation requires calculations with more than the required number of significant digits, resulting in not only an increase in circuit size but also a significant increase in time multiplied by one hour.

The above problem is solved by using the parallel multiplier circuit of the present invention. Hereinafter, an embodiment in which the parallel multiplier circuit of the present invention is applied to an ACC circuit will be described with reference to the drawings.

FIG. 6 is a diagram showing an overview of a digital television receiver.

Television f word 1d received by antenna 601.

The signal is converted into a baseband video signal 623 through a tuner 602, an IF stage 603, and a detection stage 604. The video signal 623 is supplied to a synchronization circuit 606 where the video signal 623 is synchronized and
Regeneration is performed and horizontal and vertical 1-fW e drive pulses 617, 618 are output and supplied to the deflection circuit. Further, the video signal 623 is input to the width conversion circuit 605, where sampling and numberization are performed, and a digital video signal 624 is output. The sampler frequency fs is fs=4fsc1. The sampling phase is synchronized with the horizontal and ±Q axes of the color burst. Templing pulse 615L/i that provides sampling timing
The clock 'Jh is made by the raw circuit 627, and the width conversion circuit 6
05 Digital 1 language processing circuit 622 and synchronization circuit 606
It is used as a standard for circuit operation. In addition, the clock generation circuit 627 includes the +I-axis and +Q-axis components of the sampling link, and the color detection circuit 611.
It is supplied as a detector P/L/7°616 which gives a low axis of color.

The digital video signal 624 is input to the YC separation circuit 607, and is separated into a luminance signal 608 and a color signal 609 by a digital filter. The chromaticity signal 609 is sent to the ACC circuit 61
After the signal is input to 0 and the gain is adjusted, it is supplied to the color detection circuit 611. Note that the synchronous circuit 606 is connected to the ACC circuit 610.
Then, a burst gate pulse 625 indicating the position of the color verse is input. This is the ACC circuit 61
0, it is given to the timing of color burst integration to detect the size of the color burst.

In the color detection circuit 611, the color signal 6 subjected to ACC control is
I and Q fi signals 613 and 614 are obtained, respectively, by selectively extracting the signals of phase 1 and QIlIl11 from 26 using a detection pulse 616.

Luminance signal 608, ■ and Q signal 613°, -, '61
4 is input to the matrix circuit 612 and converted into FL G B j @ number 61'9 by a predetermined matrix operation. This is converted into an analog signal by the D/A converter 620.
It is converted into a B signal 621 and operates the CRT via an output circuit. The above is an overview of digital television receivers. Next, the ACC circuit 610 will be explained in detail.

FIG. 2 is a diagram showing one embodiment of the ACC circuit 610.

The ACC circuit 610 includes a multiplier 701 and a digit shift circuit 702.
, 704 and an arithmetic circuit 703. color signal 60
9 is multiplied by ACC1i number 705 by a multiplier 701 to perform gain control. The color signal 706 is a digit shift circuit 702
Digit shift (power of 2 gain adjustment) is performed based on the digit shift signal 708, and color 1e 626 is output. color signal 6
26 is output to the color detection circuit 611 and simultaneously supplied to the arithmetic circuit 703. The arithmetic circuit 703 detects the size of the color burst in the lust code 626, and then calculates the difference (error signal) between this and the target value of i. The error signal is passed through a low-pass filter (L l) F ) that determines the ACC signal 707.
is outputting. In the digit shift circuit 704, A CCjp
Only the necessary significant digits of No. 3 707 are extracted by digit shifting and output as a new ACC signal 705 to the multiplier 701.

On the other hand, the digit shift information performed here is given to the digit shift circuit 702 as a floor shift signal 708, and digit shift is performed to cancel out the digit shift in the digit shift circuit 704. Therefore, the color signal 626 is the ACC signal 707 with respect to the color signal 609.
The gain is multiplied by the magnitude of .

According to the above control procedure, by appropriately selecting the characteristics of the LPF in the arithmetic circuit 703, it is possible to control the size of the color burst of the color signal 626 to converge to the target value. Here, in order to make the following explanation easier to understand, the digit range and bit number of each signal in FIG. 7 will be summarized below.

As shown in this table, the ACC signal 707 has a variable range of 1
6 to 0, which is the gain control range for the input color signal 609. ACC signal 705 input to multiplier 701
is a signal in which 7 necessary significant digits of the Ace signal 707 (11 bits) are within the range 1-0'. Therefore, if the multiplier 701 inputs the ACCli signal 707 as it is, the multiplier 701 requires only 8×7 bits instead of the 8×11 bits. In addition, the digit shift of the ACC signal 7 ( ) 7 performed by the digit Stυ circuit 704 is
The following process is performed depending on the magnitude of the CC signal 707.

Table-1 This causes the ACC signal 705 to fall within the range of 1-0.

The digit shift circuit 702 performs the opposite digit shift. Next, each circuit shown in FIG. 7 will be explained in more detail.

FIG. 8 is a diagram showing the configuration of the arithmetic circuit 703. The calculation circuit 703 includes a color burst integration circuit 801, an error calculation circuit 802, and an LPF 803. The operation of the color burst integration circuit 801 is as follows.

The gate 804 takes in the color, - burst only during the burst gate pulse 625, and the absolute 1111 circuit 805
, a negative signal is converted to positive. Next, it consists of an adder 806 and a latch 807! Sign. The color burst is integrated by a collapsible divider. Latte 807 Lotus 7 Pull Pulse 6
15 performs a latch operation, and burst gate pulse 625
Output is cleared outside the 0 period. The launch 808 latches the input 1δ at the falling edge of the burst gate pulse 625. Through these circuit operations, the output of the launch 808 can provide the result of the absolute value integration of the burst gate pulse 616 period.

The error calculation circuit 802 converts the integral value 809 into a target value 811.
One error word 812 is created by subtracting from . The LPF 803 lowers the input error signal 812 by 0 digits and performs division by a power of 2.
14 and a latch 815 performs integration. Note that the split'σ device 813 actually only requires wiring operations.

Well, the ACC time constant is 2. ” -Tit (', I'
H: 1 horizontal circumference JiJ] ) Ni ratio '13'! I-suru. A latch operation is performed using the latch 815id and the burst gate pulse 616, and the ACC signal 707 is fully output. Through the above operations, the arithmetic circuit 703 performs the input color 1ii
- This depends on the amplitude of the color burst of No. 626.
Page 1 Direct 811 K Approaching No\CC (Signal 7 (
17" is created. As mentioned above, 7h Ic A CC
The signal 707 is output in the range 23 to 2-7 (ri) and enters the j-row moving circuit 704.

8F! FIG. 9 is a diagram showing the configuration of the i'n movement circuit 704. The digit shift circuit 704 includes seven data selectors 90
1 and a size detection circuit 902.

The configuration of the data selector is shown in FIG. 1O. I) 0~D
One of the five input signals of No. 4 is output to the Y terminal by the selection signal of SO to S4.

In FIG. 9, an input ACC signal 707 is shifted one bit at a time and input to seven data selectors 901. On the other hand, ACC ('g issue 707, 23~
The 20 digit signal is input to the magnitude detection circuit 902, and A
It is detected where the CC signal 707 falls within the size categories shown in Table 1.

FIG. 11 shows a specific configuration of the size detection circuit 902. In the figure, signals of 23 to 2 degrees of ACCf: No. 4 707 are input to terminals a3 to aQ, respectively. ) Due to the constant gate configuration, the size of A CCI No. 4 707 is
However, 16〉A≧8.8) A≧4.4) A≧2゜2>A≧
1.1) Depending on the time of A, terminals Q4, Q3°Q2.
Ql and QO are each at a level of 11'.

Q4 to QO are input as digit shift signals 708 to selection terminals 84 to SO of seven data selectors 901. In the data selector 901, 84, s3. .

82.81. As So becomes 111, the AC'C signal 707 becomes 4 and 3 P(i,
A signal (ACCI code 705) with digits lowered by 2 digits, 1 digit, and 0 digits is output.

Through the above operation, the digits shown in Table 1 are downgraded according to the magnitude of the ACC signal 707, and the number of significant digits of 7 bits is 1 to 1.
While the ACC signal 705 in the range of 0 is output, the digit shift signal 708 is output to the digit shift circuit 707.

FIG. 12 is a diagram showing the configuration of the digit shift circuit 702. The digit shift circuit 702 has seven data selectors 901 (・
4 will be completed.

In FIG. 12, the color signal 7 output from the multiplier 701
06 is the data selector 90 shifted by one pit.
1 is input. On the other hand, the digit shift signal 708 is input to the selection terminals 84 to SO of the data selector 901.
3,82,81. When So becomes "1", the tuna code (color signal 626) in which the color signal 706 is carried up by 04'f1.1 digit, 2 digits, 3 digits, and 4 digits, respectively, is output to the Y terminal. This cancels the digit shift performed by the digit shift circuit 704. The above is an explanation of the operation of the ACC circuit to which the multiplication circuit of the present invention is applied.

Next, the effects of reducing the circuit scale and multiplication time according to the present invention will be explained with reference to the above-mentioned embodiments.

As mentioned above, in the above example, the 11-bit ACC
By adding digit shift circuits 702 and 704 instead of directly converting No. 16 707 to color signal 609 and East' (1),
The 7-bint ACC signal 705 is transformed and multiplied by tζ. Therefore, the multiplier is 8 x 11 bits.
×7 bits is sufficient. This is the ACC circuit 61
The total circuit cost reduction aF is approximately 25 cm.

Regarding calculation time, fd, digit shift circuit 702゜704
The total delay time is 6 gates, which corresponds only to the delay amount of one full adder stage. However, for 8x11 bits and 8x7 bits, when ripple carry addition is used for partial product addition, the difference in calculation time is the full adder 8.
It even reaches a stage.

Therefore, the computation time for seven stages of subtraction and full adders is saved, and a reduction rate of 25% in multiplication time can be achieved.

As explained above, when multiplying an ACC signal whose variation range is large compared to the required number of significant digits, the multiplier input i6:)
Items that exceed the range will be brought within the range by lowering the digits,
By using a circuit system that compensates for this amount by carrying the output signal of the multiplier, it is possible to avoid practically impairing the ACC performance (
It is possible to reduce the circuit size and economic time of ACCl road by about 25 times.

This makes a very large contribution in terms of cost and performance when converting the circuit into an IC.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of a parallel multiplier circuit of the present invention,
Figure 2 is a configuration diagram of the carry down circuit, Figure 3 is a configuration diagram of the carry signal generation circuit, Figure 4 is a configuration diagram of the carry circuit, Figure 5 is a configuration diagram of the data selector, and Figure 6 (d The overall configuration diagram of the digital television. Figure 7 is the overall configuration diagram of the ACC circuit. Figure 8 is the (R configuration diagram) of the arithmetic circuit. Figure 9 is the configuration diagram of the Tsugage circuit. Figure 1O is the configuration diagram of the data selector. , Fig. 11 is a block diagram of the size detection circuit, and Fig. 12 is a block diagram of the carry circuit. 100... Multiplier 102, 103... Carry down circuit 111... Carry circuit Agent Patent Attorney Kensuke Chika (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 10 Figure 11

Claims (1)

[Claims] A parallel digital multiplier that multiplies a plurality of digital signals each having a predetermined number of digits as input, and an excess number of digits for digital signals that exceed the predetermined number of digits among the digital signals input to this digital multiplier. and a carry circuit that carries up the output of the digital multiplier by the total number of excess digits lowered by the carry down circuit. Parallel multiplier circuit.