JPS59117674A - Pattern matching processing system of graphic pattern extracting processing - Google Patents

Abstract

PURPOSE:To improve processing speed by stopping succeeding matching operation to start matching operation to the next dictionary pattern when the degree of disaccord between a sample pattern and a dictionary pattern exceeds a preliminarily determined threshold. CONSTITUTION:A dictionary pattern is preliminarily generated for all logical notational symbols to be extracted to register in dictionary. In case of the automatic extraction of a logical notational symbol, a sample pattern having MXXMY size in the position, extracting the symbol from an input pattern is called and the matching operation to the individual dictionary pattern of said dictionary is performed in accordance with an equation I . In the equation I , Wxy is given by an equation II. When an overall evaluated value E indicated by said equation I exceeds a prescribed threshold which is set for the purpose of absorbing the influence of deformation due to hand-writing or the like, the sample pattern is judged to be not the symbol of the dictionary pattern, and the succeeding matching operation is stopped to start the matching operation to the next dictionary pattern.

Description

Detailed Description of the Invention (4) Technical Field of the Invention The present invention relates to a pattern matching processing method in two-figure pattern extraction processing, and in particular, to a pattern matching processing method in two-figure pattern extraction processing. This invention relates to a pattern matching method when automatically extracting graphic patterns.

(B) Technical Background and Problems Application examples of this technical field include logic notation symbols drawn with reference to predetermined lattice axes, such as logic circuit drawings, and logic notation symbols drawn along the lattice axes. There is a method that automatically extracts the position and shape of a logical notation symbol from a drawing in which wiring patterns between the logical notation symbols and characters that mean the names of the symbols coexist.

As a method for realizing this, the applicant has previously proposed ``Line pattern automatic recognition method J (fi, patent application No. 56-482524).
r pattern matching method J (Japanese Patent Application No. 57-43954
We have made several proposals, including (No. 1). These methods include optically taking a hand-drawn drawing such as the one mentioned above, and compressing this human image information into small rectangular areas centered around the grid points to generate information in the vicinity of the grid points. is encoded, and this compressed code is used to extract logical notation symbols. In these proposals, as will be shown in the examples described later, each rectangular area centered on a lattice point of input image data is verified by a verification circuit.
1) The horizontal and vertical deviations of the image data relative to the grid axis are determined using two verification windows of different sizes. Second
The verification process is performed to detect the direction in which the line pattern exists and the direction in which it is shifted.
A third verification process using a third verification window detects ambiguous information on the normalized image data obtained as a result of the second verification process;
．． Second. The results of the third verification process are integrated to obtain the lattice point label code shown in FIG. 1 for each imaginary lattice. Of the 16-bit divisions in the lattice point label code shown in Figure 1, the 12th to 15th pits indicate the presence or absence of a line pattern in the normalized image data in four directions from the lattice point, namely (lower), left), upper). 0. Represented by giving 1 or 0 corresponding to ■ on the right.

Corresponding to these directions, the shift direction is 3rd to 6th bits,
The ambiguous direction is shown in the 8th to 11th bits.

θth depending on the presence or absence of the ambiguous direction and the misalignment direction.
Seven lags are provided for the bit and the seventh bit.

In accordance with the above proposal, the lattice point label code is tentatively determined as described above, the initial lattice point label code) 1 is processed by handwritten line pattern breakage correction, misalignment correction, ambiguity correction, etc., and each bit is Let the grid point label code resulting from the operation be the input cover pattern. Then, a group of lattice point label codes compiled into a size corresponding to the size of the dictionary pattern at the position where the logical notation symbol will be extracted is taken as a sample pattern, and the sample pattern and the logical notation symbol pattern to be extracted are Using the dictionary pattern in which the 4-way code is registered, a matching operation is performed for each grid point, focusing on the degree of matching J.

The position and shape of logical notation symbols are automatically extracted.

However, when automatically extracting such logical notation symbols, the logical notation symbols have various sizes and are likely to be deformed by handwriting, so it is difficult to make a judgment using matching calculations.

Firstly, since the sizes of each dictionary pattern are different, it is necessary to change the evaluation value of the matching operation according to this size.Secondly, the evaluation value of the matching operation must be changed in order to absorb the influence of deformation. It is necessary to set a threshold for

For this reason, the sample pattern at the position is at most 1
9 even though it only matches one dictionary pattern
Performs matching calculations with individual dictionary patterns until the final stage.

Since the evaluation value is determined based on whether or not it exceeds a set threshold value, it takes an enormous amount of time to perform matching processing with the entire dictionary.

(C) Object and Structure of the Invention The present invention aims to solve the problems in the above-mentioned conventional proposals, and it is possible to quickly determine the mismatch between a sample pattern and each dictionary pattern registered in a dictionary. However, it is an object of the present invention to provide a pattern matching method that can perform matching processing with the entire dictionary at high speed by stopping the matching operation. Therefore, in the present invention, the matching operation is performed by focusing on the degree of mismatch J between the sample pattern and the dictionary pattern registered in the dictionary, and when the degree of mismatch exceeds a predetermined threshold in the calculation process, The subsequent matching calculation for the dictionary pattern is stopped and the matching calculation for the secondary dictionary pattern is started.

(2) Embodiment of the Invention FIG. 2 is an explanatory diagram for explaining the present invention in detail.

FIG. 2 shows a 4-way code for one of the lattice points constituting the sample pattern according to the present invention.
P i corresponds to four-way codes D, L, U, and R of the grid point label code, respectively.

Figure 3 shows the information code for one grid point of the grid points that make up the dictionary pattern according to the present invention, and the 0th to 3rd bits are standard pattern codes and correspond from the grid point as a standard pattern. Whether there should be a line segment pattern in the direction of down (Al), left (Am), up (A3),
The 4th to 7th bits are don't care codes, and the line pattern may or may not exist in the corresponding direction from the grid point as a standard pattern. ), top (Ns).

It is represented by the right (N4). Further, a symbol area flag indicating whether or not the entire grid point is to be subjected to matching calculation is provided at the 9th bit.

FIG. 4 shows an explanatory diagram for explaining dictionary patterns. Figure (a) shows a three-man power A as an example of a logical notation symbol.
ND gate (C) in the same figure shows a region (MX, MY represent the size) and a four-way code pattern that are considered to be affected by the shape of the symbol in (a) of the same figure. In other words, it is a graphical representation of the four-way code for each grid point.

A circle indicates a grid point, a thick line indicates that a line pattern should exist in that direction from the grid point, and a double line indicates that a line pattern may or may not exist in that direction from the grid point (don't care). The direction in which there are no lines indicates that there should be no line pattern. The upper right and lower right parts of the symbol in figure (a) are curved, so the 4
The direction code information is ambiguous, so the
This part of the pattern shown in fL) is a don't care. - towards.

Figure (e) shows a dictionary pattern corresponding to the third column of the standard pattern in figure C). Further, the size of the dictionary pattern of this symbol is MxXMy.

As described above, dictionary patterns are created for all logical notation symbols to be extracted and registered in the dictionary.

In automatic extraction of logical notation symbols, MxXMy
A sample pattern with a size of is called, and a matching operation with each dictionary pattern in the dictionary is performed according to the following equation. Let us now assume that the overall evaluation value of the symbol is E.

Here, the evaluation value W□ of the -lattice stippling pattern is given as follows based on the four-way code P of the input pattern shown in FIG. 2, the standard pattern A shown in FIG. 3, and the don't care code N. It will be done.

The evaluation value W2v of this lattice pointillism takes the minimum value "0" when all the four-way codes of the sample pattern and the dictionary pattern match, and takes the maximum value "4" when they all do not match. The overall evaluation value E is expressed as the sum of the evaluation values of all grid points within a region considered to be influenced by the shape of the symbol. A threshold value is set for this overall evaluation value E in order to absorb the influence of deformation due to one handwriting, etc., and if it is less than this threshold value, it is determined to be a symbol. Therefore, in the present invention, if the overall evaluation kE exceeds this threshold value during the matching calculation process, it can be determined that the sample pattern is not a symbol of the dictionary pattern, and the subsequent matching calculation is stopped and the first-order Starts matching operation with dictionary pattern. Finally, as a result of performing a matching operation with all dictionary patterns, the one with the smallest overall evaluation value E is extracted as a symbol with the shape of that dictionary pattern at the position where the sample pattern is recalled from the input pattern. It means that it was done. Also.

It did not match all dictionary patterns. If all of the overall evaluation values E exceed the threshold, it means that no symbol exists at that position.

FIG. 5 is a block diagram of an embodiment of the invention according to the principles described above.

In the figure, two handwritten drawings are read by an image input device 1 and two image data are stored in an image memory 2. The input state of the reference point of the drawing is detected by the reference point detection circuit 4 from the image data stored in the image memory 2, and the address of each grid point corrected based on the input distortion is stored in the grid point table 5. be done.

Next, the control unit 11 reads partial image data of size 2×2 between the grid axes from the two-image memory 2 based on the address obtained from the grid point table 5, and converts it into the grid conversion circuit (horizontal ) 6 and the grid conversion circuit (vertical) 8, and the resulting information is transferred to the grid point label code generation circuit (horizontal) 7 and the grid point label code generation circuit (
vertical) 9 to generate an initial lattice point label code LBO, which is stored in the LBO table 13.

In accordance with this initial grid point label code LBO, a first verification window of a predetermined size is set by the verification window setting circuit 12,
Using this, the verification circuit 3 performs the first verification process. The first verification deviation information SXI and SYI obtained as a result is SX1
- Store in the SYI table 16.

The first verification deviation information SXI obtained in this way.

After converting and normalizing the lattice point address of the lattice point table 5 based on SYI by the address conversion circuit 18, the lattice conversion circuit (horizontal) 6 and the lattice conversion circuit (vertical) 8 are again used to generate a lattice point label code. A first verification label code LBI is obtained by the circuit (horizontal) 7 and the grid point label code generation circuit (vertical) 9, and is stored in the LBI table 14. Based on this first verification label code LBI, the verification window setting circuit 12 sets a second verification window of a predetermined size.

Using this, the verification circuit 3 performs a second verification process.

The second verification deviation information SX2 obtained as a result. SY2 is stored in the SX2/SX2 table 17.

Second verification deviation information SX2゜SX obtained in this way
After the address conversion circuit 18 converts and normalizes the lattice point address obtained from the lattice point table 5 according to 2, the second verification label code LI2 is obtained in the same manner as described above, and this is
0 to be stored in the B2 table 15 Next, to check the detailed figure state near the lattice points.

A third verification window is set by the verification window setting circuit 12, and the third verification window is set by the verification window setting circuit 12.
．． Similar to the second verification process, the verification circuit 3 performs a third verification process. The information obtained as a result is sent to the LB3 generation circuit 19 to obtain the third verification label code LB3.
Contains 20 B3B3 tables.

Then, the initial grid point label code LBO, LBI table 1 from the LBO table 13 obtained through the above processing.
The first verification label code LBI from 4.

L] 32 Second verification label code LB from table 15
2. Third verification label code L of LB3B3 table 20
B3. The first verification deviation information SXI, SYI from the SXI/SYI table 16 and the second verification deviation information SX2°SX2 from the SX2/SX2 table 17 are integrated in the lattice point label code determination circuit 21.

The resulting grid point label code is stored in the label code table 22.

For the lattice point label codes from the label code table 22, a pair processing circuit 23 performs processing to remove the four-way codes between lattice points that are not paired, and a line pattern breakage correction circuit 24 The pattern breakage is corrected, and the one-character removal circuit 25 removes those in which the relationship between grid points has character characteristics.The primary deviation correction circuit 26 and ambiguity correction circuit 27 correct the deviation flag, deviation direction, and ambiguity of the grid point label code. These corrections are made between grid points depending on the state of the flag and the opposite direction.

The lattice point label codes corrected by the correction circuits 23 to 27 are stored in the label code table 22 again.

Next, the four-way code shown in FIG. 2 is called as a sample pattern from the label code table 22 and inputted into the symbol extraction circuit 29, while the standard pattern codes A1 to A4 shown in FIG. 3 are read from the dictionary memory 28, don't care code Nl -N4, a dictionary pattern consisting of the symbol area flag S is input into the symbol extraction circuit 29. Here, sequential matching calculations are performed using both equations (1) and (2), and the position of the extracted symbol and its shape are stored in the symbol recognition table 30.

■Detailed Description of the Invention As described in detail, according to the present invention, in a large number of sequential matching operations between a sample pattern and a dictionary pattern, the matching process with the entire dictionary is performed at high speed by focusing on the degree of mismatch between two patterns. can be executed.

Further, according to the present invention, even if a part of a symbol includes a curved line or diagonal line, the dictionary pattern itself is configured to tolerate ambiguity in this part.8 Normally, dictionary patterns that are very similar to each other are not registered in the dictionary. For this reason, formula (1),
As a result of matching the sample pattern and the individual dictionary patterns in (2), if the overall evaluation value E is 'θ'' and A, it is possible to determine which symbol the sample pattern is at that point. The subsequent matching calculation with the dictionary pattern can be omitted, and even faster matching processing becomes possible.

[Brief explanation of drawings]

Figure 1 shows the lattice point label code, Figures 2 and 3 show the sample pattern and dictionary pattern for each lattice point that is subject to matching operations, Figure 4 (a) shows an example of a logical notation symbol, and C) in the same figure shows An example of a standard pattern based on the information compression, and FIG. 3(c) is an example of the dictionary pattern. FIG. 5 shows block diagrams of embodiments of the present invention. In the figure, 1 is an image input device, 2 is an image memory, 3 is a verification circuit, 4 is a reference point detection circuit, 5 is a grid point table, 6 is a grid conversion circuit (horizontal), and 7 is a grid point label code generation circuit ( 8 is a grid conversion circuit (vertical), 9 is a grid point label code generation circuit (vertical), 10 is an address control unit, 1
1 is the control section. 12 is a verification window setting circuit, and 13 is an LBO table. 14 is the LBI table, 15 is the LB2 table. 16 is SX1/SYI table, 17 is SX2/SY2
18 is an address conversion circuit, 19 is an LB3 generation circuit, 20 is an LB3B3 table 1 is a lattice point label code determination circuit, 22 is a label code table, 23 is a pair processing circuit, 24 is a line pattern breakage correction circuit, 25 is a character 26 is a deviation correction circuit, 27 is an ambiguity correction circuit, 28 is a dictionary memory, 29 is a symbol extraction circuit, and 30 is a symbol recognition table. Patent applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hirona 1 person) Junior high school student 1m > 2 figure age 31? Figure 4 (a'I (-&) (C)

Claims (1)

[Claims] In order to automatically extract the location and shape of a specific graphic pattern from an image, the entire image is divided into two-dimensional small area units and compressed coded information is used as the input pattern. The dictionary pattern of the figure pattern at the position where two figure patterns are extracted is constructed by combining the standard pattern obtained by compressing the information in small area units and the pattern that allows ambiguity. In the pattern matching processing method in the shape pattern extraction process, the sample pattern is sequentially matched with the dictionary pattern using the compressed code group corresponding to the size as the sample pattern. and the dictionary pattern to extract the degree of mismatch between the two patterns, and in the process of the calculation, it is determined that the degree of mismatch between the two patterns exceeds a predetermined evaluation threshold. 1. A pattern matching processing method in figure pattern extraction processing, characterized in that subsequent matching calculations for the dictionary pattern are stopped and matching calculations for a secondary dictionary pattern are started.