JPS59117329A - Offset compensating cmos inverter circuit and method of compensating same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention relates generally to semiconductor integrated circuits and, more particularly, to an improved complementary metal-oxide half body (0MO8) inverter circuit.

In many applications, such as switched capacitor analog-to-digital converters, it is desirable for the switching voltages of cooperating inverters to vary over a narrow range to suit a wide range of operating conditions. However, the level of input voltage at which a CMOS inverter switches varies widely depending on temperature changes and the characteristics of the devices involved and the supply voltage of the inverter. In other applications, transistor-transistor logic (TTL)
It would be desirable to provide a low power high speed inverter with an input compatible with VC and an output compatible with MO8.

Therefore, the present invention provides a compensated high speed inverter compatible with TTL input and 0MO8 output.

In a first embodiment using CMO8) transistors, two compensation circuits are connected to the outputs of the two transistor inverters. Each compensation circuit is formed from a compensation transistor that is substantially identical to a corresponding transistor of the inverter transistor.

The dates of the compensation transistors are biased to the desired inverter input switching voltage and the drain of each compensation transistor is connected to a 1:1 current mirror circuit. The output of this circuit is connected to the inverter output. Therefore,
The compensation circuit generates a current of equal magnitude and opposite polarity to the drain current of the inverter transistor. The current generated in the compensation circuit therefore cancels out the drain current of the inverter transistor at a predetermined switching voltage.

In the second embodiment, the TTL compatible input switching voltage is
The inverter and mirror transistors are generated by biasing the compensation transistor at the level
The output switching voltage is selected to also be compatible with 0MO8 devices.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1 Referring now to the drawings, a first embodiment implemented in an 0MO8 device in accordance with the present invention is shown in FIG.

Transistors M1 and M2 form the basic inverter. In this, the inverter input is Ml-M2/7'
The inverter output is Ml-M
2 drain interconnect. The source of Ml is connected to the supply voltage ■, and the source of M2 is connected to ground.

The output currents of transistors M and 114, whose dates are connected together and their respective sources are connected to the voltage supply, form a 1:1 current mirror circuit, and from the drain of M4 in the circuit. is equal to the input current σ) from the drain of M3. The drain of M4 is connected to the output of the inverter. The drain and date of M3 are connected to the drain of M5n. This 17”1M,
5 (7") source is connected to ground. The date of M5 is connected to a voltage divider circuit formed from transistors M6 and M8. Similarly, transistors M9 and M
The 10n source is connected to ground and the dates are connected together thereby forming a 1:1 current mirror circuit. The drain of Mlo, which is the output of this mirror circuit, is
Furthermore, it is connected to the inverter output. The gate and drain of M9 are connected to the drain of transistor M7,
The source of l is connected to the voltage supply and M70 case-1-
is connected to the M6-M8 voltage divider at the same point as the gate of M5.

The voltage on M5 and Ml r-) is the inverter switching voltage, ie, when the inverter input voltage exceeds this voltage point, the voltage at the output of the inverter changes state. When the inverter voltage is initially at a high potential level and drops to a voltage below the switching point, the inverter output switches from a low level to a high level. Conversely, if the inverter voltage passes through a switching point while changing from a low level to a high level, the inverter output switches from a high level to a low level.

In the circuit of Figure 1, the switching point, which is /2, can be set by configuring transistors M6 and M8 substantially identically so that it lies at the node between the drain of M6 and the source of The voltage will be approximately V/2. This is also the date voltage of M5 and Ml. M5 and Ml
The physical dimensions of are chosen to be substantially equal to the dimensions of M2 and Ml, respectively, so that the drain currents of M5 and Ml are the same as those of M2 and M1 that flow when the input voltage exceeds the switching point or It becomes equal to the amount of drain current of Ml. Therefore, M5's drain 't style &':! ,M
The drain current of M2 is made into a mirror output by the drain current of M2, so that a current of the same magnitude but opposite to the drain current of M2 is output. The drain current of M4 cancels the drain current of M2 at the inverter output node. Similarly, the drain current of Ml, which is equal to the drain current of M1, is reversed in polarity by the drain current of Mlo, with the current remaining unchanged, and the drain current of Ml is canceled out by the output current. Furthermore, the desired switching point, which is the inverter output stripe Ml2, is compensated. Furthermore, the switching point changes only slightly over large changes in temperature, supply voltage, transistor voltage, and threshold voltage.

FIG. 2 is a second example of an inverter according to the present invention that is compatible with TTL input and C1, AO3 outputs. TTL circuits typically operate within the 0.8-2.0 volt range. The desired switching voltage at the inverter input is therefore the midpoint of this range, or 1.4 volts.

The voltage (MS and M7r) is therefore set to 1.4 volts. This 'voltage is connected to an additional transistor M11 of appropriate size wired in series between M6 and MS as shown in FIG.
and Ml2.

The desired gate or bias voltage is generated at the source of the MS. Given a supply voltage of 5 volts, a very close approximation of the desired bias voltage, say Ml4, or in other words about 1.25 volts, can be obtained using transistors of the same size M6° Mll, Ml2 . By selecting MS, you get Burn. Ml, which is the same as M3, M2. The size of M4 is approximately V/2 or 2.0 mm to fit the input of the subsequent CMO8 circuit.
5 volts [output switching voltage is selected so that it is maintained.

With a switching voltage of 2/V, the inverter of the present invention is advantageous for use in switched capacitor analog/digital converters, for example, to stabilize the voltage during switching.
Since charge transfer can be compensated, accuracy can be improved. It will be clear to those skilled in the art that the present invention can be operated as a high speed comparator circuit in which the voltage at the input of the circuit is compared to the bias voltage of MS-M7.

As described above, the switching voltage of 0MO8 can be stabilized at a predetermined voltage level by using a compensation circuit that cancels the cross-current at the drain of the inverter transistor to a desired voltage level. By removing the offset voltage in this way, operational accuracy is improved and speeding up is possible. Additionally, the circuit of the present invention has low power consumption and is compatible with TTL inputs and 0MO8 outputs, so a wide range of applications is anticipated.

Other embodiments and modifications of the invention will become readily apparent to those skilled in the art from the following description and the description shown in the accompanying drawings. Therefore, the present invention is not limited to the description herein, and it is not intended that the above-mentioned modifications and embodiments be included within the spirit of the appended claims &i1. It's obvious.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a CMOS inverter circuit according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a TTL compatible inverter according to a second embodiment of the invention. Agent Akira Asamura

Claims (1)

[Scope of Claims] (1) An inverter means for generating an output voltage of (i) opposite to the input voltage, and an output current of the inverter means connected to the output of the inverter means with a predetermined σ of the inverter means. and means for generating a current that counteracts the input switching voltage level. (2) a first active device in which said circuit is connected to a second active device;
and having an active element connected to the output of said first and second active devices to conduct a current in said predetermined amount equal to and opposite in polarity to the absolute value of the current flowing through said first and second active devices. 2. A circuit according to claim 1, further comprising said compensation means occurring at a voltage level. 3. The circuit of claim 2, wherein said circuit includes means for biasing said compensating means at a '1L voltage approximately equal to said predetermined voltage level. (4) In the above circuit, the compensation means is the first
and a first having an output connected to an output of the second force active device.
and a current source R connected to the input of the first current source so that the current through the third active device R increases to the current through the first active device R at a predetermined voltage level. a 20' trough source having substantially the same third active element and an output connected to the output of the 10' slewing source; 4, wherein the current through the fourth active device is approximately equal to the current through the second active device at the predetermined voltage level.
term circuit. 5. The circuit of claim 4, wherein said biasing means includes voltage dividing means connected to said sixth and fourth active devices. (6) In the circuit, the first, second, third, and fourth active devices, the first and second current sources, and the voltage dividing means include complementary metal oxide semiconductor devices. Fifth apex circuit. (7) a second MOS inverter means for generating an output voltage of opposite polarity relative to the input voltage; a first MOS transistor having an r-t and a drain connected to the date and drain of the transistor; In the inverter means having the first and second MOS transistors, the dates of the first and second MOS transistors form a power supply, and the first and second MOS transistors
OS) said drain of said transistor is connected to said inverter means and said inverter means power output forming an output of said inverter means, said first MOS) transistor being connected to said inverter means output to form an output of said inverter means; A circuit comprising a first compensating means for generating a current equal to and opposite in polarity and means for biasing said first and said second compensating means. (8) A first circuit in the circuit having an output connected to the output of the inverter means.
and a sixth MOS connected to the input of the first current source)
8. The circuit according to claim 7, comprising a transistor. 19) In the above circuit, the second compensation circuit has a second current source having an output connected to the output of the inverter means, and a fourth transistor connected to the input of the second current source. The circuit according to claim 8. (10) In the above circuit, the means for applying the bias includes voltage dividing means connected to the dates of the sixth and fourth MOS transistors. ■ In the above circuit, the first, second, third and fourth
11. The circuit of claim 10, wherein the MOS) transistors include complementary MO8) transistors. (12) In the above circuit, the first current source is a fifth MOS transistor having a date and a drain connected to the drain of the fifth MOS transistor. connected tl
12. The circuit of claim 11, further comprising a sixth transistor having a drain connected to the output of said inverter means. 03) In the above circuit, the second current source is connected to the fourth MOS;) a seventh MOS having a date and a drain connected to the drain of the transistor; a) a transistor and the seventh MOS; 13. The circuit of claim 12, further comprising an eighth MOS transistor having an r-gate connected to the output of said inverter means and a drain connected to the output of said inverter means. (14) In a method for compensating the output of an inverter circuit including first and second active devices, at a predetermined input voltage of the inverter, the first active device is equal to and opposite in polarity to the absolute amount of current flowing through the first active device. 1
generating at the output of the inverter circuit a second compensation current equal to and opposite in polarity to the absolute amount of current flowing through the second active device at the predetermined input voltage; ' The above method comprising the steps of: