JP3206365B2 - Signal input / output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a signal input / output circuit for transmitting a signal between circuits operating at different power supply voltages.

[0002]

2. Description of the Related Art At present, a semiconductor integrated circuit (IC) having a power supply voltage of 5 V is used in many electronic devices, but an IC operating at a lower voltage (3 to 3.3 V) may be used. It is increasing.

For example, an IC operating at 3 V has an I
Consider a case where an external signal (potential 0 V to 5 V) from C is applied. In this case, the output transistor (transistor provided between the 3V power supply circuit and the output terminal) constituting a part of the output circuit in the 3VIC is supplied with its own power supply voltage of 3V when the signal potential is 0V, and there is no problem. . However, when the external signal potential is 5 V, the output transistor is supplied with the opposite polarity with a potential difference of 2 V (= 5 V-3 V).

[0004]

In order to prevent a leakage current due to the applied voltage (2V) of the reverse polarity power supply from flowing into the output circuit, a depletion type auxiliary MOS transistor whose gate is clamped at 3V is connected to a 3V power supply circuit. And an output circuit terminal. However, in such a case, if the variation of the gate threshold value Vth (pinch-off voltage Vp) that determines the boundary between conduction and non-conduction of the depletion type auxiliary MOS transistor is not kept small, the following problem occurs.

(1) In the case of depletion type field effect transistors having the same structure, the smaller the pinch-off voltage Vp, the smaller the mutual conductance gm. Generally speaking, a transistor having a small transconductance gm has a relatively large internal resistance when conducting, and the voltage drop between its drain and source also increases.

If the pinch-off voltage Vp is too small due to variation, a low gm depletion type transistor (large internal resistance during conduction; that is, large voltage drop)
Exists between the 3V power supply circuit and the output circuit,
There is a possibility that the signal amplitude that can be extracted from the output circuit of the 3V operation becomes insufficient.

(2) If the pinch-off voltage Vp becomes too large due to variation, there is a possibility that the depletion type auxiliary MOS transistor cannot be cut off when 5 V or more is applied to the output terminal. Leakage current flows into the circuit.

(3) While ensuring a sufficient output signal amplitude (for example, an output amplitude of 2.4 V or more with respect to a power supply voltage of 3 V ± 0.3 V), an external high voltage signal (for example, 5 V ± 0.3 V) is applied to an output terminal. 5V) is applied, the above-mentioned depletion type auxiliary MO
The allowable variation range of the pinch-off voltage Vp (threshold Vth) of the S transistor must be set extremely small.

(4) Minimizing the variation in the pinch-off voltage Vp (threshold value Vth) of the depletion type auxiliary MOS transistor means that the margin of the manufacturing process of an IC including this transistor is reduced, and Yield is reduced. That is, the manufacturing cost of this IC increases.

An object of the present invention is to provide a signal input / output circuit capable of obtaining a sufficient output signal amplitude irrespective of variations in the threshold value Vth (pinch-off voltage Vp) of the auxiliary MOS transistor and capable of sufficiently suppressing the leak current. It is to provide.

[0011]

In order to achieve the above object, a signal input / output circuit according to the present invention has a first potential (+3.3).
V) a drain-source circuit is inserted between the first power supply circuit (Vdd) and the output circuit (18), and a depletion-type field-effect transistor (auxiliary MOS transistor 10) whose gate is supplied with a control potential (VR); A second power supply circuit (Vss) of a second potential (0 V) and the output circuit (1);
8) a switch transistor (16) inserted between
And when the absolute value (4.8 V) of the potential (Eo) of the output circuit (18) is greater than the absolute value (3.3 V) of the first potential, the depletion type field effect transistor (10). Control potential changing means (22) for changing the absolute value of the control potential (VR) in the decreasing direction (from 3.3 V to 2.7 V); and changing the control potential (VR) by the control potential changing means (22) Speeding means (24) for increasing the speed.

[0012]

When the potential of the output circuit is between the first potential and the second potential (0 to +3.3 V), the control potential (VR) becomes a predetermined potential (+3.3 V). Set. When the potential (+ 4.8V) of the output circuit (18) exceeds the predetermined potential (+ 3.3V), the control potential (VR) is lower than the predetermined potential (+ 3.3V) (+2. 7V). Thereby, the depletion type field effect transistor (1)
The gate-source voltage of 0) is biased in a direction in which cutoff is easy. When the transistor (10) is completely cut off, a leak current flowing from the output circuit (18) to the transistor (10) side is suppressed.
At this time, the speed of changing the control potential (VR) by the control potential changing means (22) is increased by the speed-up means (24).

Here, the gate threshold value Vth (pinch-off voltage V
Even if p) varies to a large extent, the control potential (VR) can be changed with a large variation width enough to absorb the variation width, so that the manufacturing process margin of the depletion type field effect transistor 10 is increased. Can be.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A signal input / output circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic configuration of a signal input / output circuit according to one embodiment of the present invention. Signal transfer between this circuit and an external circuit (not shown) is performed via the I / O pad 18.

The I / O pad 18 is a depletion type N
Connected to the source of channel auxiliary MOS transistor 10. The drain of the transistor 10 is connected to a conductive circuit (M
It is connected to a first power supply circuit Vdd of a first potential (for example, +3.3 V) via a switching element 12 such as an OS transistor. I / O pad 18 also has a conductive circuit (M
It is connected to a drain of a switch transistor (enhancement type N-channel MOS transistor) 16 via an OS transistor (eg, an OS transistor) 14. The source of the transistor 16 is connected to a second power supply circuit V of a second potential (for example, 0 V).
Connected to ss.

The gate of the switch transistor 16 has
A signal Ei from an internal circuit (not shown) is input. A signal Eo obtained by inverting the signal level of the input signal Ei is output from the source of the transistor 10 to the I / O pad 18.

The gate of the depletion type transistor 10 has a first power supply circuit Vdd and a second power supply circuit Vss.
From the comparator 22 fed by the control potential VR
Is applied. This comparator 22 has a reference potential Vr
ef (for example, +3.9 V) and the comparison potential Vcomp (=
(The potential of the output Eo of the I / O pad 18). When the comparison potential Vcomp is lower than the reference potential Vref, the comparator 22 applies a high potential (+3.3 V) control potential VR to the gate of the transistor 10, and when the comparison potential Vcomp is higher than the reference potential Vref, the low potential ( +2.7 V) is applied to the gate of the transistor 10.

The depletion type transistor 10 has a unique gate-source voltage (pinch-off voltage Vp) that indicates a limit to complete cutoff. The pinch-off voltage Vp (for example, 2 V) in the depletion type transistor corresponds to the gate threshold voltage Vth in the enhancement type transistor. That is, in the depletion type, the pinch-off voltage V
When the reverse bias is applied at p or less, the drain-source conducts, and in the enhancement type, the drain-source conducts when the gate-source is forward-biased at the gate threshold voltage Vth or more.

The signal level of the output signal Eo (0 V to +3.
3V) does not exceed the reference potential Vref (+3.9 V) (Vref> Vcomp), the control potential VR output from the comparator 22 is +3.3 V. Then, the depletion type transistor 10 is always in a conductive state without being reverse-biased at the pinch-off voltage Vp (2 V) or more. Therefore, the power supply Vdd
The maximum signal level of output Eo (+3.3) due to the interposition of transistor 10 between
V) does not substantially decrease.

It is to be noted that the depletion type transistor 10 which is biased below the pinch-off voltage Vp and is in a conductive state is turned on.
In order to suppress the “variation” upper limit value of the conduction resistance (drain-source internal resistance) of the transistor 10, the design center value of the transconductance gm of the transistor 10 is set to be relatively large. As a result, the variation center value of the pinch-off voltage Vp also shifts in a slightly larger direction (in this case, the center value of the pinch-off voltage Vp is assumed to be 2 V). For this reason, in order to completely cut off the transistor 10, it is necessary to reliably reverse-bias the gate-source between the gate and the source at a pinch-off voltage that is slightly larger than the pinch-off voltage. A means for satisfying this requirement is switching control of the gate control potential VR by the comparator 22, which will be described below.

That is, the I / O pad 18 is supplied from an external circuit.
When a high-level signal (for example, + 5V = Vcomp> Vref) exceeding the reference potential Vref (+3.9 V) is applied to the N-channel M, the depletion type N-channel M
Control potential V applied to the gate of OS transistor 10
R drops from + 3.3V to + 2.7V.

As described above, when the gate control potential VR is lowered, a high-level external signal (+5) is applied to the I / O pad 18.
V) is applied, the voltage between the gate and the source of the depletion type transistor 10 is 5V-2.7V = 2.3V.
(This is a pinch-off voltage Vp = 2 V or more) and is reverse-biased to completely cut off. With this cutoff,
Leakage current is prevented from flowing from the I / O pad 18 (+ 5V) to the power supply Vdd side via the transistor 10.

If the gate control potential VR is +3.3
Assuming that the voltage remains at V, the depletion type transistor 10 is reverse-biased at a gate-source voltage of 5V-3.3V = 1.7V, and this reverse bias voltage 1.7V is pinch-off of the transistor 10. Voltage Vp =
Since the voltage is 2 V or less, the transistor 10 cannot be completely cut off, and a leak current may flow from the I / O pad 18 (+5 V) to the power supply Vdd via the transistor 10.

In the above configuration, the pinch-off voltage Vp of the depression type transistor 10 is, for example, 1.8 V
Even if it fluctuates to 2.2V, the gate control potential VR
Is switched to +2.7 V to provide a reverse bias of 2.3 V (this is the upper limit of the variation of the pinch-off voltage Vp 2.2).
V is secured, the transistor 1
0 can be completely cut off, and the leak current can be completely suppressed.

By applying a large change to the gate control potential VR so as to cover the variation of the pinch-off voltage Vp of the depletion type transistor 10,
The output Eo of a sufficient signal level (Vdd level) is obtained without being affected by the variation of the pinch-off voltage Vp of the transistor 10, and at the same time, the leakage current flowing from the outside to the inside via the I / O pad 18 is reduced. Can be suppressed.

In the embodiment of FIG. 1, the signal state of the I / O pad 18 (3.3 V output or 5 V input) is determined by the comparator 2.
2 and the control potential V according to the detection result.
R is switched.

That is, the comparator 22 in this embodiment operates at the potential of the I / O pad 18 (comparison potential Vcom).
p) and a predetermined reference potential Vref, and Vref ≧
In the case of Vcomp, a gate control potential VR of the same potential as Vdd (+3.3 V) is applied to the gate of the depletion type N-channel MOS transistor 10. Also, comparator 2
2 is that if Vref <Vcomp, the potential is Vdd-α (+
(2.7 V) is applied to the gate of the transistor 10.

The control potential VR of the comparator 22
In order to increase the switching speed, a VR switching speed-up unit 24 is provided (details of the VR switching speed-up unit 24 will be described later with reference to FIG. 2).

Now, it is assumed that reference potential Vref is set to + 3.9V. Then, when the circuit of FIG. 1 supplies the output Eo (maximum +3.3 V) corresponding to the input Ei from the internal circuit to the I / O pad 18 (Vref> Vc)
omp), a gate control potential VR of +3.3 V is applied to the gate of the transistor 10. In this case, since no reverse bias is applied between the source and the gate of the depletion type transistor 10 at the pinch-off voltage Vp (2 V) or more, the transistor 10 is in a conductive state and the I / O
From the pad 18, a signal output Eo of a maximum of +3.3 V can be obtained.

On the other hand, the output circuit of FIG.
5V) from the I / O pad 18 (Vre
f <Vcomp) is a gate control potential VR of +2.7 V
Is applied to the gate of transistor 10. in this case,
The reverse bias is applied between the source and the gate of the depletion type transistor 10 at a voltage (5-2.7 = 2.3 V) or higher than the pinch-off voltage Vp (2 V), so that the transistor 10 is completely cut off and the I / O pad The leakage current to the 18 power supply circuit Vdd side substantially stops flowing.

The change speed of the gate control potential VR corresponding to the change of the comparison potential Vcomp is determined by the VR switching speed-up unit 2.
4 speeds up. Due to this increase in speed, when a +5 V signal is applied to the I / O pad 18 from an external circuit, the control potential VR is immediately changed (with little delay) from +3.3 V to +3.3 V.
The voltage is switched to 2.7 V (the details will be described in the description of FIG. 2).

FIG. 2 is a circuit diagram embodying the configuration of FIG. In this embodiment, the conductive circuit element 12 of FIG. 1 is configured by an enhancement type P-channel MOS transistor 12, and the conductive circuit element 14 of FIG. 1 is configured by an enhancement type N-channel MOS transistor 14. A positive-phase input + Ei is applied to the gate of P-channel MOS transistor 12, and a negative-phase input -Ei is applied to the gate of N-channel MOS transistor 16. These transistors 12 and 16 constitute a complementary MOS (CMOS) inverter.

The comparator 22 shown in FIG. 1 comprises enhancement-type MOS transistors 221 to 227 in FIG. That is, the depression type auxiliary M
Output Eo from the source of OS transistor 10 is applied to the gate of N-channel MOS transistor 221.
The drain of the transistor 221 is connected to the + 3.3V first power supply circuit Vdd. The source of transistor 221 is connected to the gate and drain of N-channel MOS transistor 222. The substrate of the transistor 221 is connected to the source and the substrate of the transistor 222, and the source of the transistor 222 is connected to the drain of the N-channel MOS transistor 223. The gate of the transistor 223 is connected to the first power supply circuit V
dd.

The output Eo is connected to the source of the transistor 222.
A potential (PG) that changes in response to the above appears. This source is connected to the gate of P-channel MOS transistor 224 and the gate of N-channel MOS transistor 225. The drain of the transistor 224 is connected to the drain of the transistor 225. The source of transistor 224 is connected to first power supply circuit Vdd, and the source of transistor 225 is a P-channel MOS transistor 226.
Connected to the source. The source of the transistor 223 is also connected to this source.

The reference potential Vref for comparison is applied to the gate of the transistor 226 from the reference potential generating circuit 30. The drain of the transistor 226 is an N-channel M
Connected to the drain of OS transistor 227. Transistor 227 has a gate connected to first power supply circuit Vdd, and a source connected to second power supply circuit Vss. Transistors 224 and 225 form a CMOS inverter, invert the level of its input (PG), and output gate control potential VR.

The VR switching speed-up section 24 is constituted by a MOS capacitor 240. The gate of the MOS capacitor 240 is connected to the source circuit of the depression type MOS transistor 10 (circuit to the I / O pad 18 in FIG. 1). Also, the drain, source and substrate rates of the MOS capacitor 240 are determined by CMO
It is connected to the input (PG) circuit of the S inverter (224 + 225). The level change portion of the comparison potential Vcomp is time-differentiated by the MOS capacitor 240, and the result of the differentiation is added to the gate control potential VR via the CMOS inverter (224 + 225).

The comparison reference potential Vre is supplied to the comparator 22.
The reference potential generating circuit 30 for giving the f is connected to an enhancement type N-channel MOS transistor 301 connected in series.
To 304 and an enhancement-type P-channel MOS transistor 305 to 306. In this voltage dividing circuit, the transistor 30
A reference potential Vref (for example, +2.1 V) obtained by dividing the voltage of 3.3 V of the first power supply circuit Vdd is obtained from the connection point between the source 1 and the drain / gate of the transistor 302.

In FIG. 1, the comparator 22 is considered as a symmetrical operation input type, but in FIG. 2, the comparator 22 is configured as an asymmetrical input type. Therefore, in the embodiment of FIG. 2, the value of the reference potential Vref (+2.1 V) is different from the reference potential Vref (+3.9 V) of FIG.

Now, assuming that the gate threshold of the transistor 223 whose gate potential is fixed to Vdd is Vth223 and the gate threshold of the transistor 226 is Vth226, the reference potential Vref is Vdd-Vth223-Vth
226. Vth223 = Vth226 = 0.6V
Assuming that Vdd = + 3.3 V, Vre
f = + 2.1V. Transistors 221 and 22
Assuming that both the gate thresholds Vth of V.2 are 0.6 V, the source potential of the transistor 223 becomes Vref + Vt
Since h223 = + 2.7 V, the transistor 221
Has a gate potential (Vcomp) of +3.9 V (= 2.7 V +
If it is more than (0.6V + 0.6V), the transistor 221 turns on, and if it is less than + 3.9V, the transistor 221 turns off.

Under the above assumption, when the output Eo is at a low level (Vcomp = 0 V <+3.9 V) or a high level (Vcomp = + 3.3 V <+3.9 V) in the 3.3 V operation, the transistor 221 is turned on. Off, transistor 2
24 is turned on, and the control potential VR becomes Vdd = + 3.3V.

On the other hand, when the output Eo is at the high level (Vcomp = + 5 V> +3.9 V) in the 5 V signal system, the transistor 221 is turned on, the transistor 225 is turned on, and the control potential VR is the source potential of the transistor 223. + 2.7V.

In the above configuration, the transistor 224
And the control potential VR (+) that changes according to the potential of the output Eo from the drain of the transistor 225 to the gate of the transistor 10.
(3.3V or + 2.7V).

Here, the depletion type N-channel MO
The pinch-off voltage Vp of the S transistor 10 is set to 2V,
The variation tolerance is ± 0.2 V (± 10 V for 2 V).
%), The following description will be made.

When the source potential of the depletion type transistor 10 (potential of the I / O pad 18 in FIG. 2) becomes +5 V, the gate control potential VR of the transistor 10 whose pinch-off voltage Vp is 2 V ± 0.2 V decreases to +2.7 V. ,
5V-2.7V between the gate and source of transistor 10
= 2.3 V reverse biased. According to the above assumption, the pinch-off voltage Vp of the transistor 10 is at most 2.2.
Therefore, the transistor 10 reverse-biased at 2.3 V completely cuts off. As a result, a forward bias (5 V) is applied to the drain-side PN junction of the transistor 12.
-3.3V = 1.7V) is prevented from being applied as it is, and the PN junction does not conduct.

On the other hand, the enhancement type transistor 1
The gate threshold value Vth of 4 is set to, for example, 1.5V ± 0.5V. Then, in the circuit configuration of FIG. 2, the gate potential is Vd
Since the d potential is fixed at +3.3 V, the voltage applied to the drain-side PN junction of the transistor 16 (drain-source potential difference of the transistor 16) is 3.3 V-1.5.
V ± 0.5V = 1.8V ± 0.5V. For this reason, the voltage applied to the drain-side PN junction of the transistor 16 is 2.3 V at the maximum, and if the breakdown voltage of this PN junction is set to, for example, 2.5 V or more, +
This PN junction does not break down due to the application of 5V.

The gate input of the transistor 16 (−
When Ei) is 0 V, the potential difference between the gate and the drain of the transistor 16 is 2.3 V at the maximum, and the withstand voltage of the gate oxide film of the transistor 16 is sufficiently ensured. (When 5 V is applied to the gate oxide film, depending on the structure of the transistor 16, the withstand voltage of the gate may not be provided.) The MOS capacitor 240 instantaneously changes in the output Eo.
Current flows through the gate capacitance of the gate electrode, and this current changes the potential VR (from +3.3 V to +2.7 V or vice versa).
Speed is sharpened.

FIG. 3 is a waveform diagram for explaining the AC operation of the embodiment of FIG. 2 (for easy understanding of the waveform,
The potential relationship is partially different from that used in the description of FIG. 2). When the potential of the output Eo increases toward +3.3 V immediately after the time 0 ns, the comparison potential Vcomp also increases by the same amount. In accordance with the time differential value of the potential rise, the potential PG and the gate control potential VR are
It changes more sharply than when there is no 40. During a period (20 ns to 40 ns) during which the potential of the output Eo is stable, the potential of the PG is increased by the gate threshold Vth of the transistor 221 by the amount of E.
It becomes lower than the potential of o.

Immediately after the output Eo changes, the potential V
R temporarily overshoots the Vdd potential (+3.3 V), but after the current through the MOS capacitor 240 stops flowing, the potential VR becomes the Vdd potential (+3.3 V).
V) (time 40 ns).

Immediately after the time of 40 ns, the potential of the output Eo becomes +0
When the voltage drops toward V, the comparison potential Vcomp also drops by the same potential. According to the time derivative of this potential drop,
The potential PG and the gate control potential VR change (fall) more sharply than when the MOS capacitor 240 is not provided. When the current of the MOS capacitor 240 stops flowing due to the sudden change, the once lowered potential VR immediately returns to the Vdd potential (+3.3 V) (time 50 ns). On the other hand, the output E
The period during which the potential of o drops and stabilizes (50 ns to 10 ns)
0 ns), the potential of PG is at a certain potential (+
(1.3V to 1.4V).

At this PG potential (+1.3 V to +1.4 V), the transistor 224 turns on and the transistor 225 turns off, and the CMOS inverter (224 + 225)
Applies a control potential VR of a high level (+3.3 V) to the gate of the depletion type transistor 10.

The output Eo which rises to a potential (+4.8 V in this example) equal to or higher than the Vdd potential (+3.3 V) takes time 100
When the voltage is applied to the I / O pad 18 of FIG. 2 after ns, the comparison potential Vcomp also increases by the same amount. The potential PG and the gate control potential VR sharply change in accordance with the time differential value of the potential rise. During a period in which the potential of the output Eo is stable (110 ns to 140 ns), the potential of the PG is V
It becomes a potential (+3.6 V to +3.8 V in this example) between the dd potential (+3.3 V) and the Eo potential (+4.8 V).

At this PG potential (+3.6 V to +3.8 V), the transistor 224 is turned off, the transistor 225 is turned on, and the CMOS inverter (224 + 225)
Is the low-level control potential VR (+1.8 V in this example)
To the gate of the depletion type transistor 10. Then, the transistor 10 has a high voltage (+
The output Eo of (4.8 V) is reverse-biased at the pinch-off voltage Vp or higher (4.8 V-1.8 V = 3 V), and cutoff is ensured. Thus, the leakage current to the transistor 10 due to the application of the high voltage output Eo is suppressed.

When the output Eo decreases after the time of 140 ns, the PG potential sharply drops. When the CMOS inverter (224 + 225) performs the level inversion operation due to the decrease in the PG potential, the control potential VR becomes the Vdd potential (+
3.3V) and stabilizes thereafter (time 150ns ~)
200 ns). Thus, the state returns to the same state as before the time 0 ns.

FIG. 4 is a waveform chart for explaining the DC operation of the embodiment of FIG. (However, the description will be made with the voltage values of the respective parts being partially changed from those used in the description of FIG. 2.) When the potential of the output Eo is +3.9 V or less (that is, 5
When no V signal is applied), the gate control potential VR is +
Take a constant value of 3.3V. In this case, the depletion type MOS transistor 10 is always in a conductive state, and its drain potential (= drain potential of transistor 12) E1
2 changes in the same manner as the output Eo. The potential of the output Eo is V
Below the dd potential (+3.3 V), the PG potential is also substantially constant (+1.5 V to +2 V).

The potential of the output Eo is Vdd potential (+3.3
From around V), the PG potential also starts to rise in response to the rise in the potential of the output Eo. PG with output Eo rise
The CMOS inverter (224 + 22)
When (5) enters the level inversion operation (Eo = around +3.9 V), the control potential VR decreases (in the description of FIG. 1, + 2.V).
7 V, but in this example +1.8 V).

In this case, the source potential (= output Eo potential) is sufficiently higher (+3.9 V) than the gate potential (VR = + 1.8 V) of the depletion type MOS transistor 10, so that the gate potential of the transistor 10 The sources are reverse-biased at a voltage (3.9 V-1.8 V = 2.1 V) higher than the pinch-off voltage Vp (for example, 1.5 V). Then, the transistor 10 is completely cut off, and the drain potential E of the transistor 12 is
12 stabilizes after a slight decrease corresponding to the decrease of the control potential VR (+3.5 V in this example). Transistor 12
Is fixed at the Vdd potential (+3.3 V), the drain-side PN junction of the transistor 12 is forward-biased (with a potential difference of 3.5 V−3.V) at the stable potential (+3.5 V) of the drain potential E12. (3V = 0.2V) and no conduction occurs.

In the region where the output Eo is 4 V or more, the gate control potential VR is sufficiently reduced.
0 can be completely cut off by the potential of the I / O pad 18 of about 5V. Therefore, no leak current flows from the I / O pad 18 to the drain side of the transistor 12.

[0059]

When the potential of the signal Eo in the output circuit (I / O pad) 18 exceeds the power supply Vdd potential (+3.3 V), the control potential VR becomes lower than the Vdd potential (+3.3 V) (+2.3 V). 7V). Thus, the gate-source voltage of the depletion type MOS transistor 10 is biased in a direction in which the transistor 10 is cut off irrespective of the variation of the pinch-off voltage (gate threshold). As a result, the output circuit 18
, The leakage current flowing into the transistor 10 side can be suppressed. The control potential V corresponds to the potential change of the signal Eo.
Since R changes suddenly, even if the signal Eo changes at high speed,
The control potential VR can follow a change in the signal Eo.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a signal input / output circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram that embodies the configuration of FIG. 1;

FIG. 3 is a waveform chart for explaining the AC operation of the embodiment of FIG. 2;

FIG. 4 is a waveform chart illustrating the DC operation of the embodiment of FIG.

[Explanation of symbols]

10: N-channel auxiliary MOS transistor (depletion type field effect transistor), 12: conductive circuit / element (enhancement type P-channel MOS transistor), 14: conductive circuit / element (enhancement type N)
Channel MOS transistor), 16 switch transistor (enhancement type N-channel MOS transistor), 18 I / O pad (output circuit), 22 comparator (control potential changing means), 24 VR speed-up section (speed-up section) ), 30... Reference potential generating circuit, 221-221
223, 225, 227: enhancement N-channel MOS transistors, 224, 226: enhancement P-channel MOS transistors, 240: enhancement N-channel MOS transistors (MOS capacitors), 301 to 304 ... enhancement N-channel MOS transistors, 305; 306: enhancement type P-channel MOS transistor, Vdd: first power supply circuit (first potential 3.3V), Vss: second power supply circuit (second potential 0V), VR: control potential, Vref: reference potential, Vcomp: comparison Potential, Ei ... input signal, Eo ...
Output signal.

Claims (4)

(57) [Claims] A depletion-type field-effect transistor in which a drain-source circuit is inserted between a first power supply circuit having a first potential and an output circuit, and a control potential is applied to a gate; a second power supply circuit having a second potential A switch transistor inserted between the output circuit and the output circuit; and in a state where the absolute value of the potential of the output circuit is larger than the absolute value of the first potential, the absolute value of the control potential of the depletion type field effect transistor. A signal input / output circuit comprising: control potential changing means for changing the control potential in a decreasing direction; and high-speed means for increasing the speed of changing the control potential by the control potential changing means. 2. A depletion-type field effect transistor having a drain and a source circuit inserted between a first power supply circuit at a first potential and an output circuit, and a control potential applied to a gate; a second power supply circuit at a second potential A switch transistor inserted between the output circuit and the output circuit; and comparing the potential of the output circuit with a predetermined reference potential, and when the absolute value of the potential of the output circuit is larger than the absolute value of the reference potential. The absolute value of the control potential of the depletion type field effect transistor is decreased, and the absolute value of the control potential of the depletion type field effect transistor is increased when the absolute value of the potential of the output circuit is smaller than the absolute value of the reference potential. A comparator for increasing the speed of decreasing or increasing the control potential by the comparator. No. input and output circuit. 3. A depletion-type field effect transistor having a drain / source circuit inserted between a first power supply circuit having a first potential and an output circuit, and having a gate supplied with a control potential; the first power supply circuit and the depression A conductive circuit inserted between the field-effect transistor; a switch transistor inserted between a second power supply circuit of a second potential and the output circuit; and a switch transistor between the second power supply circuit and the switch transistor. A transistor of the same conductivity type as the depletion type field effect transistor; comparing the potential of the output circuit with a predetermined reference potential, and determining that the absolute value of the potential of the output circuit is If the absolute value of the control potential is larger than the absolute value of the reference potential, the absolute value of the control potential of the depletion type field effect transistor is reduced, and A comparator for increasing the absolute value of the control potential of the depletion-type field-effect transistor when the absolute value of the potential is smaller than the absolute value of the reference potential; A signal input / output circuit comprising: a speed-up means for increasing or decreasing the control potential by the comparator. 4. A depletion-type field effect transistor having a drain / source circuit inserted between a first power supply circuit having a first potential and an output circuit, and having a gate supplied with a control potential; the first power supply circuit and the depression A first conductivity type field effect transistor having a gate to which a first input signal is applied; and a second potential circuit between the second power supply circuit and the output circuit. A second conductivity type field effect transistor having a drain-source circuit inserted therein and a gate supplied with a second input signal having an opposite phase to the first input signal;
The potential of the output circuit is compared with a predetermined reference potential, and when the absolute value of the potential of the output circuit is larger than the absolute value of the reference potential, the absolute value of the control potential of the depletion type field effect transistor is reduced. A comparator for increasing the absolute value of the control potential of the depletion-type field effect transistor when the absolute value of the potential of the output circuit is smaller than the absolute value of the reference potential; A signal input / output circuit comprising: speed-up means for increasing or decreasing the control potential by the comparator in response to the increase.