JPS59115621A - Logical circuit - Google Patents

Abstract

PURPOSE:To offer a counter circuit possible for test by a short test series by changing over the counter operation into a normal counter operation, a shift register operation and an operation of two 2-bit counters by means of a gate connecting means in a counter circuit included in a logical circuit. CONSTITUTION:The mode is selected to the shift register mode at test, 0, 1 are shifted and the function of a D-FF is checked by the observation from an output line 7. The functions not confirmed by said check, i.e., the functions of connecting Sw41-Sw4n and connecting Sw22-Sw2n are confirmed as follows. That is, when the shift register operation is executed so as to set all FFs to 0 and a clock is supplied to FFs at an odd number stage from a clock input line C, the positive output Q of the FFs is inverted into 1 at the normal operation, and the output Q of an even number of stages receives the clock from the output Q of the prestage and is inverted into 1. The inversion is checked by the shift register operation and by observing whether each FF is set to 1 or not from an output line 7. The positive output of the even number of stages and the connecting function to the next stage are checked according to the above-mentioned method. Switches shown in the figure are constituted actually by logical gates or TRs or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an easily testable counter circuit in a large scale integrated circuit (LSI) having a multi-stage counter circuit.

[Prior art and its problems]

Conventionally, LSI'i test l.
When doing so, a long test series is required to confirm the functionality of the counter circuit. For example, in an LSI containing a 12-bit counter, 4,096 clocks are required for the final bit counter to operate, and in the case of a 16-bit counter, 65,536 clocks are required. Therefore, having a multi-stage counter requires a long test series, which is
This method has the disadvantage of increasing the test time of I.

[Purpose of the invention]

This invention improves the drawback that the test series of LSIs with multi-stage counters described above becomes long.
The purpose is to provide a complete counter circuit that can be tested with a short test series.

[Summary of the invention]

FIG. 1 is a block diagram showing an example of a normal counter circuit. The figure shows an example of a 4-bit Atsuzo counter.
In the figure, 1 is a clock input line, 2345 is a D-type flip-flop, D is a data input terminal of the D-type flip-flop, CKld is a D-type flip-flop input terminal, and QQ is a positive output of the D-type flip-flop. The output terminal, the inverted output terminal, and 01.02.03.04 are the normal output lines of the respective flip-flops.

The waveform of the output 01.02.03.04 of each bit of the counter when all clocks are supplied to the clock input terminal is the second waveform.
As shown in the figure. In this case, the output 04 of the final stage; 0 → 1 → 0
In order to change, 16 clocks must be supplied. In the case of a multi-stage counter, the output of the final stage changes from 0 → 1 →
In order to change to 0, it is necessary to supply a large number of clocks. Therefore, when testing an LSI having multiple stages of counters, a long test series is required.

FIG. 3 is a block diagram showing the configuration of the present invention. In this example, a configuration of an even-numbered 8-stage counter is shown. In the figure, 1234 is a D-type flip-flop;
is a shift data external input line, 6 is a clock input line during normal operation, 7 is a counter external output line, D, CK, Q, and Q are the data input terminal, clock input terminal, and normal output of the D-type flip-flop, respectively. terminal, inverted output terminal, C is external clock input line, 5w1l~S I n r Sw2
1~SW2 n, SW3□832, 5w41~5W4
n is a switch.

5WII~3VL'1n for normal counter operation
OFF, 3w21~5W2n 7. rON,
5W315Wa2k OFF, 5W41~Sw4.
, fON and supplying a clock from the clock input line 6.

If the first mode is a normal counter operation, the second mode is 5w11~Sw1°1.1 ON, Sw2
i~S2n f OFF.

"""N "'az 'K ON, 5w41~SW4
The shift register is realized by inputting shift data from the shift data external input line 5 2 and supplying a clock from the external clock input line C.

The third mode is Swll-3wl r, 'tl O
FF, odd number of 5w21-8w2n-i OFF
Even numbered gate? :ON, Sw""ON, 5w3z'f
l: OFF, 5W41-8W4+1 f ON,
This is achieved by supplying a clock to the odd-numbered flip-flop (1) from the external clock input line C, resulting in an independent two-pit power counter operation such as D flip-flops 1 and 3, and the next flip-flop. .

The fourth mode is to turn off S"11-8 In,
Sw21-8W2 n odd number is ON, even number is O
FF, SWAT OFF.

Set 5W32 to ON, 5W41 to SW4 ne ON,
This is realized by supplying a clock from the external clock input line C to the even-numbered D flip-flops, and the D flip-flops 2, 3rd and 30th stage, and the next stage flip-flop, etc. Bit power counter operation is performed.

During the test, first operate in the second mode, that is, shift register mode. * 0 〃% 1. 〃f
- shift and observe from external output line 7. This operation allows all functions of the 1D flip-flop to be checked.

The functions that cannot be confirmed in the operation of the shift register are the inversion function of the counter, that is, the connections 5W41 to S4n between the inversion output of the D flip-flop and the data input terminal, and the clock input CK of the normal output terminal Q and the next stage D flip-flop.
This is the function of connection 5W22 to S2r+.

In order to check these functions, operate the third mode. If the shift register is operated in advance and the state of all D flip-flops is set to 6/1, and a clock is supplied from the external clock input line C to the odd-numbered stage D flip-flops, if they are functioning normally, the odd-numbered stage The normal output Q of the flip-flop is inverted and becomes 1", and the normal output Q of the even-numbered stage receives a cyclic signal from the normal output Q of the 7th flip-flop of the odd-numbered stage in the previous stage, and is inverted and becomes 1". 3. To check these inversions, set the shift register mode, operate the shift register, and connect each D flip-flop to 11 from the external output line 7.
“This can be achieved by observing the set value.

Through these operations, the inverting function of each D flip-flop, the normal output Q of the odd-numbered D flip-flop, and the D
Although it is possible to check the function of the connection between the flip-flop and the clock input CK, it is not possible to check the function of the connection between the normal output of an even stage D flip-flop and the next stage D flip-flop.

To check this function, operate the fourth mode. Operate the shift register in advance and all D
If the value of the flip-flop is set to 10" and a clock is supplied from the external clock input line C to the even-numbered D flip-flops, the normal output Q of the even-numbered flip-flops will be I turned around and became Qi 1,
Furthermore, the normal rotation output Q of the odd-numbered stage receives the clock supply from the normal rotation output Q of the even-numbered flip-flop in the previous stage and becomes 1. To check for these reversals,
This is realized by operating a shift register and observing from the external output line 7 whether the value of each D flip-flop is set to 11''.

The switches in FIG. 3 are actually made of logic gates or transistors, and their gate connection means and gate control means will be described in the embodiment section of the invention.

〔Effect of the invention〕

The present invention is characterized in that the counter circuit included in the logic circuit can be switched to normal counter operation, shift register operation, and two 2-bit power counter operations by gate connection means as described above. It has a distinctive sound that allows you to fully test the counter in two modes.

Therefore, according to the present invention, if the number of stages in the counter shown in FIG. , 4 for counter operation, and even if these are used in combination, there is an effect that the cost is significantly reduced.

[Implementation f11 of the Invention] Here, the gate connection means and the gate control means will be described.

FIG. 4 shows a configuration in which the gate connection means, ie, the switch in FIG. 3, is replaced with a MOS transmission gate. 12
34 is a D-type flip-flop, 5 is a shift data external input line, 6 is a clock input line during normal operation, 7 is a counter external output line, 8 is an MO8 transmission gate, C is an external clock input line, and D.

CK, Q r and Q are D-type flip-flops (Df-type input terminal, clock input terminal, normal output, inversion output, and 01 to G6 are gate connection means control lines.

The gate control circuit is shown in the m5 diagram, and A and B are shown in the foPJ diagram.
is a mode control line, 01 to G6 are gate connection means control lines,
1 is an AND gate, 2 is a NAND gate, and a 34-digit inverter.

The operation of FIG. 5 is shown in Table 1. During normal counter operation u,
A=O, B=O, A=l in shift register mode
, B=1. ．． In two 2-bit counter modes, A=
O, B=1 and A=1. , by setting B=O, the fourth
The circuit in the embodiment of the invention shown in the figure can be controlled.

Table 1 The configuration shown in FIG. 3 requires as many external control lines as the number of switches, which is not desirable for LSIs with limited external terminals. Therefore, by using the configurations shown in FIGS. 4 and 5, the configuration shown in FIG. 3 can be realized with a small number of external terminals.

[Brief explanation of drawings]

Figure 1 shows a conventional 4-bit counter circuit; Figure 2 shows a conventional 4-bit counter circuit;
The figure shows the clock waveform in Fig. 1 and the output waveform of the normal rotation output 01.02.03.04 of each bit of the counter, Fig. 3 shows the entire configuration of the present invention, and Fig. 4 shows the present invention. FIG. 5 is a diagram showing an embodiment of the invention. FIG. 5 is a diagram showing a mode control circuit in an embodiment of the invention. I<rllz, 4 Electric tube 廿 1A-1J℃
wealth 6 brown (4〔(兇)Fig. 5 crl crl r3 l4 G-, nishi

Claims (1)

[Claims] In a counter circuit existing in a logic circuit, the counter circuit operates as a shift register and as an independent counter of 2 bits each from the first stage of the counter circuit,
In addition, in order to operate as an independent counter of 2 bits each starting from the second stage of the counter, the data input of the flip-flop constituting each bit If of the counter circuit is connected to the inverted output of the flip-flop and the flip-flop of the previous stage. It has gate connection means that can alternately switch between the normal output of the flip-flop of the preceding stage and the external clock input line for the clock input of the flip-flops constituting each of the Virator circuits of the counter circuit. It has a gate connection means that can be switched alternately, and further has two external clock input lines, which are alternately supplied to each flip-flop, and when testing, they are connected to a shift register and connected to a shift register. The function of each flip-flop is confirmed by operating it, and the counter circuit is operated as an independent counter of 2 bits each starting from the first stage, and the function of inverting the counter and connecting the normal output of the flip-flop to the next stage clock input is confirmed. Furthermore, the second stage of the counter circuit is operated as an independent counter of 2 bits each, and the normal rotation output of the 2-bit counter whose function cannot be confirmed by the independent counter operation of 2 bits each from the first stage is connected to the next stage. A testable logic circuit characterized by confirming the connection function of a clock input of a flip-flop at the front stage of a 2-bit counter.