GB2171826A - Soft programmable logic array - Google Patents

Abstract

A soft programmable logic array comprises first, second, fourth and sixth logic ranks of functional elements (12 to 26), (28-38), (52-58), (68, 70) each of which produces logic functional outputs which are predetermined logic functions of the inputs; third, fifth and seventh ranks consisting of flip-flop pass- through devices (40 to 50), (60-66), (72, 74) connected to perform an inverting non-delayed pass-through or a latch function according to a predetermined function; an output enable rank (80 to 124) connected to receive inputs from the third, fifth and seventh ranks of pass-through devices to provide data output for said logic array; and control circuitry connected to all the functional elements and pass-through devices for controlling and clocking the logic array and for providing latch inputs to set all the functional elements and the flip-flop pass-throughs to perform a predetermined logic function. <IMAGE>

Description

1 GB2171826A 1

SPECIFICATION

Soft programmable logic array The present invention relates to soft program- mable logic arrays.

Typically, programmable logic arrays are incorporated on large scale integrated circuit (LSI) or very large scale integrated circuit (VI-SI) circuit chips. These programmable logic array chips are of a type that when manufactured, the particular logic function of the circuit is not determined. A programmable logic array chip is designed so that the logic func- tion of the chip may be subsequently determined. Most of such prior art chips are hard programmable in that they contain fuses or other elements which are permanently burned or blown out in order to determine the logic function of the device. The present invention relates to a soft programmable logic array in that any particular device may be repeatedly programmed with the same or with different logic functions through a process of inputting logic functional data, which is sometimes known as characterisation data. Although a soft programmable logic array requires the loading of characterisation data in order to function, a soft programmable logic array ac- cording to the present invention is not merely a memory device. The characterisation data is used to control the particular logic functions to be performed at particular logic levels in the soft programmable logic array. In addition, soft programmable logic array according to the present invention may be arranged with four quadrants or sectors and control circuitry on each chip so that several independent arrays are on one chip with common functional control.

U.S. Patent Specification No. 3,818,252 shows a plurality of word lines and digit lines as inputs to an array which contains fuses for the programmable elements. This patent spe- cification shows, in effect, a variation of a standard programmable logic array having two levels for the production of a sum of products type of function, but does not disclose the present multi-level soft programmable logic ar- ray. U.S. Patent Specification No. 4,233,667 also shows a programmable logic array, but which does not disclose the present invention in structure or capability.

U.S. Patent Specification No. 3,912,914 shows a programmable switching module which can become extremely complex for any particularly large switching iunction to be em ployed since the programming control for any switching function must be brought off the particular chip by individual wires to control the switching function. The present invention may be programmed by inserting a stream of characterising data which controls the various logic elements as a result of a characterising process. U.S. Patent Specification Nos. 130

3,855,536, 3,976,983 and 4,293,783, all show logic arrays but which either require programming control through external logic pins or which have limitations on the particular logic functions that may be accomplished.

Although the present invention is primarily directed to any novel integer or step or combination of integers or steps, herein disclosed and/or as shown in the accompanying draw- ings, nevertheless, according to one particular aspect of the present invention to which, however, the invention is in no way restricted, there is provided a soft programmable logic array comprised of: a first logic rank of func- tional elements each of which produces logic functional outputs which are predetermined logic functions of the inputs; a second rank of functional elements connected to said first rank each of which produces logic functional outputs which are predetermined logic functions of the inputs; a third rank consisting of flip-flop pass-through devices connected to second rank to perform an inverting non-delayed pass-through or a latch function accord- ing to a predetermined function; a fourth rank of functional elements connected to receive inputs from said third rank of pass-through devices each of which produces logic functional outputs which are predetermined logic functions of the inputs; a fifth rank consisting of flip-flop pass- through devices connected to said fourth rank to perform an inverting nondelayed Pass-through or a latch function according to a predetermined function; a sixth rank of functional elements connected to receive inputs from said fourth rank of passthrough devices, each of which produces logic functional outputs which are predetermined logic functions of the inputs; a seventh rank of flip-flop passthrough devices connected to receive data inputs from said sixth rank to perform an inverting non-delayed pass-through or a latch function according to a predetermined function; an output enable rank con- nected to receive inputs from said third, fifth and seventh ranks of pass- through devices to provide data output for said logic array; and control means connected to all of said functional elements and pass-through devices for controlling and clocking said logic array and for providing latch inputs to set all of said functional elements and said flip-flop pass throughs to perform a predetermined logic function.

Preferably each functional element has three data inputs, eight logic control inputs, one data output and is comprised of an eight-to one multiplexer and eight AND gate/set latch circuits as inputs to the multiplexer.

According to a further non-restrictive aspect of the present invention there is provided a soft programmable logic array for performing a preselected logic function on a data input function comprising: a first rank of logic ele ments each of said logic elements consisting 2 GB2171826A 2 of functional elements having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the func- tion to be performed connected to receive data inputs to said system and a first set of logic signals to set the latches of said first rank of logic elements; a second rank of logic elements connected to said first rank of logic elements, consisting of functional elements each having a plurality of data input receiving lines connected to said first rank, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs to said second rank and a second set of logic signals to set the latches of said second rank of logic elements; a third rank of logic elements connected to said second rank and consisting of flip-flop passthrough devices having means for receiving and latching a third set of logic signals to control the function performed by said pass-through devices; a fourth rank of logic elements each of said logic ele- ments consisting of functional elements each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed con- nected to receive inputs from said third rank of pass-through devices and having means for receiving and latching a fourth set of logic signals to set the latches of said functional elements to perform the predetermined logic function; a fifth rank of logic elements connected to said fourth rank and consisting of flip-flop passthrough devices having means for receiving and latching a fifth set of logic signals to control the function performed by said pass-through devices; a sixth rank of logic elements consisting of functional elements connected to said fifth rank each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs from said fifth rank of passthrough devices and having means for receiving a sixth set of logic signals to set the latches of said functional elements to perform the predeter ined logic functions; a seventh rank of logic elements connected to said sixth rank consisting of pass-through devices each having a plurality of data input receiving lines, as least one data output line and means for receiving and latching control signals representative of the predetermined function to be performed; and an output enable rank connected to receive inputs from said third, fifth, and seventh rank of pass-through devices to provide data output for said logic array.

The logic array may further comprise control means for providing a serial stream of control signals for input into all of the latches of said functional elements and a stream of latch set control signals to cause the setting of the appropriate latch control signal in the appropriate latch.

The logic array preferably includes clock control means to control the gating of the appropriate control signals to the appropriate functional elements in logic rank order during operation of the logic array.

The logic array may include a counter ar- ranged to be incremented upon receipt of individual control signals in the input serial data stream and the output count of said counter controls the addressing of said functional elements.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which:

Figures 1 A, 1 B and 1 C are intended to be viewed in left-to-right order, side-by-side, and represent a detailed logic diagram of one embodiment of a soft programmable logic array according to the present invention; Figure 2 is a detailed logic diagram of one of the functional elements of the logic array shown in Figures 1 A, 1 B and 1 C; Figure 3 is a detailed logic diagram of a pass-through/hoid device of the logic array shown in Figures 1 A, 1 B and 1 C; Figure 4 is a detailed logic diagram of an output enable logic element of the logic array part shown in Figure 1 C; Figure 5 is a logic diagram of a control circuit of the logic array shown in Figures 1 A, 1 B and 1 C; Figure 6 is a logic diagram of the control circuit for characterising logic to drive the logic array of Figures 1 A, 1 B and 1 C; and Figure 7 is a simplified logic diagram of the logic array shown in Figures 1 A, 1 B and 1 C, showing only essential logic interconnections.

Figures 1 A, 1 B and 1 C show one embodiment of a soft programmable logic array 10 according to the present invention. Logical data inputs occur at the left-hand side of Fig- ure 1A, and progress through the various logic levels so that outputs, according -to the predetermined programmed logic function, occur at the right-hand side of Figure 1C.

A plurality of functional elements 12, 14, 16, 18, 20, 22, 24, 26 make up a first logic level of the logic array 10. Functional elements 12 to 26 are all identical and the structure of the functional element 12 is shown in detail in Figure 2. Each functional element has three data inputs. The data inputs to the functional element 12 are shown as A, B and C with number notation to show the particular functional element number. Similar notation is used for the data inputs for all eight functional ele- ments of the first logic level. Each functional element 12 to 26, has a single output which is interconnected with the remainder of the logic array 10. A second logic level is formed of six functional elements 28, 30, 32, 34, 36, 38. The six functional elements, 28 to 38, are 3 GB2171826A 3 connected to six pass-through/hold devices 40, 42, 44, 46, 48, 50. These pass-through/hold devices are all identical and a detailed diagram of the pass-through/hold device 40 is shown in Figure 3. These six pass-through/hold devices constitute a third logic level. The outputs of these six pass-through/hold de vices are connected to a fourth logic level.

The fourth logic level consists of four func tional elements 52, 54, 56, 58. The outputs of the four functional elements of the fourth logic level are connected as inputs to four passthrough/hold devices 60, 62, 64, 66 which constitutes a fifth logic level. The pass through/hold devices 60 to 66 constitute the 80 fifth logic level. A sixth logic level consists of two functional elements 68, 70. The outputs of the functional elements 88, 70 provide in puts to function/pass-through elements 72, 74 which constitute the eighth logic level. Each functional element has a number with a prefix of FE with a particular element number. Similarly, all of the pass-through/hold devices are numbered with a particular number and the prefix FP.

Output logic consists of a two-stage element which may be thought of as a single function. The first stage of each twostage element is an output enable gate which is shown in detail in Figure 4. The output enable gate is connected with a tristate buffer which has possible outputs of "High", "Low" and "Floating". The floating output floats with the signal level on the output line assuming that other active logic devices are also connected to the same logic line. Thus, the output logic is, in the illustrated embodiment determined by 12 pairs of output devices having 12 output enable gates 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124. Each output enable gate is associated, respectively, with a tri-state buffer 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126.

The logic array shown in Figures 1 A, 1B and 1C may preferably be constituted as one quadrant or sector of four identical quadrants or sectors to be put on a single VLSI chip. In different embodiments, a different number of sectors with a common control system may be used. Thus, a single VLSI Chip would contain four logic arrays, each as shown in Figures 1A, 1B and 1C, arranged in quadrants together with a single control circuit as shown in Figures 5 and 6. Figure 6 is so constituted that it may control four separate circuits of the type shown in 1 A, 1B and 1C. The various control lines shown entering Figure 1A are generated by the control circuit as shown in Figure 6, which will be described in detail later.

The outputs of the control circuit to each individual quadrant is connected to a 3-input to 8-output decoder 140 shown in Figure 1A. C5, C4, C3 input lines come from the control circuit of Figure 6, while C'9 control line turns the decoder ON or OFF, depending on whether this is the particular one of the four quadrants addressed. Similarly, a decoder 142 is a 2-input to 4- output decoding element with the inputs being derived from the control circuit of Figure 6, while C'13 line turns the decoder on or off, based on inputs as shown in Figure 6. Sets of AND gates 144, 146, 148 control the fanout of the required control signals in order to load the program for a particular programmable logic function to be performed.

Referring now to Figure 2, a detailed logic diagram is shown of the functional element 12. The functional element has an 8-bit to 1bit multiplexer 200 where output FD represents the data output. The data input is represented by input signal lines A, B, C which are the select control lines of the multiplexer, but which form the data inputs to the functional element. For each of the eight input lines to the multiplexer there is an AND gate/set latch circuit 202, 204, 206, 208, 210, 212, 214, 216. The functional or characterising data in- puts to control the functional output of the multiplexer 200 are provided on program inputs SO to S7. Clear signal and write enable signal functions will be explained in connection with the control circuit of Figure 6. Each of the set latch circuits 202 to 216, when programmed with a functional input, will hold that functional input for all operations of the circuit. The clear signal will clear to zero all of the gates as part of the initialisation process. The write enable signal must be enabled in order to write or program any function.

It is known from the functional description of a multiplexer that an 8bit to 1-bit multiplexer having three control inputs may select any one of the possible inputs as an output using a 3-bit control signal. Conversely, it is known that any logical function of three data bits must be either a high or a low data bit. By properly programming the eight input bits to the multiplexer 200 with high and low bits, provision may be made for the output of the multiplexer 200 to be any logical function of the three data bits input on control lines A, B, C. This then represents the logical structure of the functional element 12 which operates as a building block of the logic array.

Referring now to Figure 3, the passthrough/hold device 40, is shown in detail. The pass-through/ hold device 40 consists of a set/re-set AND gate latch element 220, a flip-flop 222, and an AND gate 224, all connected as shown. If the latch element 220 is set as part of the characterisation function, the data input from the previous section makes the AND gate 224 and the device functions as a data pass-through circuit, and inverts the data while passing it through without significant time delay. If the latch element 220 is not set, then for data to pass through the unit a clock signal must initiate the flip- 4 GB2171826A 4 flop 222 in addition to the data input in order to make the AND gate 224 pass the data.

Referring to Figure 4, the output enable gate is formed of a set/re-set latch circuit 230 together with a gate 232. If the output of the gate 232 is ON, the buffer 82 is responsive to be high or low in response to the data input to the buffer. If the output enable line of the gate 232 is not enabled, then the associ ated buffer is off or floating, regardless of the data input. Input control lines to the gate 232 function as follows: E holds or forces the gate to be OFF; F is a test input and forces the output to be enabled; and E is the nor al enable function input.

Figure 5 shows a control system register 281 which produces a FORCE control func tions input to a gate 283 as shown in Figure 1C and respectively for the other similar qua drants.

Referring now to Figure 6, a control circuit 300 for controlling the logic array of Figure 1 as one of four identical logic arrays is shown.

The control circuit 300 has a controlling clock 302. The input test data stream is provided on an input 304. The input test data stream may be provided in a standard computer envi ronment as one function of the test mainte nance logic system outside of the normal data paths as part of the initialising function. The clock 302 performs a set, clear and forget function. That is, it prepares a one shot signal for controlling the various clear bits on a clear output 306 so that all circuits are intially cleared, but because a one shot is formed, 100 the clear signal does not need to drop out, it drops out automatically.

A decoder 308 works in conjunction with a counter 310 to provide an 8-bit output chan nel for gating in common to the various func tional elements such as the functional element 12. Thus, the input serial stream of data on a 1-bit channel is controlled by the counter 310 with the decoder 308 so that each functional element, such as the functional element 12, which is addressed by the 8-bit output chan nel, has its program inputs sequentially trig gered. A counter 312 provides output control signals on lines C as shown to Figure 1 for controlling which select logic on which the functional elements or which the pass through/hold devices are triggered for ad dressing of the programming function. The counter 310 also controls which output enable gate is addressed.

Referring now to Figure 7, a simplified sche matic logic diagram of the logic array of Fig ures 1 A, 1 B and 1 C is shown. The logic de vices are only shown symbolically and the var ious programming and control function lines are not indicated. Thus, reference numerals 12, 16, 18, 20, 22, 24, 26 are used on Fig ure 7 to indicate functional elements just as on Figure 1A because the element and its function is intended to be the same. Thus, Figure 7 shows the same logic array as shown in Figure 1 A, 1 B and 1 C with eight levels of logic and an output level forming the soft programmable logic array 10. The one significant difference in Figure 7 is that the two-stage pairs of output elements, as shown in Figure 1C, are simplified to a single output element in Figure 7. Thus, the combined output enable gate and tri-state buffer devices are indicated on Figure 7 with the reference numerals 82A 86A and so, respectively, to 126A to indicate correspondence to the tristate buffers 82, 86, 90 and so on up to 126, as shown in Figure 1C.

The soft programmable logic array, according to the present invention and described above, is designed to solve one of the recurring problems in logic design, that of "gluing" parts of a system in simple control functions.

This is to distinguish from significant arithmetic functions like adders and multipliers which are usually specially designed. Although the logic array could be designed to form an addtiion or multiplying function, it would not be typically efficient. The logic array is considered to be most efficient in performing stray, leftover or "glue" functions of the sort that are needed to complete the logic of an arithmetic or Boolean operation system in a com- puter. For example, if a computer system has four separate 16-bit adders, or even multipliers, that operate separately in 16-bit mode, then it would be useful to use a soft programmable logic array to allow for control and logic functions for allowing the four separate systems to operate in parallel in a 64-bit mode. It is not intended that the logic array be used to implement the entire control section of a computer mainframe. Dedicated mi- crocode and dedicated arithmetic or Boolean functions would be more efficient for designs as large as that. Instead, the logic array will work well for functions such as overflow detection in an arithmetic logic unit or control distribution for tri-state bus usage.

The prior art used fused techniques in making programmable logic arrays. However, there is no useful or economical way to introduce fuse-type programmable logic into very large scale integrated circuits. The present invention fulfills such a need by providing for either combinational or sequential logic functions which may be selected and mixed by the user as a result of characterisation data.

The base functional element of the logic array, is a functional element such as the functional element 12 that can be configured to implement any logic function of three inputs. A number of logic levels or ranks of these functional elements is connected together to form the logic array as a whole. A first rank of the functional elements is tied to the input pins and the outputs of the first rank of functional elements drive the next succeeding rank of functional elements.

GB2171826A 5 There are four separate groups of functional elements in the embodiment of the present invention shown. There are four separate logic arrays on a single VLSI chip and each logic array is referred to as a sector or quadrant since it is one of four identical logic arrays. Within each quadrant there are eight functional elements in a first rank connected to 24 input pins. There are six functional elements in a second logic rank, four functional elements in a third logic rank, and finally two functional elements in a fourth logic rank. All functional level outputs of the second and succeeding ranks are connected to chip output pins in addition to supplying output to succeeding ranks. This means that a user can implement up to six moderately simple logic equations or up to 12 mixed term logic equations, or as few as two complex logic equations, using the various combinations of functional elements in ranks. The most complex equation that can be programmed in a given logic array of the type shown in Figures 1 A, 1B and 1c can encompass seven functional elements with 21 input pins.

At the output of each functional element in each rank, except those of the first rank, is a selectable flip-flop or pass-throug h/ hold device. Each flip-flop is selectable to function as a single cycle holding register or to pass data directly through with no data latching and with minimum delay. There is an input on each flipflop that allows all flip-flops to be forced clear under system control for testing.

Associated with each chip output pin is an output element that controls the tri-state control line of each output pin buffer. A user can force the output pin to be constantly enabled, that is, the data output never turned off, as well as enabling an input pin associated with each of the four quadrants to control the tristate line of each output pin of a quadrant.

Each functional element, such as the functional element 12, contains an 8to-1 multi- plexer driven by eight memory latches and three select inputs, A, B and C, that are decoded to select the state of one latch to the multiplex output. The eight data latches are set and cleared to implement the desired logic function of the A, B, C inputs. The eight data latches form a full truth table for three inputs, allowing any logic function of three bits to be implementing by setting and clearing the required data latches. As a simple example, FID = ABC is made by clearing all data latches except for the latch associated with S7, which is set. The truth table for any required logic function is easily found by several well-known logic methods.

All latches are initialised by circuitry con- 125 trolled from the control circuit shown in Figure 6. All latches are cleared at the same time and then conditionally set sequentially by data coming in the input 304. Within each func- tional element, latch bit zero is strobed first and then latch bits are strobed in order with latch bit 7 occurring last.

The pass-through/hold device 40, as shown in Figure 3, is a 2-to-1 multiplexer that is con- trolled by a latch bit which is identical to the latch element 220 in the functional element 12. The latch elements are also controlled in the same manner under the system control functions provided by the control circuit in Figure 6. If the latch element is cleared, then the input data from the driving functional element is passed directly to the output of the multiplexer, and thence to the 'output pin and succeeding functional elements, if any. In this case, the data is inverted. This must be taken into account when writing the logic equations of succeeding ranks of functional elements. If the latch element is set, then the output of the flip-flop 222 is connected to the multi- plexer output. Note that in this case, data is not inverted from the input to the output as in the direct pass-through case. This change in inversion between flip-flop and pass-through mode causes no problems because the data latch is a write-once device only at the powerup condition. It, thus, cannot change during use. The fact that data is inverted can be taken into account by generating the logical complement of the required logic function in the function element driving the particular input.

The flip-flop 222 is clocked continuously without any gating. This means that in order to build state-sequential circuitry, the output of the functions element must be connected back to a chip input as an input to the defining logic equations. There is a reset input to the flip-flop that comes from the control device shown in Figure 6 that can be used to initial- ise the flip-flops for usage or testing. The output enable gate 80, shown in Figure 4, is connected to the tri-state control line of each functional output pin. The output enable has three differing nodes of operation.

The first mode of the output enable is a data bit of storage that, if set, will hold the respective tri-state control line high with the output enabled, except that the output pin can be forced off by the output disable Hold-off bus.

The second operational condition is that if the data bit is clear, then the input/output/ pin in common for each output enable device in a quadrant can control the tri-state control line. A high level on this pin will enable all output buffers and the corresponding logic array quadrant, except that the Hold-off bus again can override the enable line.

The third mode of operation is that each output in a quadrant can be forced on, output enabled, by a function bit in the control systemregister 281 shown on Figure 5. Thus, there are four individual control bits. While it is expected that this facility will normally be used for maintenance, there is nothing pre- 6 GB2171826A 6 cluding its use in system operation. The control circuit shown in Figure 6 is an integral part of the soft programmable logic array and provides initialisation with characterising or test data. This is because the logic array has no function until the control circuit loads the data latches that describe selected logic function. The data latches that implement the required logic functions are loaded by first clear- ing all the data latches in all quadrants and then setting each latch individually, if required, with the data coming from the test data input. There is a bit counter, on chip, that counts from zero to 767. Of the 768 counts, 736 are bit latches for 184 latches in each quadrant plus 8 extra counts. Each function latch is set if the test data input bit is a one and then the counter is incremented. This counter is simply bumped by one if the input bit is zero. The function bit descriptions for the control functions are as follows: The WRITEF function is active if bit one of the control register is set when a test strobe input pin is active. The WRITEF must be active to enable the writing of the function description latches. WRITEF can be set in the same control word as INITF and CLEARF. When WRITEF is active and the test clock enable input pin is high, the state of the test data input pin is written into the currently addressed latch.

The INITF function is activated if bit 2 of the control register is set when the test strobe input pin is active. INITF performs two functions: 1) it clears to zero the address counters that select individual function latch bits, and 2) it also clears all interstage flipflops in all four logic quadrant arrays. INITF is a ome-shot function in that it is active for only one clock at the leading edge of test strobe becoming active. This means that this function can be in the same function control word as WRITEF to simplify the contol sequences required in order to write the function description latches. This is done by holding the test clock enable control line low or inac- 110 tive when bringing test strobe high. After a delay of at least two clock cycles, the test clock enable can be brought high and the description latches are written.

The CLEARF function is activated if bit 3 of 115 the control register is set when the test strobe input pin is active. CLEARF clears to zero all function description latches in all quadrants. This must be done at powerup time when the logic array is first being written and can be performed at other times to change the chip function. CLEARF is not necessary if it is required that the description latch that is holding a zero be changed to a one. A func- tion of WRITEF/INITF is used with a data stream of all zeros except for ones at the required change locations. CLEARF is a oneshot function in that it is active for only one clock cycle at the leading edge of a test strobe becoming active. This means that this function can be in the same function control word as WRITEF to supply the control sequences required in order to write the function description latches. This is done by holding the test clock enable low when bringing the test strobe high. After a delay of at least two clock cycles, the test clock enable can be brought high and the description latches written.

The four functions, FORCEF 0 through FORCEF 3 respectively, representing bits 4, 5, 6 and 7 of the control system register 281, force all output pins active in the respective quadrants. The function overrides the state of the output enable pin, the Hold-off bus, and the state of any function description latch in the output enable gates. While it is expected that these function bits will be used mainly by diagnostics, they can also be used during nor al system operation. The four bits are loaded into a static holding register at a leading edge of a test clock enable signal.

The BLOCKF function is active if bit 8 of the control system register is active when the test strobe input is active. BLOCKF disables all output pins in all quadrants. This function overrides the output enable pins and the state of any function description latch in any output enable device. BLOCKF forces the hold-off bus into the disable mode. BLOCKF will not override any active FORCEF function.

The logic array, according to the present invention and described above, has several desirable attributes. First, the logic array is configured for the function being performed. If the part or array is moved from one location in the system to another location, it implements the logic equations for the new location without any physical change of the part. The delay of a logic signal through the part is proportional to the complexity of the logic equation being implemented. Several simple equations can be done, or few or more complex equations, thus giving the logic designer additional flexibility. The logic array implements variable functions among a fixed set of inputs rather than the previous fixed equations on variable inputs of the prior art. The flip-flops, which are part of the logic path, can be used to implement state equations or can be disabled to implement combinational logic.

The first rank of functional elements feed into second rank of functional elements. Each individual functional element of the second rank can then drive its own output pin or it can feed third rank of functional elements which drive output pins. The third rank can in turn drive fourth rank of functional elements. Because of this interconnection, the logic array can have all outputs on the second level active so that up to six moderately simple equations can be solved in the logic array. As large equations get more and more complex, the third and fourth rank of functional ele- ments can be used to allow wider and wider 7 GB2171826A 7 first and second level pieces to be part of the logic equation and solve thereby more and more complex logic equations.

Both logic types of solutions can be used at the same time. In other words, some simple logic equations should provide signals that can also go into more completed logic equations. Second and third level outputs can be active at the same time that third and fourth level outputs are active, so that simple and complicated logic functions are produced simultaneously. By choosing the state of the passthrough/hold devices, whether they are holding or passing data, some of the logic equations can be state equations and some of the logic equations can be pure combination equations.

Claims (9)

1. A soft programmable logic array comprising: a first logic rank of functional elements each of which produces logic functional outputs which are predetermined logic functions of the inputs; a second rank of functional ele- ments connected to said first rank each of which produces logic functional outputs which are predetermined logic functions of the inputs; a third rank consisting of flip-flop passthrough devices connected to second rank to perform an inverting non-delayed pass-through or a latch function according to a predetermined function; a fourth rank of functional elements connected to receive inputs from said third rank of pass-through devices each of which produces logic functional outputs which are predetermined logic functions of the inputs; a fifth rank consisting of flip-flop passthrough devices connected to said fourth rank to perform an inverting non-delayed pass- through or a latch function according to a predetermined function; a sixth rank of functional elements connected to receive inputs from said fourth rank of pass-through devices, each of which produces logic functional outputs 45. which are predetermined logic functions of the inputs; a seventh rank of flip-flop pass-through devices connected to receive data inputs from said sixth rank to perform an inverting nondelayed Pass-through or a latch function ac- cording to a predetermined function; an output 115 enable rank connected to receive inputs from said third, fifth and seventh ranks of passthrough devices to provide data output for said logic array; and control means connected to all of said functional elements and passthrough devices for controlling and clocking said logic array and for providing latch inputs to set all of said functional elements and said flip-flop pass-throughs to perform a predeter- mined logic function.

2. A logic array as claimed in claim 1 in which each functional element has three data inputs, eight logic control inputs, one data output and is comprised of an eight-to-one multiplexer and eight AND gate/set latch circu- 130 its as inputs to the multiplexer.

3. A soft programmable logic array for performing a preselected logic function on a data input function comprising: a first rank of logic elements each of said logic elements consisting of functional elements having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the func- tion to be performed connected to receive data inputs to said system and a first set of logic signals to set the latches of said first rank of logic elements; a second rank of logic elements connected to said first rank of logic elements, consisting of functional elements each having a plurality of data input receiving lines connected to said first rank, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs to said second rank and a second set of logic signals to set the latches of said second rank of logic elements; a third rank of logic elements connected to said second rank and consisting of flip-flop pass-through devices having means for receiving and latching a third set of logic signals to control the function performed by said pass-through devices; a fourth rank of logic elements each of said logic elements consisting of functional elements each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive inputs from said third rank of passthrough devices, and having means for receiving and latching a fourth set of logic signals to set the latches of said functional elements to perform the pre- determined logic function; a fifth rank of logic elements connected to said fourth rank and consisting of flip-flop pass-through devices having means for receiving and latching a fifth set of logic signals to control the function per- formed by said pass-through devices; a sixth rank of logic elements consisting of functional elements connected to said fifth rank each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs from said fifth rank of pass-through devices and having means for receiving a sixth set of logic signals to set the latches of said functional elements to perform the predetermined logic functions; a seventh rank of logic elements connected to said sixth rank consisting of pass-through devices,each having a plurality of data input re- ceiving lines, at least one data output line and means for receiving and latching control signals representative of the predetermined function to be performed; and an output enable rank connected to receive inputs from said third, fifth and seventh rank of pass-through 8 GB2171826A 8 devices to provide data output for said logic array.

4. A logic array as claimed in claim 3 in which each functional element has three data inputs, eight logic control inputs, one data output and is comprised of an eight-to-one multiplexer and eight AND gate/set latch circuits as inputs to the multiplexer.

5. A logic array as claimed in claim 3 or 4 further comprising control means for providing a serial stream of control signals for input into all of the latches of said functional elements and a strean of latch set control signals to cause the setting of the appropriate latch con- trol signal in the appropriate latch.

6. A logic array as claimed in any of claims 3 to 5 including clock control means to control the gating of the appropriate control signals to the appropriate functional elements in logic rank order during operation of the logic array.

7. A logic array as claimed in any of claims 3 to 6 including a counter arranged to be incremented upon receipt of individual control signals in the input serial data strean and the output count of said counter controls the addressing of said functional elements.

8. A soft programmable logic array substantially as herein described with reference to and as shown in the accompanying drawings.

9. Any novel integer or step or combination of integers or steps, hereinbefore described, irrespective of whether the particular claim is within the scope of, or relates to the same or a different invention from that of, the preceding claims.

Printed in the United Kingdom for Her Majesty's Stationery Office, Dd 8818935, 1986, 4235Published at The Patent Office, 25 Southampton Buildings. London. WC2A 'I AY. from which copies may be obtained.