JPS59200526A - Software programmable logic array - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates specifically to software programmable circuits of the type known as programmable logic arrays.

BACKGROUND OF THE INVENTION In general, programmable logic arrays are implemented in large scale integrated circuits (LSI) or very large scale integrated circuits (VLSI).
) is incorporated into the chip. These programmable logic array chips are of a type in which the specific logic function of the circuit is not defined at the time of manufacture.

A programmable logic array chip is designed such that the logic function of the chip is subsequently determined. Most conventional such chips are programmable by vergeware in that they have fuses or other elements that are permanently blown to determine the logic function of the device. The present invention relates to software programmable devices in that any particular device can be programmed repeatedly with the same or different logic functions by the procedure of inputting logic function data, sometimes known as characteristic data. It is something. For a software programmable logic array to function, characteristic data must be low
Although necessary, a logical array according to the present invention is not simply a storage device. The characteristic data is used to control the particular logic functions to be performed at particular logic levels of the array. Furthermore, according to the invention, each chip has four quadrants on it, viz. It is configured to have four sectors and a control circuit.

Previously, a plurality of word lines and digit lines are shown as inputs to an array with fuses for programmable elements, as disclosed in U.S. Pat.
No. 18.252 is known.

This patent shows a variation of a standard programmable logic array that has two levels of summation that is essentially a product of functions;
Multi-level software programmable logic arrays such as the present invention are not predictable. U.S. Pat. No. 4,233.667 also shows a programmable logic play, from which one cannot expect the structure or performance of the present invention.

U.S. Pat. No. 3,912,914 shows a switching module that can become very complex if any particularly large switching functions are used. This is because program control for any switching function must be done outside the specific chip by individual wires to control the switching function. The present invention is programmed by introducing a set of characteristic data that controls the various logic elements that are the result of a characterization process. Other previously known patents include US Patent No. 3.855.536.

No. 3,976,983 and No. 4,293,783
All of these are related to logic arrays, which either require program control through external logic pins or have limitations on the logic functions that can be performed. That's it.

SUMMARY OF THE INVENTION The present invention provides a software program that can be controlled to perform a particular logic function by providing a set of input characteristic data that is latched into a logic play to cause the programmed logic function to be executed. The purpose is to provide a possible logical array. A logic array according to the present invention is grouped on a single chip into sectors having common program logic for several sectors. In the embodiment of the invention, four sectors are shown.

A logic array according to the present invention is made up of a number of logic levels or stages, each logic level having a plurality of specific logic elements. Embodiments of the invention have eight basic types of logic elements:
Elements of the type are logical functional elements, ie just functional elements.

A functional element has multiple inputs and is capable of performing all possible logical operations applied to these inputs. A particular embodiment of the invention employs a functional element with six inputs and one output as a building j block. This function element has data inputs that are used as control bits for an eight-output multiplexer, the eight inputs of which are latched to control the output function output from the data output of the multiplexer. Represents a blank programmed logic input.

The second type of logic element in the present invention is a pass-and-hold element, which is set to latch a particular input until it is clocked or whatever the data input is. Either that is set to pass that input as its output. In this embodiment, the pass function also has the function of being inverted.

By using four levels of function elements, along with four levels of pass-and-hold function elements with various interconnections of logic between the levels, essentially any logic function output can be generated for multiple inputs. can get. An eighth logic level, output drive and three-state buffer element is provided for complete control of all output logic levels. By interconnecting logic elements at various levels in the logic array according to the invention, a logic function can function at all eight levels or be output as an output at an initial logic level.

In this way, the second . 6th. and the output of the fourth level can be directly dated as the output of the logic array.

BEST MODE FOR CARRYING OUT THE INVENTION In accordance with one embodiment of the present invention, FIGS. 1A, 1B, and 1C arranged from left to right illustrate a detailed diagram of software programmable logic array 10. Represents a logic diagram. Logic data progresses between various logic levels as it enters from the left side of the diagram and exits from the right side of the diagram according to preprogrammed logic functions.

Multiple functional elements 12.14, 16, 18°20.22
．． 24, 26 constitute the first logic level of logic array 10 according to the invention. Functional elements 12 to 26 are all identical, and the structure of functional element 12 is shown in detail in FIG. Each functional element has three data inputs. These data inputs to functional element 12 are shown with numbers appended to A, B, and C to indicate the number of the particular functional element. Similar symbols are used for data inputs to all eight functional elements of the first logic level. Each functional element 12-26 has one output that is interconnected with other portions of logic array 10 as shown in the logic diagram. The second logic level consists of six functional elements 28, 30, 32, 34.36.3
It is composed of 8. These six functional elements 28
38 are six passing and holding elements 40, 42° 44.
Connected to 46.48.50. All of these pass-and-hold elements are identical, and a detailed view of pass-and-hold element 40 is shown in FIG. These six pass and hold elements constitute the sixth logic level of this embodiment of the invention.

The outputs of these six pass φ holding elements are connected together as shown in the logic diagram.

The fourth logic level of this embodiment of the invention consists of four functional elements 52.5 whose inputs are made as shown in the logic diagram.
Consists of 4.56.58.

The outputs of these four functional elements of this fourth logic level are connected to be inputs to four pass and hold elements constituting the fifth logic level. The pass and hold elements 60, 62, 64, 66 constitute a fifth logic level. The 60th logic level has two functional elements 68.7
Consists of 0.

The outputs of the functional elements 68, 70 are, according to the invention, the functional pass elements 72, which constitute the seventh logic level of the embodiment in question.
．． 74. In this logic diagram,
Each functional element has a number prefixed with FE to represent the number of the particular element. Similarly, all passing
Retaining elements are designated by a specific number prefixed with FP.
numbered.

The output logic of the present invention is composed of two-stage elements that can be considered as a single function. The twelfth stage of the two-stage element has an output drive date of 8, which is shown in detail in FIG.
It is 0. Each output drive r-) 80 is connected to a three-state buffer 82 which can produce an output that is ``high'', ``low'', or ``floating''. Assuming that the elements are also connected to the same logic line, it will float depending on the signal level of the output line.Thus, the output function of this embodiment of the invention is 12 output drives/l'-) 80
゜84.88.92.96.100.104.

12 with 108.112, 116, 120.124
determined by the set of output elements. Each output drive date is a 6-state buffer 82°86.90,94,
98,102,106°110.114,118,12
2.126.

The logic arrays shown in FIGS. 1A, 1B, and 1c are preferably arranged in one of four identical sectors or the entire quadrant located on a single VLSI chip. It is constructed as the minus part of the minute. In different embodiments, different numbers of sectors with a common control system are used. In this way, a single VLSI
The chip has four circuits as shown in FIGS. 1A, 1B, and 1C, with a single control circuit as shown in FIGS. 5 and 6. 6th
The figure is configured so that four separate circuits of the type shown in FIGS. 1A, 1B, and 1C can be controlled. The various control lines provided as inputs in FIG. 1A are generated by a control circuit as shown in FIG. 6 and described in more detail below.

The output of the control circuit input to each sector of the logic array is
-t"t-da 1 with 6 human power and 8 outputs shown in Figure 1A
40. Input line (C5゜Cal ”3
) leads from the control element of FIG. Or switch it off. Similarly, the decoder 142 is a two-power, four-output element whose inputs are given from FIG. 6, while the control line (C'8) Turn on or off. - Group Anne V date 144,146゜1
48 controls the fanout of the control signals necessary to low V the program for the programmable logic function to be executed.

FIG. 2 shows a detailed logic diagram for a logic function element 12 of the type used in this embodiment of the invention. Each functional element has an 8-bit input 1-bit output multiplexer 200, where output FD represents the data output. Data inputs are represented by input signal lines A, B, and C.

The signal line is a selection control line for the multiplexer, and constitutes a data input to the functional element.

For each of the eight input lines to the multiplexer,
Untrr-set latch circuit 202゜204.2
06, 208, 210, 212, 214, and 216 are connected. The function input 5 for controlling the function output of the multiplexer 200, that is, the characteristic data input, is the program input (So).
or S, ). The functions of the clear signal and write drive signal are explained in conjunction with the control logic of FIG. Each set latch 202-216, when programmed with a function input, holds that function input for all operations in the circuit. The clear signal clears all dates to zero as part of the initialization process. The write drive signal must be driven to write or program any function.

According to the description of the function of a multiplexer, it is known that an 8-bit input, 1-bit output multiplexer with three control inputs can select any one of the possible inputs as output using a 6-bit control signal. It is being Conversely, it is known that any logic function of six data pits must be either the high order data bit or the low order data bit. By appropriately programming the eight input bits to multiplex clock 200 with high order bits and low order bits, the output of multiplexer 200 can be set to any logic value of the six digit bit inputs provided from control lines A, B, and C. Becomes a function. This then represents the logical structure of the functional element 12 which, according to the invention, acts as a pilling block of the present array.

FIG. 3 schematically shows a detailed logic diagram of the pass-and-hold elements 40, which are all identical in this embodiment of the invention. The passing/holding element 40 is a set/reset amplifier P.
c-Tratch element 220° flip-flop 222. and date 224, all connected as shown. If the set/reset latch circuit 220 is set as a characteristic function role, the data input coming from the previous element is
4, the circuit functions as a data passing circuit,
Then, it passes through and inverts the VC-F'-tar without a large time delay. If the set/reset latch circuit 22
In order for data to pass through the circuit, when 0 is not set, the clock signal, in addition to the data input, must start flip-flop 222 so that date 224 passes the data.

As shown in FIG. 4, the output drive circuit 80 includes r
- It consists of a set/reset latch circuit together with the gate 232. If the output of output drive date 232 is on, the buffer goes high or low in response to the data input to the buffer. If the output drive line of output drive date 232 is not driven, the associated buffer will be off or floating, regardless of data input. The input control lines to output drive date 232 function as follows.

H holds /7''-), that is, it is forcibly turned off.

F is the test input that forces the output, and E is the normal drive function input.

In Figure 5, as shown in Figure 1C,
A control system register 281 is shown that generates the FORCF control function for FORCF 3, and similarly for other similar sectors, respectively.

In FIG. 6, a control circuit according to the invention is shown as one of four identical circuits for controlling the circuits of FIGS. 18-1C. The control circuit 300 has a control clock 302.

A series of input characteristic data is provided at input 304.

A set of input test data is provided in a standard computer environment as a function of a test maintenance logic system outside of the normal data path, in the role of an initialization function. The clock 302 performs set, clear, and forget functions. That is, it provides a one-shot signal that controls the rear bits coming out of the clear output 306 so that all circuits are initially cleared. However, since the one-shot signal is formed, the clear signal There is no need for it to be erased; it will disappear automatically.

Decoder 308 acts in conjunction with counter 310 to provide an 8-bit output channel for the various functional elements 12 that commonly controls the operation of r-to. Thus, the continuous flow of input data applied to the 1-bit channel is controlled by the counter 310 in conjunction with the decoder 308 so that the 8-bit output select channel 310 allows the output of the 8-bit output select channel 310 to Each functional element in turn triggers its program input. A counter 312 is shown in FIG. 1A to control which selected logic for which function element 12 or which passing fist holding element 40 is activated in response to an address specification of a program function. Give an output control signal to line C. The counter also
Controls which output drive element is designated as voltageless.

FIG. 7 shows a simplified version of the logic diagram according to the present invention as shown in FIGS. 1A, 1B, and 1C. Logic elements are only represented symbolically, and various program and control function lines are not shown.

0 Thus, reference numbers 12, 14. 16, 18° 20.
22.24.26 are used to indicate functional elements in FIG. 7 as well as in FIG. 1A. This is to make elements and functions correspond.

Thus, FIG. 7 shows the same logic system shown in FIGS. 1A, 1B, and 1C, with eight logic levels and output levels determined by software. A siprogrammable logic array 10 is configured. One major difference between the two figures is that the two-stage output element shown in Figure 1C is replaced by the two-stage output element shown in Figure 7.
It is simplified to a single output element. Thus, the combined output drive date and six-state buffer elements in FIG. 7 correspond to the six-state buffers 82, 86, . . . , 126 shown in FIG. are respectively numbered 82A.

86A, . . . , 126A.

A software programmable logic array is designed in accordance with the present invention to solve one of the recurring problems in logic design, namely the problem that "haunts" systems in simple control functions. This is to distinguish it from important arithmetic functions such as adders and multipliers, which are usually specially designed. Although, according to the present invention, the logic array is designed to implement the function of add-squaring, it is generally not effective. Logic arrays, according to the present invention, are most effective in performing the type of discrete, residual, or "trailing" functions necessary to complete the arithmetic logic or pool algebraic operation system in a computer. For example, if a computer system has four separate 16-bit adders or multipliers operating separately at 16 bits, then the four separate systems can be It is useful to use a software programmable logic array to provide bit-operated control and logic functions.The software programmable logic array runs the entire control section of the computer's mainframe. It is not intended to be used as such.

A dedicated microcoor V and a dedicated arithmetic or sol function itself are useful for the design. Instead, software programmable logic arrays work well for functions such as overflow detection in arithmetic logic units or control distribution for using six-state buses.

Traditionally, fuse technology has been used to create programmable logic arrays. However, it is not economically advantageous to incorporate fuse-type programmable logic arrays into very large scale integrated circuits. The present invention meets this need by providing one of a combinational function or an ordinal logic function that can be selected and used in conjunction with the user as a result of the characteristic data.

According to the invention, the basic functional element of the logic array is a logic unit or functional element 12 that can be configured to perform any logic function having three inputs.

The logic levels or stages of many of these elements are
They are connected to form a logical array as a whole. A first stage of these elements is coupled to an input pin and the output of the first level of the functional element drives the next successive stage of the functional element.

In the disclosed embodiment of the invention, there are four separate groups of functional elements. According to this embodiment of the invention, there are four separate groups of logical arrays on one VLSI chip, and each array is one of four identical copies, so one sector or Let's call it the -quarter part. Within each quarter or sector of the array, there are 24
There are 8 functional elements connected to 8 input pins.

The second logic level or stage has six functional elements, the sixth logic level or stage has four functional elements, and the last or fourth At the logic level or fourth logic level, there are two functional elements. The outputs of all function levels of the second and subsequent stages are connected to the chip output pins as well as to the outputs for feeding the next output level. This allows the user to use different combinations of functional elements at different levels in the logic array.
This means that up to 6 suitably simple logical expressions, or 12 mixed logical expressions, or up to 2 complex logical expressions can be handled. Figures 1A, 1B, and 1
The most complex expressions that can be programmed in a given logic array of the type shown in Figure C can span up to 7 functional elements with 21 input pins.

Except for the first stage functional element, the output of each functional element in each stage includes a selectable flip-flop or pass-through.
There is a holding element. Each flip-flop can be selected to function as a single-cycle holding register or to pass data directly through with minimal delay without latching the data. Each flip-flop has an input connected to it that forces all seven flip-flops to clear under test system control.

Each chip output pin is connected to an output element that controls a six-state control line for each output pin of the buffer. The user can force the output pin to be driven at all times. That is, the input pins associated with each of the four sectors can not only be driven to control the six-state line of each output pin of the sector, but the data output can never be turned off.

Each functional element, such as element 12, has an eight-power single-output multiplexer driven by eight memory latches and three selection inputs A, B, and C, the memory latches and selection inputs for the outputs of the multiplexer. It is decoded to select the state of one latch. Eight data latches are input A.

B, C are set to perform the desired logic function;
cleared. The eight data latches constitute a complete truth table for the three inputs. Therefore, by setting and clearing the required data latches,
Any 6-bit logic function is executed. As a simple example, FD = A x B * C is created by clearing all data latches except the one associated with the program input (S7) which is set. Truth tables for any required logical function are easily constructed by several well-known logical methods.

All latches are activated by circuitry controlled from the management system shown in FIG. All latches are cleared simultaneously and then set sequentially depending on the condition of the data coming into the test data output bin 304. Within each functional element, latch bit 0 is set first, latch bit 7 is set last, and so on.

As shown in FIG.
It is a two-power, single-output multiplexer controlled by the same latch bits as .

The latch bit 202 is also similarly controlled by the system control function 7 provided by the apparatus in FIG. If the latch bit is cleared, the input data from the driving function element is passed directly to the output of the multiplexer, so if
It is passed to the output bin and the next following function element, if any. In this case, the data is inverted.

This must be taken into account when writing logical expressions for successive levels of functional elements. If the latch bit is set, the output of the flip-flop is connected to the output of the multiplexer.

It should be noted that in this case the data is not inverted as it goes from the input to the output as in the case of direct pass. This change in reversal between the flip 70 mode r and the passing mode V does not pose any problem. This is because the data latch is an element that performs writing once only under conditions where the voltage has increased. This way, it cannot change during use. The fact that the data is inverted can be taken into account when generating the logical complement of the required logical function in the functional element driving a particular input.

Flip-flop 222 is continuously clocked without being controlled by any date. This means that in order to construct a state-sequential circuit, the output of the function must be connected to a chip input as an input for defining a logical formula. The data flip-flop is powered by a reset input output from the management control system shown in FIG. 6, which can be utilized to start the flip-flop for use or testing. The output drive element 80 shown in FIG. 4 is connected to the three-state control line of each function output bin. The output drive has six different operating modes.

The first modulus of the output drive is a data bit of storage which, if set,
Holds each six-state control line to output drive high unless the output bin can be forced off by the Output Disable Hold Stop bus.

The second condition for operation is that if the data bit is cleared, the common input/output bin for each output drive element within a sector can control a 6-state control line.

A high level in this bin will drive all output buffers and corresponding logic arrays in the sector, except when the hold-stop path can regain control of the drive line.

In the sixth operation mode P, each output within a sector is
It can be forced on to be output driven by a function bit in the control system register 281 shown in FIG. Thus, there are four individual control bits. Although it is generally desired that this device be used for maintenance, it may also be used for system operation. The control system interface functions shown in FIG. 6 are integral to the software programmable logic array and provide characteristic data numbers for initialization.

This is because the array is functional only when the maintenance system rows the data latches that describe the selected logical function.

The data latches that perform the required logic functions are first brought low by clearing all data latches in all sectors, and then each latch is individually driven, if necessary, by data coming from the test data input. By setting it, it is set to low P. On the chip is a bit counter that counts from 0 to 767. Of the 768 counts, 766 are bit latches for the 184 latches in each sector, plus 8 extra counts in each sector. If the test data input bit is 1, each function latch is set and the counter is incremented. This counter simply increments by one count if the input bit is 0. The function bit description for the control function is as follows. If the Teststro input bin is activated and bit 1 of the control register is set, the WRI
TEF function is activated. This WRITEF must operate to enable writing to the function description latch. WRITEF can be set with the same control word as INITF and CLEARF. When WRITEF is active and the test clock drive input bin is at a high level, the state of the test data input pin is written to the latch that is currently designated as AVless.

If the test strobe input bin is activated and bit 2 of the control register is set, the INITF function is activated.

INITF performs two functions. That is, first, INITF clears to zero the amares counters that select individual function latch bits. And secondly, I
NITF' also clears all intermediate state 7 lip-flops in all four sector logical arrays. INITF is a one-shot function in that it is activated for only one clock at the leading edge of the test strobe that is activated.

This means that this function can simplify the control sequence required to write a function description latch with the same function control word as WRITEF. This is done by holding the test clock drive control line low or inactive when the test strobe is at a high level. After a delay of at least two clock cycles, the test clock drive goes high and the write latch is written.

0LE when bit 6 of the control register is set when the test strobe input is activated.
The ARP function is activated. CLEAR clears all function description latches in all sectors to zero.

This must be done on voltage rise when the logic array is being written for the first time, and can be done at other times to change the chip function. 0LEARP is not needed if a write latch holding a zero is required to be changed to a one. WRITEF・I
The NI'rF function is used with a series of data that are all zero except for the zero case at the desired location change. 0LEARP is a one-shot function in that it operates only for one clock cycle at the leading edge of the test strobe when it is active. This means that this function can provide the necessary control order to write the function description latch with the same function control word as ITEF. This is done by holding the test clock drive low when the test strobe is at a high level.

After a delay of at least two clock cycles, the test clock drive goes high and the write latch is written.

The four functions FORCEFO through FORCEF'3 each represent bits 4,5,6,7 of control register 281 and force all output bins in their respective sectors to operate. This function governs the state of the output drive pin, the hold-stop path, and the state of any function description latches in the output drive date. Although these function bits are expected to be used primarily by diagnostics, they are still used in normal system operation. The four bits are
Pulled low to a static holding register on the leading edge of the test clock drive signal.

The BLOCKF function is active when bit 8 of the control register is active when the test strobe input is active. BLOCKF inhibits all output pins in all sectors. This function governs the state of any function description latches on the output drive pins and any output drive elements. BLOCKF forces the hold-stop path into inhibit mode. BLOCKF does not dominate the FORCEF function in any active state.

Logic arrays have several favorable properties according to the present invention. First, a logical array is configured for the function being executed. If a portion of the array is moved from one location in the system to another, the array executes the logical expressions for the new location without physically changing the portion. . The delay of the logic signal through said section is proportional to the complexity of the logic expression being executed. Several simple or somewhat complex equations can be implemented, thus giving the logic designer a degree of freedom. The logic array performs a variable function within a fixed set of inputs, whereas traditionally it performs a fixed formula for variable input. Flip-flops, which are part of the logic circuit, can be used to implement state equations and can be inhibited to implement combinatorial logic.

The first level functional element feeds into the second level functional element. Each second level functional element drives its own output pin or is fed into a sixth level functional element, which drives an output pin. This time, the sixth level drives the output of the fourth level. Because of this interconnection, the array can operate all outputs of the second level of the furnace so that up to six suitably simple equations can be solved within the array.

6. The more complex a large equation becomes, the 6th and 4th level elements can be used such that the elements of the first and second levels play the role of the logic equation more and more, thereby , can solve increasingly complex logical equations.

Solutions of both logic types are available simultaneously.

In other words, some simple logic equations produce signals that can still be input into more complex logic equations. The second and sixth level outputs are activated at the same time as the third and fourth level outputs are activated, so that simple and complex logic functions are created simultaneously. By selecting the state of whether a pass/hold element retains data or still passes data, some logical formulas can be state formulas, while others can be purely combinatorial formulas. .

[Brief explanation of drawings]

1A, 1B, and 1C, arranged from left to right, are block diagrams of detailed programmable logic arrays in one embodiment of the present invention;
FIG. 2 is a detailed logic diagram of one of the functional elements according to the present invention shown in FIGS. 1A, 1B, and 1C; FIG. FIG. 1C shows a detailed logic diagram of the pass-through and retaining element according to the invention; FIG. 4 shows a detailed logic diagram of the output drive wheel mount according to the invention, shown in FIG. 1C; 5 is a logic diagram of a control circuit according to the present invention for the logic system shown in FIGS. 1A, 1B, and 1C; FIG. 6 is a logic diagram of a control circuit shown in FIGS. 1A-1C; FIG. 7 is a logic diagram of a control circuit for the characteristic logic used to drive the system according to the invention, which is a simplification of the system according to the invention shown in FIGS. 1A to 1C. This is a logical diagram that shows only basic logical interconnections. 10...Logic array, 12.14,16,18°20
．． 22, 24, 26, 28, 30.32°34.36,
38.52, 54, 56.58° 68.70...Function element, 40.42, 44, 46° 4B, 50, 60, 6
2,64,66.72°74... Passing/holding element, 8
0.84.88.92゜96.100,104,108
, 112, 116° 120.124... Output drive date, 82, 86° 90.94, 98, 102, 106,
110゜114.118,122,126...6-state buffer, 200...Multiplexer, 202.20
4. 206. 208. 21 0. 212. 21 4
. 216... Latch circuit, 300... Control circuit, (A
. B, C) - Data input, (So + Sl 1
S21 S31S4 + ”5 + 86+ 87
)...Program input, (FD)...Output agent Asamura Ko 9 2F-ZZ = older brother; 2, 1-

Claims (1)

[Scope of Claims] (1) A logic array programmable by software, comprising: (a) a plurality of logic stages, each of which is constituted by a functional element, having a logic input; R and a logic output that is a predetermined function of the input, each of the functional elements having an input connected to receive a data input and a data output representing a logic expression of the data input. , that is, each of the eight functional elements has an input connected to the output such that at least one output can be any logical function of the plurality of inputs, and each of the functional elements has: a logic stage having a plurality of latches equal to the number of possible output states to hold predetermined logic instructions for the associated output states corresponding to said logic function to be executed; ) a plurality of stages, the stage having an input connected to receive an output of one of the logic stages, and an input of another of the logic stages and an output of the logic array. Consists of flip-flop pass elements with outputs connected to υ, each of which is
(c) inverting a logic condition and passing the inverted condition without delay or latching the logic condition until released, according to a predetermined logic function to be performed; Logic array characterized in that it comprises control means for setting all of said functional elements and said flip-flop pass elements to perform a predetermined logic function. (2. In claim 1, (a) a first logic stage consisting of eight functional elements connected to receive system data input; (b) an output of said first logic stage; (c) a sixth stage consisting of six Noritub flop pass elements connected to the output of said second logic stage; ) a fourth logic stage consisting of four functional elements connected to the output of the sixth stage; (e) four 7 flip-flop pass elements connected to the output of the fourth logic stage; (a) a sixth logic stage consisting of two functional elements connected to the output of said fifth stage; (g) connected to the output of said sixth logic stage; an eighth stage consisting of twelve output drive gates connected to the outputs of the sixth, fifth and seventh stages; (3) In claim 2, each output drive unit 9
- The output of the motor is forced to be high with one mode P. A logic array characterized in that it can be made low or floating or connected to an input function as an output in the operation of another motor. (4) In claim 2, each functional element is 6
A logic array having eight data inputs, eight logic control inputs, and one output. (5) As set forth in claim 4, each functional element is characterized by comprising an eight-power single-output multiplexer and eight unlegged set latch circuits connected as inputs to the multiplexer. logical array.