JPS59115524A - Formation of electrode for semiconductor device - Google Patents

Formation of electrode for semiconductor device

Info

Publication number
JPS59115524A
JPS59115524A JP57234505A JP23450582A JPS59115524A JP S59115524 A JPS59115524 A JP S59115524A JP 57234505 A JP57234505 A JP 57234505A JP 23450582 A JP23450582 A JP 23450582A JP S59115524 A JPS59115524 A JP S59115524A
Authority
JP
Japan
Prior art keywords
electrode
heater
wire group
group
pressure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57234505A
Other languages
Japanese (ja)
Inventor
Akira Shibata
芝田 章
Yoshiyuki Nagahara
美行 永原
Toru Nunoi
徹 布居
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP57234505A priority Critical patent/JPS59115524A/en
Publication of JPS59115524A publication Critical patent/JPS59115524A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to form an electrode and a lead wire at the same time by performing a simple process by a method wherein a thin metal wire group for electrode is placed on the surface of a semiconductor element and heat and pressure are applied. CONSTITUTION:An N type diffusion layer 11 is formed on a P type Si substrate 10 and, at the same time, a solar battery element 13 whereon the lower electrode 12 is formed is arranged between a base heater 14 and the upper heater 15 when the upper electrode forming process is performed in such a manner that the electrode 12 is facing downward. Then, a fine metal wire group 16 is placed on the surface of the element 13 in such a manner that it is covering the whole surface. The heater 15 is brought down in the direction shown by the arrow P in the diagram maintaining the positional relations as above-mentioned, and pressure is applied on the element 13. As a result, the contacted part of the element and the fine wire group 16 is heated up by the heaters 14 and 15, and the fine wire group 16 is electrically and mechanically connected to the surface of the element 13. According to this method, the electrode can be formed by performing a heating and pressurizing process only, and besides a lead wire can be formed simultaneously, thereby enabling to cut down the manufacturing time remarkably.

Description

【発明の詳細な説明】 く技術分野〉 この発明は半導体装置の電極形成方法に関し、特に太陽
電池の製造方法に好適な電極形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method of forming electrodes for semiconductor devices, and particularly to a method of forming electrodes suitable for manufacturing methods of solar cells.

〈従来技術〉 従来、太陽電池の電極形成は、真空蒸着法または導電性
ペーストの印刷方法によって行っていた。しかし、真空
蒸着法は時間、コストの点で低価格、大量生産を指向す
る上で不向きであり、また蒸着金艮のロスが大きいとい
う欠点があるため、現在は導電性ペーストの印刷方法が
主流になりつつある。第1図に典型的な導電性ペースト
印刷方法を示す。まず、シリコンウェハ1の下面にAl
ペースト2を印刷、焼成する(工程(八))。Alペー
スト2の下面に形成されるダス[・3は焼成段階で形成
される酸化膜である。続いて化学的に或いは物理的にダ
スト3を除去しく工程(B))、さらに、半田イ」けを
可能にするため、露出したへ1ペースト2上にAgペー
スト4を印刷しく工程(C) )、乾燥、焼成する(工
程(D))。以上の工程を経たのち、Agペースト4−
1−にリード線5を半田6で半田付けして結線を完了す
る(工程(E))。このように導電性ペーストを用いる
従来の電極形成方法は、真空工程が不要であるため時間
的、コスト的に真空蒸着法に比べて有利であり、また材
料の無駄がないという利点がある。
<Prior Art> Conventionally, electrodes of solar cells have been formed by a vacuum evaporation method or a conductive paste printing method. However, the vacuum evaporation method is unsuitable for low prices and mass production in terms of time and cost, and also has the drawback of large losses of evaporated gold, so currently the printing method of conductive paste is the mainstream. It is becoming. FIG. 1 shows a typical conductive paste printing method. First, Al is placed on the bottom surface of the silicon wafer 1.
Print and bake paste 2 (step (8)). The dust 3 formed on the lower surface of the Al paste 2 is an oxide film formed during the firing step. Next, there is a step (B) in which the dust 3 is chemically or physically removed, and a step (C) in which Ag paste 4 is printed on the exposed paste 2 to enable soldering. ), drying and firing (step (D)). After going through the above steps, Ag paste 4-
The lead wire 5 is soldered to the wire 1- with solder 6 to complete the wiring connection (step (E)). As described above, the conventional electrode forming method using a conductive paste is advantageous in terms of time and cost compared to the vacuum evaporation method because it does not require a vacuum process, and also has the advantage that there is no wastage of materials.

しかしながらこの方法はペーストの印刷、焼成。However, this method involves printing and baking the paste.

および半田付けの工程が必要であるため、工程が複雑化
する欠点があるとともに十分なコスト低減を実現するこ
とが出来なかった。
Moreover, since a soldering process is required, there is a drawback that the process becomes complicated, and a sufficient cost reduction cannot be achieved.

〈発明の目的〉 この発明の目的は、極めて簡単な工程で電極の形成とリ
ード線の形成とを同時に行うことが出来る半導体装置の
電極形成方法を提供することにある。
<Objective of the Invention> An object of the present invention is to provide a method for forming electrodes of a semiconductor device, which allows forming electrodes and forming lead wires at the same time in extremely simple steps.

〈発明の構成〉 この発明は、PN接合部の形成された半導体素子の表面
に、ワイヤクロス(金属メソシュ)等の電極用金rr5
釧線群を載・已て加熱、加圧することによって、前記金
属細線群を半導体素子面に接続することを特徴とする。
<Structure of the Invention> This invention provides electrode gold rr5 such as wire cloth (metal mesh) on the surface of a semiconductor element in which a PN junction is formed.
The method is characterized in that the group of fine metal wires is connected to the surface of the semiconductor element by placing and applying heat and pressure to the group of wires.

第2図は、この発明の電極形成方法を説明する図である
。。
FIG. 2 is a diagram illustrating the electrode forming method of the present invention. .

P型シリコン基板10上にN型拡散層11が形成される
とともに、AI?ペーストを印刷することによって形成
された下部電極12を有する太陽電池素子13は、上部
電極の形成する工程において、図示するように、ベース
ヒータ14と上部ヒータ15との間に下部電極12を下
側にして配置される。そして、素子13の表面に素子1
3の表面全域を覆うようにして、金属細線群16が載置
される。以上の位置関係を保って、上部ヒータ15を矢
印P方向に下げ、素子13を一定の圧力で押圧する。そ
うすると素子13と金属細線群16との接触部がヒータ
14.15によって加熱され、一定の時間の加熱、加圧
によって金属細線群16が電気的および機械的に素子1
3の表面に接続する。十分なオーミック接触を得られた
段階で、ヒータ15を矢印Pと逆方向に引き上げること
によって、上部電極の形成が完了する。なお、この場合
において、素子13の表面はシリコン素面であっても良
いし、またリンチタネートガラス(P”FG)やシリグ
ー1〜ガラス(SG)等の絶縁薄膜が形成されていても
良いし、またインジウムティンオキサイド(TTO)や
SnOユ等の透明導電薄膜が形成されていても良い。
An N-type diffusion layer 11 is formed on a P-type silicon substrate 10, and an AI? In the step of forming the upper electrode, the solar cell element 13 having the lower electrode 12 formed by printing paste has the lower electrode 12 placed between the base heater 14 and the upper heater 15 on the lower side as shown in the figure. It is placed as follows. Then, element 1 is placed on the surface of element 13.
A group of thin metal wires 16 is placed so as to cover the entire surface of the metal wires 3. While maintaining the above positional relationship, the upper heater 15 is lowered in the direction of arrow P, and the element 13 is pressed with a constant pressure. Then, the contact portion between the element 13 and the metal wire group 16 is heated by the heater 14.15, and by heating and pressurizing for a certain period of time, the metal wire group 16 is electrically and mechanically connected to the element 1.
Connect to the surface of 3. When sufficient ohmic contact is obtained, the heater 15 is pulled up in the direction opposite to the arrow P, thereby completing the formation of the upper electrode. In this case, the surface of the element 13 may be a bare silicon surface, or may be formed with an insulating thin film such as lintitanate glass (P"FG) or silicone glass (SG), Further, a transparent conductive thin film such as indium tin oxide (TTO) or SnO may be formed.

〈発明の効果〉 この発明によれば、加熱、加圧工程だけで簡単に電極が
形成出来、しかも同時にリード線も形成されるため、電
極形成と配線用のリード線の半田付りを別々に行う必要
がなくなり、製造時間が極めて短縮される。また、工程
が減ることによって大規模な設(Rtiが不要になり、
電気、ガス等の間接材料費が極端に減る利点があるとと
もに、特別な雰囲気を必要とせず、通常の空気中で電極
形成を行うことが出来/り。さらに金属細線群を使用す
るため、リード線の取りイ」け位置を予め決める必要が
無い利点がある。
<Effects of the Invention> According to the present invention, electrodes can be easily formed by only heating and pressurizing processes, and lead wires are also formed at the same time, so electrode formation and soldering of lead wires for wiring can be performed separately. This eliminates the need for this process, significantly reducing manufacturing time. In addition, by reducing the number of processes, large-scale installation (Rti) is no longer required,
It has the advantage of drastically reducing indirect material costs such as electricity and gas, and electrodes can be formed in normal air without requiring a special atmosphere. Furthermore, since a group of thin metal wires is used, there is an advantage that there is no need to decide in advance where the lead wires are to be taken.

〈実施例1〉 Jtff:O、(15mm、線幅0.1m+r+、開[
1率約90%のへlエキスバンドメタル16aを用言す
る。第31m(C)にこのエキスバンドメタル16aの
部分拡大図を示す。次に予めP型シリコン基板10上に
接合深さ約0’、3.umのN型拡散層11を形成する
とともに、下部電極としてP型基板IO十にAgペース
トを印刷した素子13を準備する。そしてこの素子13
を約300°Cに温度調節されたベースヒータ14上に
、N型Ftllを上にして置き、エキスバンドメタル1
6aをその上に重ねる。次に約300℃に温度調節した
」二部ヒータ15を素子13に加わる圧力が約300k
g/ C+aとなるようにして1分間加圧する。以上の
工程を実行すると、N型層11とエキスバンドメタル1
6aの間に良好なオーミック接触が得られ、機械的強度
も大であった。この素子の電流−電圧特性をAMCエア
ーマス)1ソーラシユミレータにより測定したところ0
.70のフィルファクタを得ることが出来た。
<Example 1> Jtff: O, (15 mm, line width 0.1 m+r+, open [
An expanded band metal 16a with a ratio of about 90% is used. No. 31m (C) shows a partially enlarged view of this expanded metal 16a. Next, the bonding depth is approximately 0' on the P-type silicon substrate 10, and 3. An element 13 is prepared in which an N-type diffusion layer 11 of um is formed and Ag paste is printed on a P-type substrate IO1 as a lower electrode. And this element 13
Place the N-type Ftll on top of the base heater 14 whose temperature is adjusted to about 300°C, and place the expanded metal 1
Layer 6a on top. Next, the temperature was adjusted to about 300 degrees Celsius, and the pressure applied to the element 13 was about 300 k
Pressurize for 1 minute at g/C+a. When the above steps are executed, the N-type layer 11 and expanded metal 1
6a, good ohmic contact was obtained, and the mechanical strength was also high. The current-voltage characteristics of this element were measured using an AMC air mass) 1 solar simulator and were found to be 0.
.. A fill factor of 70 was obtained.

〈実施例2〉 P型シリコン基板10上にリンチタネートガラス(PT
G)液を塗布し、920℃で20分の熱処理を行い、接
合深さ0.3μm程度のN中層および反射防止膜として
のPTGl*17を同時に形成した(第4図参照)。P
TG膜17は、厚みが約800人の透明な絶縁膜である
。P型基板lOには、Agペーストにて下部電極12を
付けた。
<Example 2> Lintinate glass (PT) was deposited on the P-type silicon substrate 10.
G) solution was applied and heat treated at 920° C. for 20 minutes to simultaneously form an N intermediate layer with a junction depth of about 0.3 μm and PTGl*17 as an antireflection film (see FIG. 4). P
The TG film 17 is a transparent insulating film with a thickness of approximately 800 mm. A lower electrode 12 was attached to the P-type substrate IO using Ag paste.

次に上記実施例1で用いたAIエキスバンドメタル16
aをPTG膜1膜上7上ね、ベースヒータ14、上部ヒ
ータ15とも約300℃に温度調節し、加圧内約300
1(H/ clで1分間加熱したところ、A1エキスバ
ンドメタル1(iaはPTG絶縁膜17を突き破り、良
好なオーミック接触を得ることが出来た。この素子の電
流−電圧特性をΔM1ソーラシュミレータにより測定し
たところ、0.74のフィルファクタが得られた。
Next, AI Exband Metal 16 used in Example 1 above
The temperature of both the base heater 14 and the upper heater 15 was adjusted to about 300°C, and the pressure was set at about 300°C.
1 (H/Cl) for 1 minute, the A1 extended metal 1 (ia) broke through the PTG insulating film 17 and was able to obtain good ohmic contact. The current-voltage characteristics of this element were measured using a ΔM1 solar simulator. When measured, a fill factor of 0.74 was obtained.

〈実施例3〉 P型シリコン基板10上に接合深さ0.3.+1mのN
型拡1&1Ftllを形成し、また、P型シリコン基板
10にΔGペース1〜の下部電極12を付りる。さらに
N型拡1tk、層11の上に透明導電性膜のITo膜1
8を蒸着形成する(第5図参照)。ITO膜18は反射
防止膜および素子の直列抵抗成分軽減のために設りるも
ので、シー[抵抗50〜100Ω10である。次に板#
0.05mm、線幅0.1mm、開口率93%のAIエ
キスパン1′′メタル暑6aをド1゛0膜I8の上に重
ね、ベースヒータ14.上部ヒータ15とも200°c
に温度調節し、加圧内約20 (l k g / c、
Iで一分間加圧したところ良好なオーミック接触と強固
な接着力を得ることが出来た。この素子の電流−電圧特
性をAM1ソーラシュミレータで測定したところ0.7
4のフィルファクタを得ることが出来た。
<Example 3> A junction depth of 0.3. +1m N
A mold expansion 1&1Ftll is formed, and a lower electrode 12 of ΔG pace 1~ is attached to the P-type silicon substrate 10. Furthermore, an ITo film 1 of a transparent conductive film is formed on the N-type expansion 1tk and the layer 11.
8 is formed by vapor deposition (see FIG. 5). The ITO film 18 is provided as an anti-reflection film and to reduce the series resistance component of the element, and has a resistance of 50 to 100 Ω10. Next board #
An AI expander 1'' metal heater 6a with a diameter of 0.05 mm, a line width of 0.1 mm, and an aperture ratio of 93% is overlaid on the base heater 14. Both upper heaters 15 and 200°C
Adjust the temperature to about 20 (l kg/c,
When pressure was applied for one minute at I, good ohmic contact and strong adhesive strength were obtained. The current-voltage characteristics of this element were measured using an AM1 solar simulator and were found to be 0.7.
A fill factor of 4 was obtained.

〈実施例4〉 実施例2の工程において、裏面をP型シリコン素面のま
まとし、P T G膜17およびP型シリコン基板10
の両側に上記実施例1,2で用いたAIエキスバンドメ
タル1’ 6 aを接触しく第6図参照)、ベースヒー
タ14.上部ヒータ15とも300℃に温度調節した後
、加圧内約300kg/cmlで加圧した。この素子の
電流−電圧特性はAMlソーラーシュミレータによる測
定によると0゜69のフィルファクタであり、接着力も
非常に強固であった。
<Example 4> In the process of Example 2, the back surface is left as a P-type silicon bare surface, and the PTG film 17 and the P-type silicon substrate 10 are
(See FIG. 6) and the base heater 14. After adjusting the temperature of both upper heaters 15 to 300° C., the pressure was applied to about 300 kg/cml. The current-voltage characteristics of this element were measured using an AMl solar simulator, and the fill factor was 0.69, and the adhesive strength was also very strong.

〈実施例5〉 実施例4で用いた全く同し素子を、Δlエキスパン]−
メタル16aの代わりに直i¥80μmのΔlワイヤ1
6b(第3図(A)参照)を約2mm間隔で直線状に配
置した(第7図参!!6 )。実施例4と同条件で加熱
、加1騙シたところ、電流−電圧特性で0.70のフィ
ルファクタを得ることが出来、接着力も強固であった。
<Example 5> Exactly the same element used in Example 4 was subjected to Δl expansion]-
Direct I¥80μm Δl wire 1 instead of metal 16a
6b (see FIG. 3(A)) were arranged in a straight line at intervals of about 2 mm (see FIG. 7!!6). When heated and heated under the same conditions as in Example 4, a fill factor of 0.70 was obtained in terms of current-voltage characteristics, and the adhesive strength was strong.

以上五つの実施例を上げたが、接着する電極と接着され
る素子側とで種々の組合せが可能である。電極側では形
状的にワイー1’1(ib(第3図(A) 参照) 、
 ワ・イヤを織ったクロスマル(−1・16c(第3図
(B)参照)、エキスバンドメタル16a(第3図1(
C)参照)等があり、材質的にばΔl、Ag、Ni、八
u、CuおよびCIlのNiメ・ツキ等、各種メッキ品
等がある。また、接着される素子においても、シリコン
を例にとれば、シリコン素面が露出した素子、リンチタ
ネートガラス(PTG)、  リンシリケートガラス(
PSG)、チタネートガラス(1’G)、シリケートガ
ラス(SG)等の絶縁体薄膜、ITo、5n02等の透
明導電M膜がウェハ面に形成された素子等がある。
Although the five embodiments have been described above, various combinations of the electrodes to be bonded and the elements to be bonded are possible. On the electrode side, the shape is 1'1 (ib (see Figure 3 (A)),
Cross maru (-1.16c (see Fig. 3 (B)) woven with wire and wire, extended band metal 16a (Fig. 3 (1))
In terms of materials, there are various plated products such as Δl, Ag, Ni, 8U, Cu, and CIl (Ni-plated). In addition, in the case of elements to be bonded, taking silicon as an example, there are elements with exposed silicon surfaces, lintitanate glass (PTG), phosphosilicate glass (
There are elements in which an insulating thin film such as PSG), titanate glass (1'G), or silicate glass (SG), or a transparent conductive M film such as ITo or 5n02 is formed on the wafer surface.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電極形成方法を工程順に示す図である。 第2図はこの発明の電極形成方法を説明する図である。 第3図は金属細線群の具体例の部分拡大図である。 第4図〜第7図はそれぞれこの発明の詳細な説明する図
である。 13−太陽電池素子、  14−ベースヒータ、15−
上部ヒータ、  16  (16a、16b、16C)
−金属細線群。 出願人  シャープ株式会社 代理人  弁理士 小森久夫 11図 喚3図
FIG. 1 is a diagram showing a conventional electrode forming method in order of steps. FIG. 2 is a diagram illustrating the electrode forming method of the present invention. FIG. 3 is a partially enlarged view of a specific example of a group of thin metal wires. FIGS. 4 to 7 are diagrams each explaining the present invention in detail. 13-Solar cell element, 14-Base heater, 15-
Upper heater, 16 (16a, 16b, 16C)
- Group of thin metal wires. Applicant Sharp Co., Ltd. Agent Patent Attorney Hisao Komori Figure 11 Figure 3

Claims (1)

【特許請求の範囲】[Claims] +11PN接合部の形成された半導体素子の表面に電極
用金属細線群を載せた後、前記素子に対して前記金属細
線群を加熱、加圧することによって、前記金属細線群を
半導体素子面に接続することを特徴とする半導体装置の
電極形成方法。
After placing a group of thin metal wires for electrodes on the surface of the semiconductor element on which the +11PN junction is formed, the group of thin metal wires is connected to the surface of the semiconductor element by heating and pressurizing the group of metal thin wires with respect to the element. A method for forming electrodes of a semiconductor device, characterized in that:
JP57234505A 1982-12-22 1982-12-22 Formation of electrode for semiconductor device Pending JPS59115524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57234505A JPS59115524A (en) 1982-12-22 1982-12-22 Formation of electrode for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57234505A JPS59115524A (en) 1982-12-22 1982-12-22 Formation of electrode for semiconductor device

Publications (1)

Publication Number Publication Date
JPS59115524A true JPS59115524A (en) 1984-07-04

Family

ID=16972075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57234505A Pending JPS59115524A (en) 1982-12-22 1982-12-22 Formation of electrode for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59115524A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5474621A (en) * 1994-09-19 1995-12-12 Energy Conversion Devices, Inc. Current collection system for photovoltaic cells

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5474621A (en) * 1994-09-19 1995-12-12 Energy Conversion Devices, Inc. Current collection system for photovoltaic cells
WO1996009650A1 (en) * 1994-09-19 1996-03-28 Energy Conversion Devices, Inc. Current collection system for photovoltaic cells

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