JPS59115522A - Formation of electrode for semiconductor device - Google Patents

Formation of electrode for semiconductor device

Info

Publication number
JPS59115522A
JPS59115522A JP23450382A JP23450382A JPS59115522A JP S59115522 A JPS59115522 A JP S59115522A JP 23450382 A JP23450382 A JP 23450382A JP 23450382 A JP23450382 A JP 23450382A JP S59115522 A JPS59115522 A JP S59115522A
Authority
JP
Japan
Prior art keywords
wire group
duct
wafer
wire
heaters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23450382A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Nagahara
美行 永原
Toru Nunoi
徹 布居
Akira Shibata
芝田 章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP23450382A priority Critical patent/JPS59115522A/en
Publication of JPS59115522A publication Critical patent/JPS59115522A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to complete a wire connection work by performing only one process for heating and pressurization by a method wherein, after conductive paste has been printed and sintered on the surface of a semiconductor wafer, a fine metal wire group is placed thereon and the fine metal wires are heated and pressurized for the wafer. CONSTITUTION:Al paste 2 is printed and sintered on the surface of the Si wafer 1 formed on a P-N junction part. An alloy layer 2 and a duct 3 are formed by performing a sintering. Then, they are placed between heaters 7 and 7' without removing the duct 3. At the same time, a plurality of lead wire groups 5' are arranged between the heater 7' and the duct 3. the heaters 7 and 7' are heated up under the condition where the above-mentioned positional relations are maintained and, at the same time, said heaters 7 and 7' are moved in the direction of the arrows P and P as shown in the diagram, and the wafer 1 and the wire group 5' are pressurized. As a result, the wire group 5' enters into the duct 3, the wire group 5' comes in contact with the alloy layer 2 and fixed. To be more precise, attracting force is generated between the wire group 5' and the duct 3 and the wire group 5' and the layer 2, and an excellent ohmic contact state is formed between the wire group 5' and the layer 2 by the above-mentioned attracting force.

Description

【発明の詳細な説明】 く技術分野〉 この発明は半導体装置の電極形成方法に関し、特に太陽
電池の製造方法に好適な電極形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method of forming electrodes for semiconductor devices, and particularly to a method of forming electrodes suitable for manufacturing methods of solar cells.

〈従来技術〉 従来、太陽電池の電極形成は、真空革着法または導電性
ペーストの印刷方法によって行っていた。しかし、真空
蒸着法は時間、コストの点で低価格、大量生産を指向す
る上で不向きであり、また蒸着金属のロスが大きいとい
う欠点があるため、現在は導電性ペーストの印刷方法が
主流になりつつある。第1図に典型的な導電性ペースト
印刷方  。
<Prior Art> Conventionally, electrodes of solar cells have been formed by a vacuum leather bonding method or a conductive paste printing method. However, the vacuum evaporation method is unsuitable for low price and mass production in terms of time and cost, and also has the disadvantage of large loss of evaporated metal, so currently, the printing method of conductive paste is mainstream. It is becoming. Figure 1 shows a typical method of printing conductive paste.

法を示す。まず、シリコンウェハ1の下面にA1ペース
ト2を印刷、焼成する(工程(A))。AIペースト2
の下面に形成されるダスト3は焼成段階で、形成される
酸化膜である。続いて化学的に或いは物理的にダスト3
が除去され(工程(B))、さらに、半田イ1けを可能
にするため、露出したAIペースト2上にAgペースト
4を印刷しく工程(C)) 、乾燥、焼成する(工程(
D))。
Show the law. First, A1 paste 2 is printed and fired on the lower surface of silicon wafer 1 (step (A)). AI paste 2
The dust 3 formed on the lower surface is an oxide film formed during the firing step. Next, chemically or physically dust 3
is removed (step (B)), and in order to enable soldering, Ag paste 4 is printed on the exposed AI paste 2 (step (C)), dried, and fired (step (C)).
D)).

以上の工程を経たのち、Agベースト4上にリード線5
を半田6で半田付けして結線を完了する(工程(E))
。このように導電性ペーストを用いる従来の電極形成方
法は、真空工程が不要であるため時間的、コスト的に真
空蒸着法に比べて有利であり、また材料の無駄がないと
いう利点がある。しかしながらこの方法はペーストの印
刷、焼成、および半H(付けの工程が必要であるため、
工程が複雑化するとともに十分なコスト低減を実現する
ことが出来なかった。
After going through the above steps, the lead wire 5 is placed on the Ag base 4.
Solder with solder 6 to complete the connection (Step (E))
. As described above, the conventional electrode forming method using a conductive paste is advantageous in terms of time and cost compared to the vacuum evaporation method because it does not require a vacuum process, and also has the advantage that there is no wastage of materials. However, this method requires the steps of printing, baking, and attaching the paste.
The process became complicated and it was not possible to achieve sufficient cost reduction.

〈発明の目的〉 この発明の目的は、リード線の結線を1工程で完了する
ことの出来る半導体装置の電極形成方法を提供すること
にある。
<Object of the Invention> An object of the invention is to provide a method for forming electrodes of a semiconductor device, which allows connection of lead wires to be completed in one step.

〈発明の構成〉 この発明は、電極用の導電性ペーストを焼成することに
よって、形成された合金前を覆う酸化膜を取り除くこと
なく、その酸化膜上に金属細線群を載置して加熱および
加圧′3゛ることによってその金属細線群を半導体ウェ
ハ面に直接接続すイ・、ことを特徴とする。
<Structure of the Invention> The present invention involves firing a conductive paste for electrodes, placing a group of fine metal wires on the oxide film, and heating and heating it without removing the oxide film covering the formed alloy. It is characterized in that the group of metal fine wires is directly connected to the semiconductor wafer surface by applying pressure.

実施例 第21ヅ1はこの発明の電極形成方法を説明する図であ
る。
Example 21 No. 1 is a diagram illustrating the electrode forming method of the present invention.

まず、第1図の工程(A)と同様にシリコンウェハ1の
表面に△1ペースト2を印刷し、さらに焼成する。焼成
によって合金前2とダスト3が形成されるが、ダスト3
を除去することなく、そのまま上下に配置されたヒータ
7.7′間に置く。
First, Δ1 paste 2 is printed on the surface of a silicon wafer 1 in the same manner as in step (A) of FIG. 1, and then baked. By firing, alloy pre-2 and dust 3 are formed, but dust 3
without removing it, place it as it is between the heaters 7 and 7' arranged above and below.

同時に下側のヒータ7′とダスト3との間に金属細線群
の一例である複数のリード線5゛を配置する。以」二の
位置関係を保った状態で、上下のヒータ7,7′を加熱
するとともにそれぞれのヒータを矢印P、P’方向に移
動し、ウェハとリード線5′とを加圧する。加熱および
加圧は、例えば300℃〜400℃、2001c g 
/ cnTで1分間行う第3図は上記の工程によって得
られた素子の構成1工1である。同1ン1に示すように
、ダスト3上にリード線5′を載置して加熱、加圧を施
すことによって、ダスト3内にリード線5′が入り込み
、合金層2にリード線5′が接触して固定されているこ
とが分る。すなわち、上記の加熱、加圧工程により、リ
ード線5′とダスト3問およびリード線5′と合金層2
間に物理的、化学的吸着力が形成され、それらの吸着力
によってリード線5′と合金1772間に良好なオーミ
ック接触状態が形成される。このように△1ペースト2
を焼成したままのシリコンウェハにリード線5′を重ね
、加熱しながら圧力を加えるだけで結線を完了するごと
が出来る。なお、金属細線群としては、−に記のり一1
′線に代えてメソシュ状、或いは織物状のものを用いる
ことも出来る。
At the same time, a plurality of lead wires 5', which are an example of a group of thin metal wires, are arranged between the lower heater 7' and the dust 3. While maintaining the above two positional relationships, the upper and lower heaters 7 and 7' are heated and moved in the directions of arrows P and P' to pressurize the wafer and lead wire 5'. Heating and pressurization are performed at, for example, 300°C to 400°C, 2001c g
/ cnT for 1 minute. Figure 3 shows the structure of the device obtained by the above steps. As shown in Figure 1-1, by placing the lead wire 5' on the dust 3 and applying heat and pressure, the lead wire 5' enters into the dust 3, and the lead wire 5' is placed on the alloy layer 2. It can be seen that they are in contact and fixed. That is, by the heating and pressurizing process described above, the lead wire 5' and the three dust particles and the lead wire 5' and the alloy layer 2 are separated.
Physical and chemical adsorption forces are formed between them, and these adsorption forces form a good ohmic contact state between the lead wire 5' and the alloy 1772. Like this △1 paste 2
The wire connection can be completed simply by stacking the lead wire 5' on the silicon wafer that has been fired and applying pressure while heating it. In addition, as the metal fine wire group, -1
In place of the wire, a mesh or woven wire may be used.

第1し1に示す従来の電極形成方法では、化学的に(例
えば王水エッチにより)ダストを除去するのに2時間以
上必要とし、また物理的に(例えばワイヤーブラシによ
り)ダストを除去するのに略10分稈度必要とするのに
対し、」1記の方法でリード線の結線を行うのに必要な
時間は、本発明者等が実験したところによると10〜2
0秒であった。またこの場合の電気的特性は、従来の方
法によって得た結線状態の特性と全く差がなく、しかも
リード線と合金W間の接着力も十分であった。
In the conventional electrode formation method shown in No. 1 and 1, it takes more than 2 hours to remove the dust chemically (for example, by aqua regia etching), and it takes more than 2 hours to remove the dust physically (for example, with a wire brush). According to experiments conducted by the inventors, the time required to connect the lead wires using method 1 is 10 to 2 minutes.
It was 0 seconds. Further, the electrical characteristics in this case were no different from the characteristics of the wire connection state obtained by the conventional method, and the adhesive force between the lead wire and the alloy W was also sufficient.

〈発明の効果〉 以上のようにこの発明によれば、ダストの除去ペースト
の印刷、焼成、半r1.+ (=Jけの一連の工作を全
く不要とし、加熱、加圧の1工程だけで結線を完全に完
了することが出来るため、工程が大幅に簡略化すること
はもちろん、結線に必要な時間およびコストも大きく低
減出来る9)ノ果がある。
<Effects of the Invention> As described above, according to the present invention, printing, baking, semi-r1. + (= A series of machining is not required at all, and the wiring can be completed with only one process of heating and pressurizing, which not only greatly simplifies the process, but also reduces the time required for wiring. There is also the advantage of 9) which can greatly reduce costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電極形成方法を工程順に示す図である。 第2図はこの発明の電極形成方法を説明する図である。 第3図はこの発明の電極形成方法を実施したときのウェ
ハのリード線結線状態を示す図である。 1〜シリコンウエハ、  2−AIペースト、3−ダス
ト、  4−−A gペースト、  5.5 ′−リー
ド線、6−半■1、 7.7’−−−ヒータ。 弔1図 年21−J ′じ3rJ
FIG. 1 is a diagram showing a conventional electrode forming method in order of steps. FIG. 2 is a diagram illustrating the electrode forming method of the present invention. FIG. 3 is a diagram showing the state of the lead wire connection of the wafer when the electrode forming method of the present invention is carried out. 1 - Silicon wafer, 2 - AI paste, 3 - Dust, 4 - Ag paste, 5.5' - Lead wire, 6 - Half ■ 1, 7.7' - Heater. Funeral 1 illustration year 21-J 'ji3rJ

Claims (1)

【特許請求の範囲】[Claims] (IIPN接合部の形成された半導体ウェハの表面に電
極用導電性ペーストを印刷、焼成して合金層を形成し、
その合金層を覆う酸化膜上に金属細線群を載置した後、
前記ウェハに対して前記金属細線群を加熱および加圧す
ることによって、前記金属細線を半導体ウェハ面に接続
することを特徴とする半導体装置の電極形成方法。
(Print a conductive paste for electrodes on the surface of the semiconductor wafer on which the IIPN junction is formed, and bake it to form an alloy layer,
After placing a group of metal fine wires on the oxide film covering the alloy layer,
1. A method of forming electrodes for a semiconductor device, characterized in that the thin metal wires are connected to a surface of a semiconductor wafer by heating and pressurizing the group of thin metal wires with respect to the wafer.
JP23450382A 1982-12-22 1982-12-22 Formation of electrode for semiconductor device Pending JPS59115522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23450382A JPS59115522A (en) 1982-12-22 1982-12-22 Formation of electrode for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23450382A JPS59115522A (en) 1982-12-22 1982-12-22 Formation of electrode for semiconductor device

Publications (1)

Publication Number Publication Date
JPS59115522A true JPS59115522A (en) 1984-07-04

Family

ID=16972044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23450382A Pending JPS59115522A (en) 1982-12-22 1982-12-22 Formation of electrode for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59115522A (en)

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