JPS59114865A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To simplify the constitution and thus obtain a semiconductor memory whose manufacturing process is short and which actions stably by using a word line at a ground potential as a cell pair pole. CONSTITUTION:Data lines D and D' are connected to the drains of MISFET's Q3 and Q4 having gate electrodes connected to the word line WL1, the sources of these FET's are connected to data accumulated capacitors C3 and C4, and the pair poles of the C3 and C4 are connected to the other word line WL2 adjacent to the word line WL1. The word line WL1 is kept at a positive potential, and then ''1'' is written by giving a power source potential VCC to the line D and a ground potential to the line D'. At this time, the word line WL2 is kept at the ground potential. Next, the word line WL1 is turned to the ground potential, a terminal phi2 is turned to a positive potential, and the data lines D and D' are balanced by means of a balancing transistor QB, resulting in data holding state. The potential of the data lines D and D becomes approx. 1/2VCC. Then, when it is in a readout cycle, a positive potential is given again to the word line WL1, thus reading cell information out to the data lines D and D'.

Description

[Detailed description of the invention] The present invention relates to semiconductor memory cells.

Semiconductor memories are rapidly increasing in storage capacity, and in particular, various improvements have been made to dynamic random access memories (R, AM) that use one-transistor memory cells and are suitable for high density. Many small memory cells have been announced using patterning technology and multilayer structures. In other words, in the past, the general idea was to improve manufacturing yields, lower costs, and increase production volume by developing smaller memory cells and reducing the chip area. It is true that when the chip area is relatively small, further reducing the chip area has a great effect on improving the manufacturing yield, but today, when increasing the memory capacity, the chip area is 40 to 50 If it reaches 2, the effect of improving yield by reducing the chip area is small, and on the contrary, the structure becomes more complicated and the manufacturing process becomes longer due to the reduction in size. For example, when comparing the number of photoresist (PR) processes, it is found that
In order to construct an integrated circuit (type S), it is possible to construct an integrated circuit in 5 steps, but the current situation is that 9 to 12 steps are required.If the integrated circuit is large, the chip area It is becoming increasingly important to simplify the manufacturing process and shorten the construction period.

FIG. 1 shows a row of one-transistor type memory cells having the simplest structure, and FIG. 2 shows its circuit diagram. The solid line 11 indicates the field region, the dashed line 12 indicates the word line and the polycrystalline silicon layer forming the opposite pole of the cell capacitance.
Reference numeral 13 indicates an opening for connecting the drain region of the transformer 7 and the data line 14 made up of aluminum wiring layers, and point #115 indicates a cell capacitance ion implantation region. This can be manufactured using the 6PR process of field ion implantation gate polycrystalline silicon layer, contact opening, aluminum wiring layer, and cover, which is the minimum amount necessary to construct the above-mentioned and <MIS) transistor. Close to the number of processes.

Originally, in an N-channel MI8 memory, only one selected word line, which is a selection line, needs to be charged to a positive potential.
This method focuses on the fact that all other word lines remain at ground potential, and has a very simple configuration in which this ground potential word line is used as a cell counter electrode.

However, as shown in FIGS. 1 and 2, the opposite electrode of the cell capacitance of the memory cell selected by the word line WLl is all constituted by WL2, so the cell information of the memory cell selected by the word line WLl is (potential of node Nl) is all ground potential, word line W
When LI rises, charge flows from the data line that has been charged in advance during standby, and the potential at node N1 of all selected cells rises, causing the word line WL2 connected by cell capacitance to rise instantaneously. C, word line WL
There is a risk that the information in the memory cell selected by 2 will be destroyed. For the same reason, a similar risk occurs when cell information of ground potential is replaced with information of power supply potential. This causes a decrease in operating margin or a decrease in manufacturing yield.

An object of the present invention is to provide a semiconductor memory that has a short manufacturing process, a simple structure, and operates stably.

In the present invention, a pair of data lines D each have a gate electrode connected to the same word line WLI.
IS FET Q3. Q, connected to the drain of M
Each IS F'ET source has a data storage capacity jk
Cs, C4, and opposite electrodes of the data storage capacitors C, , C, are both connected to another word line WL2 close to the word line WLI. be.

Next, an embodiment of the present invention is shown in FIG. As in FIG. 1, a solid line 41 indicates a field, a dashed line 42 indicates a polycrystalline silicon layer forming a word line and a cell capacitance counter electrode, 43 indicates an opening, and a broken line 44 indicates an aluminum layer forming a data line.
A dotted line 45 indicates an impurity ion-implanted layer having a conductivity type opposite to that of the substrate. FIG. 5 shows a circuit configuration diagram.

Next, the operation of this embodiment will be explained with reference to FIG. However, N-channel type MO8)? The following describes the case where a resistor is used. First, by keeping the word imWI,x at a positive potential and applying the ground potential to the power supply potential VCC%D to D,
Write "l". At this time, the word line WL2 is kept at the ground potential. Next, after setting the word line WLI to the ground potential, 9
12 is set to a positive potential, data #D and D are balanced by the balancing transistor QB, and the data holding state (standby state) is entered. As a result, the potential of the data line D is approximately %Vcc. Next, when entering the read cycle, a positive potential is again applied to the word gWL1, thereby transmitting cell information to the data line D. Word line WL
FIG. 6 shows the change in potential of the data line D from the moment when I is set to a positive potential. The vertical axis shows the potential of the data line, and the horizontal axis shows time. The potential fluctuations of the cell capacitance nodes N, , N are also shown. Cell capacity node N3. N is capacitively coupled to the first word line WL2, but when one goes up, the other always goes down, and because they are arranged close to each other in a pair, the word line WL2 rises and is selected by the word line WL2. It does not destroy the information in the memory cells.

The potential difference S between the data line and D is the sense amplifier (S, A,)
By activating the sense amplifier with an input signal, QD can be brought to the power supply potential CC and D can be brought to the ground potential. As a result, the refresh and source of information in the cell is completed. Next, after setting the word line WLI to the ground potential, balance is achieved by setting L;152 to a positive potential as in the previous time, and the state returns to the stun state. At this time, the potentials of the data, IJD, and D are approximately %VCC. That is, in the cell using the memory cell of the present invention, the phenomenon seen in the cell of FIG. 1 does not occur.

Furthermore, like FIG. 6, FIG. 3 shows changes in the potential of the data line D after the word line WLi becomes a positive potential in FIG. That is, in the method shown in Fig. 2, the signal amount decreases when the initial potential of the data line D becomes low, so it is not necessary to charge the data line D firmly to the power supply potential Vcc during standby. , second
It is necessary to maintain a potential higher than the power supply. However, in order to generate a potential higher than the power supply, a complicated circuit is required, and it becomes susceptible to leakage current and noise voltage due to capacitive coupling. Moreover, the data line,
If both D are near the power supply potential, the gate of the balancing transistor QBI may be in a state where only a potential difference near the threshold value is applied, and for some reason,
For example, if an unbalanced potential difference occurs in the data line D due to noise due to stray capacitance coupling, etc., the balance ability may be small and malfunction may occur.

On the other hand, in the memory according to the present invention, since the signal amount does not depend on the initial potential of the data line and D, it can enter the standby state simply by balancing as described above, and there is no need to charge it to the power supply potential. Since the reset can be completed very quickly and the initial potential of the data line D is low, the gate potential of the balancing transistor QB can be sufficiently balanced with the power supply potential, making the memory cell resistant to noise.

As described above, according to the present invention, it is possible to obtain an l-transistor type memory which requires a very short manufacturing process, has a simple structure, and operates stably.

Although the above description has been made regarding an N-channel type memory, the same applies to a P-channel type memory.

[Brief explanation of drawings]

Figure 1 is a plan view of a conventional one-transistor memory cell.
2 is a circuit configuration diagram of FIG. 1, FIG. 3 is a diagram showing changes in the potential of the data line after word line WLl is selected in FIG. 2, and FIG. 4 is a diagram showing an embodiment of the present invention. A plan view for explanation, FIG. 5 is a circuit configuration diagram of FIG. 4, and FIG. 6 is a circuit diagram of FIG. 5.
7 is a diagram showing a change in the potential of the data line after word line WLI is selected in the figure. FIG. In the figure, 11, 41... field region, 12.42... polycrystalline silicon layer, 13.
43...Opening, 14,44...Data line, 15.45...Cell capacitance ion implantation region, WLl, WL2...Word line, D , five...
...Data line, Qt, Q, t, Qs, Q
4...MISFET, C,,C,,C5,C
,...Data storage capacity, 8A...Sense amplifier. , 4 /z t / figwa? Figure Z, Figure 3, Figure L4, Figure 6

Claims (1)

[Claims] In a semiconductor memory cell, a first insulator having a first data line and a second data line handling opposite information of the first data line, and having a gate electrode connected to the first word line. Gated field effect transistor and second insulated gate
The drains of the first insulated gate field effect transistor are connected to the first and second data lines, respectively, and the source of the first insulated gate field effect transistor is connected to one end of the opposite electrode of the first data storage capacitor. The sources of the second insulated gate field effect transistors are each connected to one end of a second data storage capacitor opposite electrode, and the other opposite electrode of the first and second data storage capacitors are both connected to the first opposite electrode. A semiconductor memory cell, characterized in that the semiconductor memory cell is connected to a second word line adjacent to the word line.