JPS59114859A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法Info
- Publication number
- JPS59114859A JPS59114859A JP57224151A JP22415182A JPS59114859A JP S59114859 A JPS59114859 A JP S59114859A JP 57224151 A JP57224151 A JP 57224151A JP 22415182 A JP22415182 A JP 22415182A JP S59114859 A JPS59114859 A JP S59114859A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal silicide
- semiconductor device
- semiconductor
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57224151A JPS59114859A (ja) | 1982-12-21 | 1982-12-21 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57224151A JPS59114859A (ja) | 1982-12-21 | 1982-12-21 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59114859A true JPS59114859A (ja) | 1984-07-03 |
JPH0423428B2 JPH0423428B2 (enrdf_load_stackoverflow) | 1992-04-22 |
Family
ID=16809336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57224151A Granted JPS59114859A (ja) | 1982-12-21 | 1982-12-21 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59114859A (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4812889A (en) * | 1985-09-24 | 1989-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device FET with reduced energy level degeneration |
US6043544A (en) * | 1997-01-30 | 2000-03-28 | Advanced Micro Devices, Inc. | Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric |
-
1982
- 1982-12-21 JP JP57224151A patent/JPS59114859A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4812889A (en) * | 1985-09-24 | 1989-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device FET with reduced energy level degeneration |
US6043544A (en) * | 1997-01-30 | 2000-03-28 | Advanced Micro Devices, Inc. | Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric |
Also Published As
Publication number | Publication date |
---|---|
JPH0423428B2 (enrdf_load_stackoverflow) | 1992-04-22 |
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