JPS59114662U - Image distortion correction circuit - Google Patents
Image distortion correction circuitInfo
- Publication number
- JPS59114662U JPS59114662U JP817183U JP817183U JPS59114662U JP S59114662 U JPS59114662 U JP S59114662U JP 817183 U JP817183 U JP 817183U JP 817183 U JP817183 U JP 817183U JP S59114662 U JPS59114662 U JP S59114662U
- Authority
- JP
- Japan
- Prior art keywords
- image distortion
- correction circuit
- distortion correction
- voltage
- electrode plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Television Scanning (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図及び第４図は夫々高圧変動に伴う画像歪
の説明に供する線図、第３図は従来の画像歪補正回路の
例を示す構成図、第５図は本考案の一実施例を示す構成
図、第６図〜第８図は夫々第５図例の説明に供する線図
、第９図及び第１０図は夫々本考案の他の実施例を示す
構成図である。
１は水平出力トランジスタ、４は水平偏平コイル、６は
フライバックトランス、７は’ＩＭ流回路、８は可飽和
リアクタ、１３は補正回路、１４は高圧抵抗、２２は電
極板、ＨＶは高圧である。1, 2, and 4 are diagrams for explaining image distortion caused by high voltage fluctuations, FIG. 3 is a configuration diagram showing an example of a conventional image distortion correction circuit, and FIG. 5 is a diagram showing an example of a conventional image distortion correction circuit. FIGS. 6 to 8 are diagrams for explaining the example in FIG. 5, and FIGS. 9 and 10 are diagrams showing other embodiments of the present invention. . 1 is a horizontal output transistor, 4 is a horizontal flat coil, 6 is a flyback transformer, 7 is an 'IM flow circuit, 8 is a saturable reactor, 13 is a correction circuit, 14 is a high voltage resistor, 22 is an electrode plate, HV is a high voltage be.
Claims (1)
の直列回路が接続され、この接続中点に得られる高圧検
出信号により画像歪を補正するようになされたものにお
いて、上記高圧抵抗に容量結合される電極板が設けられ
、この電極板から得られる信号が上記高圧検出信号に重
畳されるようにした画像歪補正回路。A series circuit of a high-voltage resistor and a detection resistor is connected between the output side of the high-voltage generating circuit and the ground, and image distortion is corrected by the high-voltage detection signal obtained at the midpoint of this connection. An image distortion correction circuit including an electrode plate that is capacitively coupled, and a signal obtained from the electrode plate is superimposed on the high voltage detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP817183U JPS59114662U (en) | 1983-01-24 | 1983-01-24 | Image distortion correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP817183U JPS59114662U (en) | 1983-01-24 | 1983-01-24 | Image distortion correction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59114662U true JPS59114662U (en) | 1984-08-02 |
Family
ID=30139663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP817183U Pending JPS59114662U (en) | 1983-01-24 | 1983-01-24 | Image distortion correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59114662U (en) |
-
1983
- 1983-01-24 JP JP817183U patent/JPS59114662U/en active Pending
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