JPS59157361U - pin distortion correction circuit - Google Patents
pin distortion correction circuitInfo
- Publication number
- JPS59157361U JPS59157361U JP5113583U JP5113583U JPS59157361U JP S59157361 U JPS59157361 U JP S59157361U JP 5113583 U JP5113583 U JP 5113583U JP 5113583 U JP5113583 U JP 5113583U JP S59157361 U JPS59157361 U JP S59157361U
- Authority
- JP
- Japan
- Prior art keywords
- distortion correction
- pin distortion
- correction circuit
- wave signal
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Television Scanning (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の回路の構成図、第2図〜第4図はその説
明のための図、第5図は本考案の一例の構成図、第6図
はその説明のための図である。
24はツェナーダイオード、26は定電圧電源端子であ
る。Fig. 1 is a block diagram of a conventional circuit, Figs. 2 to 4 are diagrams for its explanation, Fig. 5 is a block diagram of an example of the present invention, and Fig. 6 is a diagram for its explanation. . 24 is a Zener diode, and 26 is a constant voltage power supply terminal.
Claims (1)
正を行う過飽和リアクタに供給されるパラボラ波信号の
供給通路に、上記パラボラ波信号の所定直流レベル以下
を鈍らせる手段を設けたことを特徴とするピン歪補正回
路。 −2上記実用新案登録請求の範囲第1項記載の
鈍らせる手段は、ダイオードによるクランプ回路で構成
されてなるピン歪補正回路。1. A supply path for the parabolic wave signal supplied to the supersaturation reactor that is provided in association with the horizontal deflection coil and performs pin distortion correction is provided with means for dulling the parabolic wave signal below a predetermined DC level. Pin distortion correction circuit. -2 The blunting means recited in claim 1 of the above-mentioned utility model registration is a pin distortion correction circuit constituted by a clamp circuit using a diode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5113583U JPS59157361U (en) | 1983-04-06 | 1983-04-06 | pin distortion correction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5113583U JPS59157361U (en) | 1983-04-06 | 1983-04-06 | pin distortion correction circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59157361U true JPS59157361U (en) | 1984-10-22 |
Family
ID=30181558
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5113583U Pending JPS59157361U (en) | 1983-04-06 | 1983-04-06 | pin distortion correction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59157361U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61208372A (en) * | 1985-03-08 | 1986-09-16 | アールシーエー トムソン ライセンシング コーポレイシヨン | Video display |
JPH01177661U (en) * | 1988-01-20 | 1989-12-19 |
-
1983
- 1983-04-06 JP JP5113583U patent/JPS59157361U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61208372A (en) * | 1985-03-08 | 1986-09-16 | アールシーエー トムソン ライセンシング コーポレイシヨン | Video display |
JPH01177661U (en) * | 1988-01-20 | 1989-12-19 |
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