JPS59110251A - Information transfer system - Google Patents

Abstract

PURPOSE:To speed up transfer processing by forming transfer information into blocks and specifying block information from a processing unit. CONSTITUTION:Picture and sound data are stored in a composite data memory SDM in block form, and the processing unit CPU sends an address of the composition unit of a main storage device MEM to the memory SDM to read specific data. On the other hand, data read out of the memory DSM by the precedent address is sent to a transfer bus through an FF1 and a gate circuit G. The data is written in an FIFO memory BM at a specific channel part by opening a gate G and also sent out to a highway through an FF3 by a constant clock CLK. Thus, the processing unit CPU edits address information to allow the result to be read in block unit from the memory SDM to send to a specific channel part through a transfer bus TBUS as a composite data without the intervention of software.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a method for transmitting audio and image information at regular intervals, and in particular to information editing from an information source (storage device, etc.).
This relates to an information transfer method that is effective in compositing.

(2) Prior art and problems In general, the method of extracting information from an information source and transferring it to the target output device or transmission line is to transfer it word by word or block every few words and transfer it under program control. is being carried out. In Figure 1,
An example of this conventional information transfer method is shown below. Information processing device C
The PU reads the information to be transferred from the memory MEM under program control and sends it to the time #T via the transmission register REG.

There is also a method in which information is simply read out from an information source and sent directly to a line or the like. FIG. 2 shows an example of such a system, in which the contents of the memory address designated by the address counter X are directly outputted to the transmission register RIG and sent to a line or the like.

However, in the former method, the information transfer speed is
transfer processing, a high-speed dedicated processor is required to speed up the transfer processing, and when time-sharing transfer processing is performed to multiple destinations, the number of lines that can be connected is also limited. It has its drawbacks. Furthermore, when information is edited, combined, and transferred, that is, when information is selectively combined, the latter method cannot be used.

(3) Purpose of the Invention The present invention solves the above-mentioned problems, and provides an information transfer method that can speed up transfer processing by dividing transfer information into blocks and specifying this block information from a processing device. (4) Structure of the Invention In order to achieve the above object, the present invention provides a memory that stores blocked information, a control circuit that reads out the blocked information in units of blocks, an information sending circuit that accumulates the information in blocks and sends it out at a predetermined cycle;
The present invention is characterized in that the memory and the information sending circuit are connected by forming a bus to transfer information. (5) Embodiments of the Invention The present invention will be described in detail below with reference to embodiments.

FIG. 3 shows a configuration diagram illustrating the information transfer method of the present invention. In the figure, the CPU transfers information such as audio and images,
A processing device that performs editing etc., MEM is a main storage device,
Area a1 for storing status information of channels that output information corresponding to each channel; area a1 for storing the start address of a unit of information synthesis;

SDM is a synthetic data memory in which audio data, image data, etc. are stored in blocks (for example, B1 to Bn consisting of n words are stored as a series of words or sentences in one block unit), and CTL is a synthetic data memory that stores processing data. BUS is a common bus that connects the processing unit CPU, main memory MEM, control circuit CTL, etc.;
H#0 to CH#n are the lines to be transferred, for example, channel units that send transfer information to the highway HW that is multiplexed and connected to a switching device, etc., and MUX is the channel unit CH#0 mentioned above.
~ A multiplexing circuit that multiplexes the transfer information output from CH#n and outputs it to the highway HW, TBUS is a transfer bus that connects the composite data memory SDM and the channel unit cu#-o (H#n) .The control circuit CTL is a base address register REG which provides a start address of a blocked data address for synthesizing audio data or image data.

Data block counter CN, predetermined number of blocks (B
l...Bn is the word of each block
Generates the start signal ST of N, and also stops the operation of the counter CN by the coincidence output END of the coincidence circuit CMP.The control register CREG adds the contents of the base address register REG and the contents of the counter CN, and inputs the address to the synthesis memory. It consists of an adder AD and the like.

The detailed configuration of only CH#0 is shown for the channel section, but the other channel sections have the same configuration and input gate G.

Flip-flop FF2. FF3. FF4, first in first out memory (FIFO' memo IJ) B
It consists of M% FIFO, a counter CNT that counts a predetermined storage amount of the memory BM, and the like.

Based on this configuration, the operation of the data transfer system of the present invention will be explained below.

The image data and audio data are stored in blocks (Bl to Bn) in the composite data memory 513M as described above, and the processing device CPU is stored in the main storage device 1MEM.
The start address of the synthesis unit in the synthesis data memory SDM
The predetermined data is read by sending the data to.

For example, when the channel unit CH#0 sends audio data to the output device HW, the area corresponding to the channel in the main memory 1MEM (a * b + e +...
Processing unit C processes the starting base address of the composition unit from ).
The PU is taken out and sent to the memory control unit CTL. This base number is stored in the register REG, and the processing unit CPU sends a command to the control register CREG to activate it, and operates the block counter CN in response to the activation signal ST. The contents of this counter CN and the contents of register REG are added by adder AD, and inputted as address 8 of synthetic data memory SDM. The address A is updated in order until the composite data memory S
You can send it to DM.

On the other hand, data (for example, audio word sounds) read out from the synthetic data memory SDM according to the address ahead is sent to the transfer bus via the flip-flop circuit FF1 and the gate circuit Go. A predetermined channel section (for example, CH#O) receives data by opening the gate G, and the FIF
A constant clock C is written to O memory BM.
Data is sent to highway To via FF3 under LK.

This FIFO memory BM stores (writes) data in blocks, and also loads the data into a predetermined time slot on the highway using a predetermined clock CLK. The amount of data in the FIFO memory vBM is counted by a counter CNT based on the clock CLK-p, and indirectly detects when the FIFO memory BM becomes empty. When the FIFO memory BM becomes empty, it sets FF4 and sends a transfer request signal in priority order. An interrupt is issued to the processing unit CPU to request transmission of the next data block. Along with this interrupt processing, by sending the channel part number for which the transfer request was made to the processing unit CPU and decoder DEC via FF5, the processing bag ucPU determines the data block to be transferred next and synthesizes the data address. While sending the data to the data memory SDM, the decoder DEC opens the gate G of the corresponding channel section CH#0 at a predetermined time to take in the next block.

In this way, the address information of the data to be transferred is edited by the processing unit CPU, and data reading is performed by the synthetic data memory S.
It becomes possible to read data in blocks from the DM, and also to send it as composite data to a predetermined channel unit via the transfer bus TBUS without the intervention of software.

That is, in the transfer method of the present invention, a transfer bus is provided between the composite data memory and the channel independently of the common bus, and the data transfer speed is increased without being controlled by the processing unit CPU. , based on the data address
By simply editing data, processing can be simplified and data editing can be performed with high flexibility.

FIG. 4 shows an example of a system configuration to which the data transfer method of the present invention is applied, in which EX is a digital/I/PB
Exchanges such as X, where T is a telephone terminal, T is a communication terminal that handles voice, data, images, etc., Sv is a service device that handles voice responses, image information transfer, etc. This service device Sv is a circuit with the exchange EX tIR, a synthesizer of audio, image information, etc.
8. Equipped with a storage device M for voice mail, etc.

In such a configuration, the information transfer method shown in FIG. 3 is used in the synthesizer IR8 and becomes effective.

That is, as an example of information synthesis, when various announcements are made by voice response from the exchange EX side to a telephone installed or a communication terminal T, the telephone installed or the like is connected to the service device Sv via the exchange. This service device Sv connects the corresponding line (
For example, one time slot of a time division multiplex line) is connected, and predetermined voice data is synthesized and sent to the telephone installation side. As shown in FIG. 3, this data synthesis and transmission can be performed automatically and hardware-autonomously using the synthesized data memory, transfer bus, and channel section CH#i.

(6) As described in detail, according to the present invention, an information source and a plurality of information transmission destinations are connected by a bus, and the transmission destination is provided with a memory buffer (FIFO memory), and the data transmission destination is provided with a memory buffer (FIFO memory). The transfer (transfer between the information source and the memory buffer) is performed in blocks, and data is sent to the destination periodically (for example, in a time slot assigned to the other end of a multiplexed line). Since only the address assembly and specification are required, data transfer can be speeded up by software autonomously.
The number of transmission lines can be increased, and economical and flexible data transfer becomes possible.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of a conventional data transfer system, Figure 3 is a block diagram of an embodiment of the information transfer system of the present invention, and Figure 4 is a diagram showing an example of a system configuration to which the present invention is applied. 0 CTL is the memory control unit, SDM is the synthetic data memory,
TBUS is a transfer bus, and CH#0 to #m are channel sections. Skull 1 Figure and half 2 Figure

Claims (1)

[Claims] The memory includes a memory that stores blocked information, a control circuit that reads the blocked information in blocks, and an information sending circuit that stores the information in blocks and sends out the information at a predetermined period. and the information transmission circuit are connected in a path format to transfer information.