JPS5853838B2 - Time division channel equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-division channel device, and more particularly to a highly functional time-division channel device for an electronic exchange.

An example of a conventional time-division channel configuration is shown in FIG.

The figure shows a so-called T-8-T configuration, in which digital information from input line 1 of time switches Tll to T1n at the input stage is written into channel memory 3 by writing device 2 in synchronization with the input line clock.

The contents of the force control memory 4 are also read out at regular intervals in synchronization with the clock, and the contents are decoded by the tag decoder 5.
The contents of the specified address in the communication route memory 3 are highway 6.
sent to.

Information on the highway 6 passes through a switch 10 controlled by a control memory 7 in the space switch S, and is transmitted to a designated highway 8 at regular intervals.

Here switch 10 is input highway 6 and output highway 8
The control memory 7 is configured to control the gates provided at each intersection with the control memory 7.

Information about Highway 8 is obtained from the time switch T21 on the output stage.
~ At T2n, the writing device 2 is
, the communication path memory 3, and the decoder 5, and are sent out to the designated channel of the outgoing line 9 in synchronization with the outgoing line clock.

Control information C to be written into the control memories 4 and 7 is sent from the communication path control device SPC.

With this configuration, control memories 4 and 7
Management of control information written to the network is complicated, and therefore a dedicated channel control device is required.

In addition, since the communication path is made up of dedicated hardware, changing the configuration requires wiring changes, etc., making it difficult to realize a flexible configuration, or the communication path device can only perform the simple function of connecting. However, there are disadvantages such as the need to separately provide trunks necessary for providing the service.

The present invention is characterized by realizing a time-division communication path by stacking general-purpose microprocessors and memories, and its purpose is to easily realize expansion from small scale to large scale,
Another objective is to implement the functions necessary for various services on the communication path.

Next, the present invention will be explained with reference to the drawings.

FIG. 2 shows an example of the configuration of a channel conversion device used to configure a time-division channel device according to the present invention.

The operation of the channel converter shown in FIG. 2 is as follows.

Input information from input line 12 (corresponding to 1 in FIG. 1) enters input buffer memory 21.

The memory 22 includes a channel memory section SM (3 in FIG. 1), a control memory section CM (4 in FIG. 1), and a program memory section P.
M and others are provided, and call information, control information, programs, and other information are stored therein.

The processing section 23 reads the contents of the input buffer register 21 into the communication channel memory section SM of the memory 22 according to the program in the memory 22, and also transfers the contents to the output buffer register 2.
4 to the outgoing line 12', the channel conversion operation of the time switch composed of the writing device 2, communication path memory 3, control memory 4, and decoder 5 shown in FIG. 1 is realized.

Note that CB is a common bus for connecting the above devices, and clock 25 is an interrupt line for synchronizing with an incoming clock.

Further, it is assumed that at least one of the input buffer register and the output buffer register is provided in plural numbers, and at least one of the input line 12 and the output line 12' is provided in plural numbers.

An example of the operation of the channel converter shown in FIG. 2 will be explained with reference to the time chart shown in FIG.

In Figure 3, using the PCM 24 channel system as an example, the input line A
,B,...

This shows an example where X information is channel-converted to C, D, . . . , B on the output line.

FIG. 3a shows the time slots tl, t2 to t24 in the frame of the PCM 24 channel system and two clocks T1 . T2
This is a chart showing the temporal relationship between the input buffer register BMI and the output buffer register BMO. Information A, B・
...X is converted to C, D...X, A, B on the outgoing line.

At the timing when the clock T1 is present in the time slot tl, the content A of the input buffer register BMI is stored in address 1 of the communication path memory section SM of the memory.

At the time slot t1, when the clock T2 is present, the content C of the address in the speech path memory part SM pointed to by the content 3 of the address 1 in the control memory part CM is sent to the output buffer register BMO.

At time slot t2, when the clock T1 exists, the content B of the input buffer register BMI is stored at address 2 of the communication path memory section SM of the memory.

At time slot t2, when clock T2 is present, the contents of the address in channel memory part SM pointed to by content 4 at address 2 of control memory part CM are sent to output buffer register BMO.

Thereafter, the same operation is performed, and at the timing when the clock T1 exists in the last time slot t24, the content X of the input buffer register BMI is stored in address 24 of the communication path memory section SM.

Then, at the timing when the clock T2 is present in the same time slot 124, the content B of the address in the channel memory part SM pointed to by the content 2 of address 24 in the control memory part CM is sent to the output buffer register BMO.

Note that if there are multiple input buffer registers (21 in Figure 2) and output buffer registers (22 in Figure 2), it is easy to output the input information of any input buffer register to any output buffer register. It is possible.

FIG. 10 is a time chart when the channel conversion device of FIG. 2 operates with two incoming lines and two outgoing lines.

In Figure 10, each of the two PCM 24 channel system input lines A, B, C...X and A/, B/,
C/...X' information is transmitted to each of the two outgoing lines B'
, A... and X'...B.

FIG. 10a shows a time slot t which is twice the time slot in one frame of the PCM 24 channel system.
1 to t48 and two clocks T1.1 to T48 having different phases of the channel conversion device. Indicating the temporal relationship with T2, the figure shows two input buffer registers B corresponding to two input lines.
The input information to M■ and BM■2 is channel-converted and converted to 2.
Output buffer registers BMO1 and BMO1 corresponding to the outgoing lines
This shows the state in which the connection with Mo2 is reached, and C in the figure shows the information A, B, . . . for each time slot of each incoming line.
X, A', B'...X' connects B', A to each outgoing line
... and X'...B.

In the above, time slot t1. shown in FIG. 10a.
The lengths of t2...t48 correspond to the length of a time slot given to one channel of the incoming and outgoing PCM24 channel system.

In the control memo IJcM, information (1 or 2) instructing the output buffer register in which information should be written in addition to the address of the channel memory unit SM for reading information is written. Write information to the buffer register (BMO1 or 8MO2).

Other channel conversion operations are similar to those in FIG. 3 and are considered to be easily understood, so detailed explanations will be omitted.

Furthermore, as will be described later, the memory 22 can be provided with a trunk memory section and a data memory section to perform other functions necessary for conversion in addition to channel conversion.

The present invention provides a channel conversion device and a channel conversion device in which a trunk memory section, a data memory section, etc. are installed in the channel conversion device shown in FIG. The present invention is directed to a time-division channel device configured using a channel conversion device that performs only the channel conversion shown in FIG.

FIG. 4 shows an example of the configuration of a time-division communication path according to the present invention.

In the figure, S11 p 821 p S1□, S22 are respectively channel conversion devices as shown in FIG. □.

It is connected to the incoming line of S2□, and is in the form of a link connection.

By connecting the channel converter shown in FIG. 2 as shown in FIG.
and is transferred to any empty channel in the outgoing line group 9.

The channel conversion device Sll transfers the information on the input line I Ll to the intermediate connection line Lll 9 Ll according to the contents of the control information in the memory.
Send to either □ within a certain period.

The same applies to the channel conversion device S21. Outgoing OL1. O
Channel conversion device S1□ on the L2 side.

S2□ reads the contents of the incoming line, writes them to the communication path memory section SM, and writes the contents of the communication path memory section SM at the address indicated by the contents of the control memory section CM to the outgoing line OL1. Send to OL2.

Here, a space switch like the one shown in FIG. 1S is not required, and the scale of the communication path can be expanded by adding a channel conversion device such as 811 without providing this kind of space switch.

FIG. 5 shows an example of the configuration of the present invention when a plurality of channel conversion devices are connected to a common channel bus SH.

In the figure, Sl t S2 to Sn are channel conversion devices as shown in FIG. 2, each having two incoming lines and two outgoing lines.

Taking the channel conversion device S1 as an example, one incoming line I
Information input from L1 is sent to the desired channel conversion device S1. through one outgoing line L1 and the common bus SB. Intermediate connection line L1□, L which becomes the input line of other power (one of S2 to Sn)
2□~Ln2 to the desired channel conversion device, and from this, its output line OL1. One of OL2~OLn
output to each desired channel.

The same applies to channel conversion devices 82 to Sn.

In the present invention, it can be easily inferred from the prior art that there are various connection methods such as ring connection and loop connection in addition to the method of connecting the channel converter.

Although the time division channel device according to the present invention is not shown in the figure,
For small-scale devices, it is possible to configure one channel conversion device with a plurality of incoming and outgoing lines.

Further, in FIG. 2, the clock line 25 is used for synchronization with the incoming line, but in each of the embodiments described above, it is also possible to achieve synchronization by including a synchronizing signal in the incoming line 12.

The incoming line 12 is also connected to each subscriber or to a multiplexed line (for example, by PCM24 channel power type).

FIG. 6 shows an example of the configuration of a channel conversion device in which the trunk function is also realized on the communication path.

The numbers and symbols in the figures are the same as in Figure 2.

In this case, the memory 22 includes the communication path memory section SM, the 匍Jf
M] In addition to the memory section CM and program memory section PM, a trunk memory section TM and a data memory section DM are provided.

400Hz as shown in Fig. 7 in the trunk memory section TM.
The bit pattern corresponding to AC is stored, and the processing unit 23 sends the contents of address i of the trunk memory unit TM to the output buffer register 24 once every 125 μs, and
By sending the contents of address i+1 to the output buffer register 24 at the timing , a dial tone can be sent.

In addition, a ringing tone can be realized by sending the sound for 1 second and stopping for 2 seconds.

Alternatively, it is possible to transmit a busy tone by further changing the intermittent ratio.

In FIG. 6, a bit pattern corresponding to a signal sent from a subscriber at the time of call origination, disconnection, response, etc. is stored in a data memory unit DM, and a processing unit 23 stores a bit pattern in a data memory unit DM.
By comparing the information stored in the data memory section DM with the bit pattern of the data memory section DM, changes in call origination, disconnection, response, etc. of the subscriber can be detected.

Since the disconnection of the loop of the called subscriber can be detected in the same manner as described above, the dialed number can be detected by counting the number of disconnections in the processing section 23.

Furthermore, it is possible to easily output the information stored in the channel memory unit SM to two or more subscribers, so that a conference call can be made, and this channel device can be used to control the conference trunk. function can be provided.

By detecting a subscriber's accommodation location or assigned channel and comparing this with stored data, it is also readily possible to analyze the subscriber, ie to identify the subscriber class.

It is assumed that the above operations are executed in the processing section 23 by a program without providing any special hardware.

Therefore, in the communication path device according to the present invention, various trunk functions such as outgoing trunk, incoming trunk, busy trunk, calling trunk, conference trunk, etc. are provided by a program without adding any special hardware, and it also provides call detection and response. It is possible to perform detection functions such as call detection, end of call detection, and digit reception, as well as various control functions such as subscriber analysis, called party selection, and call path selection.

FIG. 8 shows an example of realizing the concentrating function by the time division communication path device of the present invention.

S in the figure a is a channel converter as shown in FIG.
The information of A/ and B/ is sent from ne2 to the outgoing line Line3 (
5 channels) and channel conversion.

Information B', A, C, A is stored in the control memory section CM of the memory 22.
By storing the address of the channel memory SM where each of ' and H are stored, B' and A are stored at regular intervals.
, C, A', and B are sent to the output buffer register BMO of the outgoing line 3 in the order.

FIG. 8 shows a state in which information input from incoming lines Line1 and Line2 is sent to outgoing line Line3.

FIG. 9 shows an example of reducing voice quality to deal with line congestion.

In this case, a channel conversion device S similar to that shown in FIG. 8 is used.

A, B, C from incoming line Line A' from incoming line 2
, B'.

Let us consider the case where the information of 6 channels of C' is input from the incoming line and the outgoing line has a capacity of only 5 channels.

In the first frame, 5 channels of A, A', B, B', and C (without C/) are transferred, and A in the second frame.

Send A', B, B', C (missing C).

The data are sent out repeatedly in sequence as shown in the figure below.

As shown in the figure, information A, B, C, A',
Information B' is normally sent in five consecutive frames, but is not sent in the next frame, and information C' is sent instead.

On the receiving side, the information shown in the figure is received as information A, B,
For C, A', and B', information with one missing sample value is reproduced in one channel every six frames, and information C' is sent with one channel shifted every frame. , on the receiving side, these are combined into another channel and sent out.

In this way, transmission for 6 channels is performed using a trunk line with a capacity of 5 channels.

In this way, congestion can be dealt with by essentially extending the sample period (ie reducing the audio quality).

In addition, it is easy to deal with congestion by lowering the 8-bit sampling of manual information to 7 or 6 bits, or by effectively utilizing subscriber channels that are silent. can be realized.

According to the present invention, in the time division communication path device, an output buffer register can be provided for each subscriber.

This allows subscribers to be connected in a space-divided manner,
It can provide the function of a space switch.

Furthermore, when the above-mentioned time-division communication path device uses multiplexed transmission lines as input and output lines, by providing a buffer register and an output buffer register for each channel of each transmission line, it functions as a space switch as well as a time switch. Therefore, by configuring in this way, the time division channel device can have the function of a time switch or both the functions of a time switch and a space switch.

As explained above, since the present invention constructs a communication path by stacking channel conversion devices having processing functions, the present invention has the following advantages.

(1) Since the configuration allows for easy introduction of LSI technology such as a general-purpose microprocessor, it is possible to realize miniaturization and cost reduction.

(2) Functions that were conventionally only possible with a control device can also be achieved with a communication channel.

This allows the call path to have the functions of various trunks such as a conference trunk and an outgoing trunk.

Flexible measures can be taken when line congestion occurs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an example of a conventional time-division channel device, and FIG. 2 is a block diagram showing the configuration of an example of a channel conversion device used in the configuration of the time-division channel device of the present invention. , FIG. 3 is an explanatory diagram of the operation of the channel converter shown in FIG. 2, FIG. 4 is a block diagram showing the configuration of one embodiment of the present invention, and FIG. 5 is a block diagram showing the configuration of a different embodiment of the present invention. 6 is a block diagram showing the configuration of a different example of the channel conversion device used in the configuration of the time-division channel device of the present invention, and FIG. A diagram showing an example of a bit pattern to be stored, FIG. 8 is an explanatory diagram of the line concentration operation of the channel converter in the present invention, FIG. 9 is an explanatory diagram of the congestion countermeasure in the present invention, and FIG. 10 is an explanatory diagram of two incoming lines. FIG. 2 is an explanatory diagram of the operation of a channel conversion device used in the present invention, which has two outgoing lines. Tll~TlfijT21~T2n...Time switch, S...Space switch, 1 p 12
t I Lt v ■L2〜I Ln, Linc
4, Line2 = incoming line, 2- - writing device,
3... Communication path memory, 4, 7... Control memory, 5... Decoder, 6, 8...
Highway, 9 * 12' * OI4 s OL2
~OLn p Ls ne3 +n*+*+ Outgoing line, SP
C...Communication path control device, 21, BMI...
. . . Input buffer register, 22 . . . Memory, 23 . . . Processing unit, 24. BMO...
・Output buffer register, 25...Clock,
CB...Common bus, Tl, T2...
・Clock% tl"t24...Channel timing, A, B, C, D-X, A', B'. C'...Call information, SM... Communication path memory section, CM... Control memory section, St St
t p S21 p Sl□. S2□* S1* S2~Sn...Channel conversion device, 11 p Lll t L12 p L2, e
L22~Lnl t Ln2”...Intermediate connection line, P
M...Program memory section, TM...
Trunk memory section, DM...Data memory section.

Claims (1)

[Claims] 1. A memory including a communication path memory section, a control memory section, a program memory section, a trunk memory section, and a data memory section, a processing section, at least one of which is connected to a plurality of input and output buffer registers, and these, etc. It has a common bus, stores the contents of the input buffer register in the channel memory section, and reads them out to the output buffer register at the timing determined by the control information of the control memory section, realizing a space switch and a time switch simultaneously, and also realizes a space switch and a time switch simultaneously. This indicates that one or more channel conversion devices configured to read the data into the output buffer register, transmit a signal tone, and detect the state of the subscriber using the data memory section are connected. A time-division communication path device with special features.