JPS5910993A - Dot matrix type display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in dot matrix display devices.

Conventionally, there has been a display g position for this cypress as shown in FIG. In Fig. 1, there is a matrix display with lij M rows and N-stage shift register, (4) is a latch circuit that outputs display data to the driver circuit (2) while holding the display data while displaying the display data of the row, for vertically scanning the +51ri matrix display stack. vertical scanning circuit, +6
Display signal processing circuit that creates 1D display data and transfers it to the latch circuit (4) Henrial Ic (7) Nimatrix display stack and driver circuit (2) and latch circuit (4) and vertical scanning circuit (5) t-controller death.

This is a control circuit that interoperates with the display signal processing circuit (6).

If the first row of the matrix display is to be displayed, all display data of the first row is serially transferred to the 1 display signal processing circuit+61ri latch circuit (4).

When the display data transfer is completed, the latch circuit +41
14. The display data is output in parallel to the driver circuit (2), and the driver circuit (2) drives the four peaks of the matrix display. In other words, the first row selected by the vertical scanning circuit +51K? rDisplay. After the display continues for a certain period of time, the display data on the second line is processed by the display signal processing circuit (6).
) is transferred to the latch circuit (4). When the transfer is completed, the second line is displayed. In this way, the transfer and display are repeated one after another, and the data is sequentially displayed from the first line to the Mth line at f, 9 refresh cycles.

FIG. 2 shows the typing of display data in each row of the four matrix display rows, the transfer of display data in units of rows of the shift register (3), and the timing of display. In Figure 2,
TI is the transfer time of display data for one line, T2
is the display time of the display data transferred in the transfer time Tl, and Trefl is the refresh period e''*be
C and d are typings that indicate the relationship between transfer and display of display data for the first row, second row, third row, and OM row of the four matrix display peaks, respectively, and e is a shift register (3)
This is a typing that shows the relationship between display data transfer and display. In the figure, the display data transfer time Tl is indicated by a double circle at one display time T2 on the f+ line.

Further, when display data of VcN dots are transferred during the transfer time TlO, the transfer time per dot is assumed to be Ta.

According to FIG. 2, there is a relationship ri between the refresh period Trefl, the display data transfer time T1, and the display time T2.

TreH=M, (Tt +T2)・・・・・・・・・
It is expressed as ・・・・・・・・・・・−・・・・・・・ill. Furthermore, transfer time Tl.

Since T1=N, Ta...song...song...song...song...four...song...four...+23, Inuyama 1 formula (2) Sh.

Trefr == M, (N, Ts +'l'2
) ・、・、−、、、、、・、、・、、、、、、、
It becomes +31.

Therefore, in the conventional dot matrix type display device of this kind, when the number M and N of 711x becomes large and the transfer time T3 per dot is constant, the VC is used to keep the refresh period Tveflt constant. In this case, the display time T2 must be shortened, resulting in a decrease in brightness and contrast.

Therefore, in the present invention, a first means for dividing the latch circuit (41) for latching one row of display data into a plurality of parts, and a second means for providing a plurality of latch circuits (4) for latching one row of display data. , a plurality of latch circuits (4) for latching all the display data for one row are provided.

1 latte for each! ? By each of the third means of dividing the circuit into a plurality of parts, brightness and contrast can be improved;
Furthermore, by improving the refresh rate of the iC display screen, a high-quality screen is always displayed regardless of the number of matrices M and N. Hereinafter, a small matrix display 'at' will be referred to as a small matrix display in which 9 rows or columns are divided into 2 parts in a light, and the horizontal movement of the small matrix display will be referred to as a row block, and the arrangement of columns will be referred to as a column block.

Here, to simplify the explanation, the first method uses one row of latch circuits (41 circuits divided into four circuits).

If the second means provides four row latch circuits for riJ rows + 41'f, the third means provides latch circuits for one row (4).
If there are 4 in total and each is divided into 4, VCC short leg.

Let us describe one embodiment of this invention. in this case.

3) Transfer time T3 ri for one more item will be explained as being the same as the conventional method.

1. First, a case will be explained in which the first means is implemented.

In FIG. 3, mountains 15) and (6) are the same as in FIG.

(4a), (4b), (4C) and (4d) U71
The latch circuit +41 in the figure is divided into 41 parts and the latch circuit at 7C - (la) * (]b) - (]c) and (ld)f
f latch circuit (4a)* (4b), (4c) and (
VC of 4d), corresponding M rows x 5 columns matrix display, (28), (2m), (2C) and (2
d) is a latch circuit (4a).

Driver circuits corresponding to (4b), (4C) and (4d), (3a), (3b) # (3C
) & (3d) d latch circuit (4a) (4b), (4
This is a one-stage shift register corresponding to each of c) and (4d).

If the first row of the four matrix display rows is to be displayed, the display data of the first row of the matrix display 5 (la) is transferred to the shift register (3a).

When the transfer is completed f, the display data of -f: is output to the driver circuit (2a), and the first row FFJt of the matrix display (]la is displayed. At the same time, the matrix display ()
The display data of the first row of lb) is transferred to the shift register (3L
+) and displayed at the same time as the end r. Similarly,
Display data is transferred to shift registers (3C) and (3d) and displayed. Even if you do this, the shift register (
Display data is transferred to 3a), (3b), (3C) and (3d) one after another, and the valley shift register (3a),
At the same time as the transfer ends at (3b), (3C) & (3d), the valley driver (2a), (2b), (2c)
and (2d) to display the first stroke on the matrix display tit. After PL, the transfer and display of display data is similarly repeated from the second row to the O-M row, and the display data is displayed successively in two refresh cycles.

Figure 4 shows the shift register, t, fi (3a), (3
The timing of transfer and display of display data in b), (3c) and (3d) is shown. In Figure 4, e 'e
Shift register (3a) for '*'& i, respectively.
(3b) Timing of display data transfer and display in (3C) and (3d), Tzefz ri refresh period, T4 is valley matrix display (1a), (lb)
.

(IC) and (1d) - Transfer time of display data of whereabouts.

Ts is the display time of the display data transferred during the transfer time ゛1'4.

If the fourth heart KL, two refresh cycles T by the first means
The relationship between ref2, transfer time T4, and display time T5 is as follows.

Tref2=M, (T<10Ts)...
・・・・・・・・・・・・・・・・・・・・・・・・1
4).

Assuming that the two refresh periods Trefz are the same as before.

Trefz = Tteh ... - ... Purpose ... ... 1 song / song ... +5) T4 = -,
Ts = Yu10110091088110.19911
600010030091060. (6) 4 TI Treh = M, (-4-Ts)...
4...-...Moe...+71. From Narita and formula (7), Ts = T2 +-, TI... Song/purpose/4-
...Purpose...-+8) Brightness and contrast can be improved compared to conventional ones.

If one display time T5 is the same as before.

'i'1=T2...River...For melodious use...
...For use...Open use/For use i91, so 1 set (4)
teeth.

111 'L're(2: M, (-+ 'l'2n...song...4...listen to 4uw. Narita and formula (1
0), Tref2 = 'l're rl--, M, J'1
−−−−−−−−−−−−−−−−・−(41) In other words, the refresh period T e f
2) Compared to the conventional one, it is possible to increase the brightness and contrast of the screen as well as to reduce the flickering of the screen.

Next, a case will be described in which the second means is implemented.

Since the second means VC is equivalent to the latch circuit (4) of FIG.
, the transfer time is 1iTs, and the display time is T7, then the relationship is '1'ref3=-, (Ts +T7)
−=−=−, ·−−−−03.

Refrenyu lap MTref3 'fz Same as before 7
“L is.

'l'refa = Trefl...quadruple...
Song...Song...4t13+T6=N, T3=
T't −・・−・Song・−、−・−−−−−−−−1
It will be 141, so 20 strokes.

Tref1= −, ('l'1+' T7 ) −・
The song will be song 1I5). Ceremony and Take a9
Rainbow T7=1'2+3. (TI+T2) ・・・
...(1G + that is, the display time T of this invention)
7 is the conventional display time T2 processing 3, (T1+'T2
) increases by.

Therefore, the RL degree and contrast can be improved as compared to the conventional one.

Also, if the display time Ty f is the same as before.

T7: T2...4...4...For concave ψ curves.
......Song...c171, so 9-type mouth 2I
The shore.

Tref3=-(T+ +Tz)・Ko・Kun・Kun・・Kawa・・・It is spelled o. In the formula and from the formula U&, 'L'ref3='I'rcf1--, "i're
fs -=---=-.-411i1+ That is, according to the present invention, the reflex cycle Tref3 is reduced by Tref+ compared to the conventional method. Therefore, compared to the conventional one, it is possible to reduce the flickering of the polished screen by 7 degrees, and improve the brightness and contrast.

Next, the case where the third means is implemented will be explained.

In this case, the second period of refrain is Tref4. Transmission time total 1
If ゛8゜display time iT9 and n, then the relationship between these is.

Tref4=+, (Ts +Ts) −, −, −
,,,,,,,song,,song,song,(2(becomes 11).

Assuming that the refresh period 'l'ref<i is the same as before.

Tref4 == Trefl ・A・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Since it will be UIJ, there will be 1 type (support).

becomes. From Inuyama and formula (c), '1'9 =T2 +-0Tx +3. (TI+T2)
......Mountains, Islands, In other words, according to the present invention, the display time T9 is shorter than the conventional display time T2 by 10Tt by the first means VC and 3, (Tt by the second means)
++T2) Riki Takedan speaks. Therefore, brightness and contrast can be improved as compared to conventional ones.

9. If the display time Tsi is the same as before.

T9=T2...West...song...song...previous song...four...previous song...song...song...□□□, so Niyama is.

becomes. Inuyama and human flesh exercise.

That is, with this invention, the 8th period'l'r
e f 4 can be used to completely reduce flickering on the polished screen, as well as improve the concealment and contrast.

In the above explanation, the latch circuit (
4) division purple 4 division, latch circuit by second means (4
), but the general VC2 division ih division by the first method, expansion by the second method '<
The following table shows the situation with one direction.

When using the first method.

The formula (III is Trefz = Trefx −(
−), M, Ti −−−−−−−・l19)1
1 Lifting platform by the second means.

Formula (+6j is T7='l'2+(t-1), (T
I+T2)・・・・・・■ff(191[, Tre
f3=Trefl-(-), Treft ・-=-=-
(31) A case in which the first means and the second means are all implemented simultaneously.

2- is T9 = T2+(-), Ts +C1
-1), ('l'l+'ln)・・・・・・・・・1
．． Q, Ml・・・・・・・・・・・・・・・・・・
(It goes without saying that the larger the number of h&t, the more effective it is.

As described above, in the dot matrix type display device according to the present invention, the latch circuit (4) of FIG. By means of each brightness.

-1- between contrast and refresh rate
can be done.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional dot matrix type display device, and FIG. 2 is a timing diagram showing the relationship between display data transfer time and display time of the conventional dot matrix type display device.
FIG. 3 is a block diagram of a dot matrix type display device according to an embodiment of the first means of the present invention, and FIG. 4 shows display data of the dot matrix type display device according to an embodiment of the first means of the present invention. FIG. 3 is a timing chart showing the relationship between transfer time and display time. In the figure, (l), (1a), []b), (IC), and (
ld) id matrix display, i21. (2a
), (2b), (2c) and (2d) i't driver circuit, +3), (3a), (3b), (3
c) and (3d) U shift register, (4) is a latch circuit, and (5) is a vertical run circuit. (6) is a display signal processing circuit, and (7) is a control circuit. In FIG. 1, identical or contrasting portions VC are indicated by the same reference numerals. Agent Shin Kuzuno - CM -CI LJ M
Φ′+-+ % (゛9 -580

Claims (3)

[Claims] (1) A display device configured by arranging all display elements in a dot matrix, a display signal processing circuit that creates data to be displayed on this display device, and the display device (i-
The driver circuit to drive and the display signal processing circuit mentioned above transfer one line of display data in parallel in parallel.
9 display units in a dot matrix type display device consisting of a latch circuit that holds all display data during the display, a vertical scanning circuit that vertically scans one display screen, and a control circuit that controls all of these. A dot matrix type display device whose characteristic is that a latch circuit that latches one line of display data that is transferred serially from a processing circuit is divided into a plurality of parts. (2) A display device configured by arranging all display elements in a dot matrix, a display signal processing circuit that creates data to be displayed on this display device, a driver circuit that operates the display device, and the above-mentioned display. A latch circuit converts one line of display data serially transferred from a signal processing circuit into parallel data and holds the display data while that line is displayed.
In a dot matrix type display device consisting of a vertical scanning circuit that vertically scans a display screen and all of these control circuits, the display signal processing circuit described above has a latch circuit that latches all of the display data for one line that is serially transferred. This dot matrix type display device is characterized by having a plurality of . (3) a display device configured by arranging all display elements in a dot matrix, a display processing circuit that processes all data displayed on the display device, and a driver circuit that drives the display device; The display data for one line that is serially transferred from the display signal processing circuit is converted into sound parallel, and the display data is displayed while the money is being displayed. In a dot matrix type display device consisting of a latch circuit for holding, a vertical scanning circuit for vertically scanning nine display screens, and a control circuit for controlling all of these, one line of data is serially transferred by VC from the display signal processing circuit. A dot matrix type display device, characterized in that a plurality of latch circuits for latching display data are provided, and each latch circuit is roughly divided into a plurality of pieces.