JPS59108471A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To increase the degree of circuit integration by forming a layer on which a channel region is formed by a semiconductor the same type as the layer formed with a gate region and a layer with lower impurity density than that of the gate region. CONSTITUTION:A channel region 112 made of a p<-> layer is formed on an n<+> substrate 110 and a pair of p<+> gate regions 114 are formed on the upper face of the region. A source region 116 is provided between the gate regions 114 and a cell corresponding to one picture element is formed by the combination of the source region 116 and the gate region 114. A readout address circuit 130 is connected respectively to one set of gate electrodes 124, and a readout pulse is applied sequentially to each cell. Further, the source electrode 122 is connected to the drain of a switching transistor 140, which is driven by a pulse voltage from a video line selecting circuit 132 so as to perform the readout of each cell.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to solid-state imaging devices, and more particularly to improvements in solid-state imaging devices using SIT, that is, static induction transistors.

A basic solid-state imaging device using SIT is disclosed in Patent Application Publication No. 15229 of 1980 as a starting technology, and furthermore, more specific and improved versions of this device are disclosed. This has been proposed as patent application No. 204656 of 1982 and patent application No. 157693 of 1988.

Although the basic structure of SIT is similar to that of J-FET (junction field effect transistor), it has a feature that the impurity density of the semiconductor layer forming the channel portion is low. For example, in a typical J-FET, the impurity density in the channel region is 10 to 1017 cm-3, whereas in SIT it is 1012 to 1015 cm-3.
It is about 6.

Therefore, the depletion layer formed in the channel region is formed over a wide range even in a state of thermal equilibrium where no voltage is applied from the outside, and furthermore, the channel region has a short length.

Due to the above-mentioned features that are different from ordinary J-FETs, the channel reaches a pinch-off state in a state of thermal equilibrium or with a slight reverse bias, and a potential barrier appears just before the source electrode. The amount of movement of carriers constituting the current flowing from the source electrode to the drain electrode can be controlled. That is, the drain current is determined by the amount of carriers that cross the potential barrier and reach the drain electrode.

On the other hand, the degree of the potential barrier described above also changes depending on the drain voltage applied to the drain electrode (with the source electrode as a reference). That is, by applying a drain voltage, electrostatic induction occurs, and since the impurity density in the channel region is still low, the height of the potential barrier changes, and furthermore, the peak point of the potential barrier (hereinafter referred to as "true ``Kate'') moves. For example, when the channel is formed of an n- semiconductor and a positive drain voltage is applied, the potential of the potential barrier decreases and the true position of the channel moves toward the source electrode.

Additionally, the extent of the potential barrier changes due to the accumulation of electron-hole pairs formed by light incident on the channel region. In other words, electrons and holes generated near the vacant layer in the channel region move along the potential barrier and are separated.
Accumulates in the dirt area. Therefore, the potential of the potential barrier changes. The degree of this change corresponds to the amount of incident light. Therefore, by applying an appropriate drain voltage, the drain current or source current that flows has a magnitude corresponding to the amount of incident light.

As described above, the degree of the potential barrier changes depending on the gate voltage, drain voltage, or incidence of light. Therefore, for example, if a bias voltage is applied to keep the channel in an OFF state even when light is incident, carriers caused by the incident light are accumulated, and then an appropriate readout voltage is applied, non-destructive or non-destructive It becomes possible to read image information, ie, the degree of incident light, without destroying the accumulated state of carriers. A solid-state imaging device can be configured based on such a principle.

Furthermore, the degree of potential barrier varies greatly depending on dimensional accuracy. In SIT, a potential barrier is created by the diffusion potential between the source region and the gate or channel region. That is, the potential distribution is mainly determined by the boundary conditions of each region. Therefore, the characteristics are very sensitive to the arrangement or size of each region.

For this reason, it is said to be difficult to improve the degree of integration by reducing the size of each cell, that is, the occupied area.

The present invention has been developed in view of these points, and has sufficient tolerance for process variations that appear as dimensional variations in manufacturing processes such as mask alignment, etching, and doping, and further improves the degree of integration. The purpose is to provide a solid-state imaging device that can achieve

That is, in the present invention, the layer in which the channel region is formed is the same type of semiconductor as the layer in which the dirt region is formed,
In addition, the above objective is achieved by forming the gate region with a layer having a lower impurity density than the gate region.

Hereinafter, the present invention will be described according to the embodiments shown in the accompanying drawings (5). This will be explained in detail.

FIG. 1 shows a cross-sectional view of a cell corresponding to one pixel of a solid-state imaging device according to the present invention.

In this figure, a channel region 112 made of a p layer with a low impurity density is formed on a substrate 110 made of an n+ layer made of a material such as silicon (Si) with a high impurity density. This channel region 112 is formed by epitaxial growth so that lattice defects and the like are not generated so that electron-hole pairs are well generated and separated by incident light.

A pair of dirt regions 114 made of a p+ layer with a high impurity density are formed on the upper surface of the p layer forming the channel region 112, and between the gate regions 114, a pair of dirt regions 114 made of a p+ layer with a high impurity density are formed. A source region 116 is provided.

A cell corresponding to one pixel is formed by a combination of these gate regions 114 and source regions 116,
These cells are regular and two-dimensional with appropriate spacing (IJ)
A plurality of them are arranged in a box shape to form a rigid (6) gymnastics image device.

An insulating film 12 of silicon oxide (SiO2) is formed on the entire upper surface of the p layer where the channel region 112 is formed, except for the exposed portions of the gate region 114 and the source region 116.
0 is formed for surface protection. Further, a source electrode 122 is formed in the exposed portion of the source region 112, and a transparent gate electrode 124 is formed in the exposed portion of the gate region 114 with an insulating layer 126 interposed therebetween. This insulating layer 126 is made of, for example, a SiO2 film, and thereby protects the gate region 114 and the dirt electrode 124 from each other.
A capacitor is formed between the two.

A drain electrode 128 is formed on the opposite side of the substrate 110 from the p-layer where the channel region 112 is formed.

A read address circuit 13 is connected to one set of gate electrodes 124.
0 are connected to each other, and a reading voltage is simultaneously applied to each cell in turn. The source electrode 122 is connected to the drain of a transistor 140 that performs a switching operation, and the source of the transistor 40 is connected to an output terminal 138.

The 400 transistors are each connected to a video line selection circuit 132. From this video line selection circuit 132, the transistors 140 are sequentially selected 1? A pulse voltage is output, and the transistors 140 are sequentially driven by this voltage.

A load resistor 134 and a power supply 136 are connected between the output terminal 138 and the ground, that is, the drain electrode 28, and the selected cell is controlled by the signal voltage output from the read address circuit 130 and the video line selection circuit 132. A drain current is formed and output as a voltage to the output terminal 1383.
The drive circuit will be described in detail in other embodiments.

Of the cells configured as described above, the semiconductor component is shown in FIG. 2, and the outline of the energy band in the force direction indicated by the arrow BA in this figure is shown in FIG. 3 (A). . Further, an outline of the energy band in the direction of arrow BB in FIG. 2 is shown in FIG. 3(B).

This energy band indicates a valence band, and indicates a state in which a positive voltage is applied to the drain electrode 128.

In FIG. 3(A), the convex portion of the energy band formed in the channel region 112 is mainly a part of a vacant layer caused by the diffusion potential between each region. The top P of this vacant layer is a portion called the true cage. On the other hand, in FIG. 3B, four parts of the energy band formed in the channel region 116 correspond to the vacant layer, and the bottom Q of the recess corresponds to the top P. Therefore, for example, among the electron-hole pairs generated by light incident on the channel region 112, the hole H is
It moves as indicated by the arrow HA in the figure, reaches the top P, that is, the bottom Q, and further moves to the cage area 114 where it is accumulated.

(9) In FIGS. 3A and 3B, the energy bands shown by solid lines are those of this embodiment, and the energy bands shown by broken lines are those of the channel region 112.
is formed of n single layers. That is, compared to the conventional case in which the channel region 112 is formed of n single layer, in this embodiment, as shown in FIG.
As shown in FIG. 2, the potential at the bottom Q becomes high, and therefore the potential barrier between the gate region 114 becomes shallow.

Additionally, the reduced potential barrier between dirt regions 114 is formed at the boundary between channel region 112 and substrate 110.

Next, the overall operation of this embodiment will be explained.

First, when light is incident on each cell, electron-hole pairs formed by the potential gradient portion formed in the channel region 112 are separated.

Among these, electrons move toward the drain electrode 128, and holes move toward the gate region 114 and are accumulated as shown in FIGS. 3(A) and 3(B) (10). O Next, when the transistor 40 is driven by the video line selection circuit 132, the power supply 136 is connected between the source electrode 122 and the drain electrode 128 via the resistor 134. Furthermore, the read address circuit 130
When an iR pulse voltage is applied to the dirt region 114, a drain current corresponding to the amount of holes accumulated in the dirt region 114, that is, the amount of incident light flows through the resistor B4.

This converts the drain current into voltage and output terminal 1
38.

As described above, information is read by applying a necessary voltage to the start region 114.

Therefore, if the potential recess formed between the gate regions 114 is deep as in the conventional case, the channel O
Process fluctuations have a large influence on the control of N and OFF, but in this embodiment, since the recesses are formed shallowly, the influence of process fluctuations is reduced.

Also, from another perspective, it can be considered as follows. That is, in this embodiment, part of the potential barrier between the gate region 114 and the channel regions 1 and 12 and the substrate 1
It can be considered that it is divided into 10 parts. Therefore, the influence of process variations is partially borne by the boundary between the channel region 112 and the substrate 110. However, since the formation of the channel region 112 on the substrate 110 is commonly performed for all Mg cells of the imaging device, and is performed by a well-known well-known epitaxial growth method, the influence of process variations is small. , at least
The process variations occurring in the target region 114 are sufficiently negligible. In other words, the impact of process variations is reduced by the amount corresponding to the potential barrier distributed at the boundary between the channel region 112 and the substrate 110.

FIG. 4 shows another improved embodiment of the solid-state imaging device according to the present invention. In this figure, (G) is a partially cutaway plan view, and (■) is a partially omitted end view seen from the direction of the arrow ■ in the plan view of (A). Furthermore, the end face corresponding to FIG. 1(B) is shown enlarged in FIG.

In these Figures 4(A) and 5), high impurity density N using materials such as silicon (St) is shown.
A channel region 12 made of a p-layer having a low impurity density is formed on a layered substrate 210 .

A control case region 214 consisting of a single layer with high impurity density is provided on the upper surface of the p layer forming this channel region 212.
A source region 216 made of an n-layer with high impurity density is provided around the source region 214 .

These control dart regions 214 and source regions 216 are arranged regularly and two-dimensionally in a matrix shape at appropriate intervals, as shown in FIG. (13) The region 214 and the source region 216 form a cell corresponding to one pixel.

Between adjacent source regions 216, there is a p region with high impurity density.
A floating cage region 218 made of + layer is formed. This floating gate region 218 is provided in common to adjacent cells, and is held at the same potential as the source region 216 or at a predetermined potential by suitable electrode means (not shown). As a result, a depletion layer or a potential barrier is formed in the channel region 212, and channels are separated between each cell. A silicon oxide (8102) film 220 is formed on the entire upper surface of the p-layer where the channel region 212 is formed except for the exposed portions of the control layer 214 and the source region 216.
is formed to protect the surface. source area 216
A source electrode 222 is formed in the exposed portion thereof, and is further connected in the direction in which the four cell source regions 216 are lined up. The direction of this connection is perpendicular to the direction of connection of the gate electrodes (14), which will be described later, as shown in Figure 4).

Next, a gate electrode 224 is formed on the exposed portion of the control gate region 214 with an insulating layer 226 interposed therebetween. The insulating layer 226 is made of, for example, a 5jO2 film,
is provided extending above the source electrode 222,
A gate electrode 224 is formed along this insulating layer 226.

That is, a capacitor is formed between the control gate region 214 and the gate electrode 224 by the insulating layer 226, and the source electrode 222 and the gate electrode 224 are insulated. This gate electrode 2
The direction of connection of cell 24 and the direction of connection of source electrode 222 are perpendicular to each other, making it possible to read out information stored in any cell. That is, by selecting any one of the plurality of source electrodes 222 and selecting any one of the plurality of key-1 electrodes 224, the cell at the intersection of both electrodes is selected.

A drain electrode 228 is formed on the opposite side of the substrate 210 from the p-layer where the channel region 212 is formed.

Next, the electrical equinodal circuit of the solid-state imaging device having the above-described structure and the connection between each electrode will be explained.

FIG. 6 shows the connections between the electrical circuit and external devices. Some of the connections with external devices are also shown in FIG. In these figures, a plurality of cells pc corresponding to each pixel are two-dimensionally arranged in a matrix, as shown in FIG. 4(A). (See Figure 6).

The plurality of dirt electrodes 224 have a read address circuit 2.
30 are connected to each other, and a pulse voltage for reading is applied in turn. On the other hand, the plurality of source electrodes 222 are connected to the transistor 2 that performs a switching operation.
40 drains, respectively. The sources of the plurality of transistors 240 are respectively connected to the output terminal 238, and the gates are connected to the video line selection circuit 238.
32, respectively. The video line selection circuit 232 sequentially outputs selection voltages to the transistors 240, which sequentially activate the transistors 240.

The transistor 240 is configured by, for example, an SIT that is normally in an "OFF" state, and the read address circuit 230 and the video line selection circuit 232 are configured by, for example, a shift register.

In addition, the output terminal 238 and the ground, that is, the drain electrode 2
A load resistor 234 and a power source 236 are connected between the 28 and 28, thereby forming a drain current at the time of reading, and further converting the drain current into a voltage.

In addition, in FIG. 6, the region IM indicated by a chain line corresponds to the part of the structure shown in FIG. 4(A) and the like.

Next, the overall operation of the above embodiment will be explained.

First, when light is incident on each cell, electron-hole pairs are generated in the potential gradient portion formed from the control dart region 214 to the channel region 212. Specifically, the incident light is
The channel region 212 mainly passes through the channel region 214.
electron-hole pairs are generated. Of the generated electron-hole pairs, electrons move toward the drain electrode 228, and holes move toward the control gate region 214 and are accumulated. This accumulation of holes is due to the fact that a capacitor is formed between the control gate region 214 and the gate electrode 224.

Through the above operations, image information is accumulated in each cell. Next, the video line selection circuit 232 applies a selection Noculus voltage to the transistor 240 connected to one of the plurality of source electrodes 222. As a result, the corresponding transistor 240 is driven, and the sources ilE&222 (18
) and the drain electrode 228 are connected to the power supply 23 via a resistor 234.
Connected to 6. This completes the preparation for the drain current to flow. Note that in this state, for example, the voltage of the power supply 236 is adjusted so that each cell PC is in a non-conductive state.

Through the above operations, the target video line from which image information is to be read is selected. Next, the Noyals voltage is sequentially applied to the plurality of gate electrodes 224 by the lead address circuit 230.

As a result, the cells PC located on the selected video line become conductive one after another, and a drain current corresponding to the amount of holes accumulated in the control gate region 214, that is, the amount of incident light flows through the resistor 234. Furthermore, the resistance 234
The voltage is converted into a voltage and output from the output terminal 238.

Through the above operation, the image number information corresponding to the incident light is outputted satisfactorily by changing the voltage of the output terminal 23B.

In the embodiments described above, the control region 214 is surrounded by the source region 216, but it is not necessary to adopt such a configuration. Further, a plurality of source regions 216 may be provided,
These may be connected by a source electrode 222.

Furthermore, in the embodiment described above, holes are accumulated due to light entering the floating gate region 218, resulting in a problem in that the cells PC are not well isolated from each other.

Still another embodiment that eliminates such inconvenience will be described. FIGS. 7(A) and 7(B) show still other embodiments of the present invention, and FIG. 7(A) is similar to FIG. 4(A).
), and FIG. 7(B) is a plan view corresponding to FIG.
) is a view of the end opening corresponding to FIG. 7(A) as seen from the arrow ■. In addition, this figure 7 (A), (B)
4 to 6, the same reference numerals are used for the same components as in FIGS. 4 to 6, and the description thereof will be omitted.

In the embodiment shown in FIGS. 7(A) and 7(13), the source region 246 is the control region
It is not provided around 14, but only on the - side. Furthermore, the source region 246 is connected to the floating gate region 2
It is located close to 18. That is, the distance between the source region 246 and the 70-chiing gate region 218 is set as WA, and the distance between the source region 246 and the control gate region 2i is
Letting the distance from + to WB be the relationship WA<WB.

If this is done, the potential barrier formed on the floating gate region 218 side will be higher than the potential barrier or diffusion potential formed on the control gate region 214 side, so that the separation between the cell PCs will be reduced. Becomes good.

Furthermore, in this embodiment, an aluminum shearing film 244 is formed on the source region 246 and floating gate region 218 with an insulating film 242 interposed therebetween. Therefore, no light enters the floating gate region 218, and holes (21) are not accumulated in the 70-teinggut region 218. Therefore, the isolation between the cells PC becomes good.

This improvement in isolation between cells can also be achieved by forming the floating gate region 218 deeper relative to the channel region 212 than the control gate region 214; Control gate region 214 for impurity density
This can also be achieved by making it higher than .

By using any one of the above means or a combination of a plurality of means, the cell PCs can be completely separated, and the degree of integration of the cell PCs arranged per unit area can be significantly improved.

FIG. 8 shows yet another embodiment of the invention.

This embodiment corresponds to the embodiment shown in FIG. 1, but the same applies to the embodiment shown in FIG. 4 or FIG. Note that the same reference numerals are used for the same components as those shown in FIG. 1 above, and the description thereof will be omitted.

(22) In this embodiment, the channel region is formed by two layers. That is, a channel region 112A made of a p+ layer is formed in a portion in contact with the gate region 114.
is formed, and between this channel region 112A and the substrate 110, another channel region 1 consisting of n single layer is formed.
12B is formed. Even in such a configuration, the influence of process fluctuations can be reduced as described above.

It should be noted that even if the source and drain are made to correspond inversely to those in the above embodiment, the same effect can be achieved. The same applies to the application of pulse voltages for video line selection, reading, and reading, and the above embodiments may be reversed.

Well, the driving transistor 140.240 may be a normal transistor, and this transistor 140
, 240 and the protruding address circuit 130, 230,
The video line selection circuits 132 and 232 may be integrated with the imaging device to form an integrated circuit. Although silicon was mainly used as the material, the present invention is not limited to this in any way; dalmanium, m-v
Group compound semiconductors and the like can also be used.

Furthermore, in order to obtain color image information, the matrix of the cell PC is configured to correspond to, for example, red (6), green (G), and blue (B), and the R , G, and H may be separated and made to enter each cell PC.

Further, when the gate region is formed of an n+ layer, the channel region may be formed of a single n layer.

Note that the impurity density of the p layer in the channel region is, for example, 1
012 to 1015 cm-3, preferably 1013 to 10 cm.

As explained above, according to the present invention, the layer in which the channel region is formed is made of the same type of semiconductor as the layer in which the channel region is formed, and has a lower impurity density than the dirt region. Since it is formed in this way, it has sufficient tolerance against process variations, and has excellent effects in that it is possible to improve the degree of cell integration.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a unit cell constituting a solid-state imaging device according to the present invention, FIG. 2 is a perspective view showing a semiconductor layer portion of the components shown in FIG. 1, and FIG. ),
(B) is an explanatory diagram showing an outline of the state of the energy band, FIG. 4 (A) is a partially cutaway plan view showing another embodiment of the present invention, and FIG. ), Figure 5 is an end view showing an enlarged part of Figure 4 (B), Figure 6 is a circuit diagram showing the configuration of the electric circuit, Figure 7 (A) Brush FIG. 7 is a plan view showing another embodiment of the present invention (
8) is an end view seen from the arrow ``■'' in FIG. 7(A), and FIG. 8 is a sectional view showing still another embodiment of the present invention. Explanation of symbols of main parts 112.212.112AS112B... Channel region 114.214... Dirt region 124.224... Dirt electrode (25) H... - Hole P C... Cell shadow Kei Layer 65X Jun- Patent applicant Fuji Photo Film Co., Ltd. (26)

Claims (1)

[Claims] A plurality of SIT cells each having a capacitor formed on the gate electrode are arranged, and carriers corresponding to the amount of light incident on each cell are accumulated in the gate region in contact with the channel region. In a solid-state imaging device in which the drain current changes, the dirt region is a semiconductor layer that is the same type of semiconductor as the dirt region and has an impurity density lower than that of the semiconductor layer in which the dirt region is formed. A solid-state imaging device characterized in that it is provided in contact with a region.