JPS59107637A - Logical circuit - Google Patents

Abstract

PURPOSE:To attain the constitution of a logical circuit with low power consumption, with high speed and with a small number of elements by constituting a multiplexer having a 2-input ECL gate by connecting ECL gates in cascade. CONSTITUTION:An x' and A (where; x is a control signal and A is an input signal) are ANDed by connecting in cascade the ECL gates E8, E9. Further, a gate current of the ECL gates E11, E12 is controlled by the ECL gate E10 to which a control signal (y) is inputted, the gate current flows to the gate E11 when the signal (y) is at L level and the gate current flows to the gate E12 when the signal (y) is at H level. Moreover, the gates E11, E12 are 2-input ECL gates, input signals B, A are inputted to one input of them and a signal D level-shifting an output of opposite phase of the gate E8 is inputted to the other input. Then, the x, y and B' are ANDed at the gate E11 and x, y and A are ANDed similarly at the gate E12. Thus, the circuit with low power consumption is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic circuit composed of ECL gates among semiconductor integrated circuits, and particularly to a multiplexer.

2. Conventional configuration and its problems Logic circuits have recently become more highly integrated and faster due to the development of semiconductor fat circuits.

ECL gates are often used to configure high-speed logic circuits, but in addition to high-speed circuit configurations, there is a growing demand for the development of circuit configurations with lower power consumption in order to increase the integration of ECL gates. .

In general, a multiplexer configured in an ECL gate has the following relationship, where n is the number of input signals and m is the number of control signals. It outputs one of the input signals. In the following explanation, the number of input signals n=3 (assumed to be A, B, and C, respectively), the number of control signals m
-2 (X and Y, respectively) multiplexer is taken as an example, and the relationship between the control signal and the output signal 8 is as shown in Table 1.

3 l] Table 1 The multiplexer shown in Table 1 is shown in a logic diagram as shown in FIG. In FIG. 1, 1,2.degree.3 is an AND gate, 4 is an OR gate, and the output signal 6 is expressed by the following equation.

5=xeA+xsy@B+xsy++c (2) The multiplexer shown in Table 1 and FIG.
An example of a circuit configuration using gates is shown in FIG. 2 and will be described. Second
In the figure, -VEE, BIAS1° BIAS are constant voltage power supplies, I, , I2 . T3 (Ii constant current source, R1-R6 are resistors, T1-T1□ are transistors. Also, T1 and T2.T3 and T4.T6 and T6.
T9 and T101T11 and TI2+T13 and T141T1
5 and T16 are ECL gates E1.5 and T16, respectively. R2, R3
, R4, R5゜R6゜R7 are configured and input signals A, B, and c are connected to ECL gates E2 and ES, respectively.
, the control signals x and y input to R7 are ECL respectively.
Gate E1. It is input to R3. T8 and R4, T7
and R6, T1□ and R6 each constitute a level shift circuit using an emitter follower.

The operation of the multiplexer in FIG. 2 will be explained in relation to that in FIG. 1.The ECL gate E1. By vertically stacking R2, the AND of x and A is taken, which corresponds to AND gate 1 in FIG. J: Sux to stack El and R3 vertically.
By taking the logical product of y, x, and y and inputting it to R4 and R6, respectively, via a level shift circuit, X is obtained by vertically stacking R4 and R5.

Y, B, R6 and R7 stacked vertically"ry)c
The AND gates 2 and 2 of FIG.
and 3. ? f, ta, ECL gate E2. R5
゜Wired OR by directly connecting the output of R7
The logic is taken, corresponding to the OR gate 4 in FIG. 1, and the output S
(As shown in the rumor formula, it is required.

An example of a conventional multiplexer constructed from ECL gates shown in Fig. 2 has been explained above, but when constructing an AND gate by stacking ECL gates vertically, the number of inputs increases depending on the number of stages that can be stacked vertically. Due to the limitations, a multi-input AND gate must be divided into multiple AND gates, and therefore multiple constant current sources for the ECL gate are also required. The circuit shown in Figure 2 requires three constant current sources and three emitter follower circuits for the ECL gate, which consumes a lot of power and is slow. It's also late. In Fig. 2, the number of stages that can be stacked vertically of ECL gates is two stages, but even if the number of stages is other than that, if the number of control signals is greater than or equal to the number of stages that can be stacked vertically of ECL gates. for,
Similar to the circuit shown in FIG. 2, the circuit configuration consumes a lot of power and is slow.

In high-speed logic circuits, data is often processed in parallel, and multiplexers are required for the number of data pits, so circuits with high power consumption are It becomes a factor.

Purpose of the Invention In view of such conventional problems, the present invention aims to provide a logic circuit with low power consumption, high speed, and a small number of elements. If the number of control signals is greater than or equal to the number of stages that can be stacked vertically, a multiplexer configured by stacking ECL gates vertically has a two-man ECL gate, and the number of stages of the two-man ECL gate is By inputting the input signal of the multiplexer to one side, controlling the 'i1Y, voltage and gate current of the input terminals of this two-man power ECL gate with the control signal, and selecting and outputting the input signal, power consumption can be reduced. This makes it possible to construct a high-speed logic circuit with a small number of elements.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows an embodiment of the present invention, in which the multiplexer shown in Table 1 and FIG. 1 is constructed in accordance with the present invention. In Fig. 3 as well, the number of vertically stackable ECL games i is set to two, as in the second figure.

Figure 3: Nioite, -VEE, BIASl, BIAS2[
A constant voltage source is shown in the same manner as in FIG. 2, and I4. I is a constant current source, R7-R9 are resistors, and T18 to T3o are transistors. Also, T18 and "19? T20 and T21 and T22
and T231 T24 and T25 and T261 T27 and T2
8 and T29 are ECL gates E8.8 and T29, respectively. R9, El
o, Ell, and R12, and input signals A, B,
C is the ECL gate E9. Control signals x and y are input to ECL gates E8.Ell and R12, respectively.
El.

is input. Here, ECL gate "111" 12
is a two-man powered ECL gate which is the main component of the present invention. D
l is a diode, and T3o and R9 are level shift circuits using emitter followers.

The circuit operation of the multiplexer according to the present invention shown in FIG. 3 will be explained with reference to FIG. 1. In Figure 3, EC
L gate E8. By stacking R9 vertically, the AND of x and A is taken as in the conventional example shown in Fig. 2, and the AND of Fig. 1 is obtained.
Corresponds to gate 1.

Next, ECL gate E11. The gate current of R12 is controlled by the ECL gate E1o to which the control signal y is input. When y is L, a gate current flows through Ell, and when y is H
When "12", the gate current flows.

In addition, the ECL gate E111E12 is a two-man powered EC.
It is an L gate, and input signals B and A are input to one input of each, and EC is commonly input to the other input.
A signal obtained by level-shifting the reverse phase output of the L gate E8 by the diode D1 is input. That is, E.C.
If the signal FjD is at a low level when the gate current flows through the L gate E11, the transistor T25
is off, and input signal B is output. If the signal is at high level, the transistor T25
is turned on and the gate current flows through T26, so input signal B is not output. Here, the signal becomes Low level when the control signal X is H, and the two-man ECL
The gate current flows through the gate E1 when the control signal y is L.
Therefore, in the ECL game "'11", x
, y, and B, corresponding to AND9 . . . -gate 2 in FIG. Next, in the ECL gate E12, the AND of x, y, and A is similarly taken, and the AN of FIG.
Corresponds to D gate 3. Also ECL gate E91”11
By directly connecting the output of 1E12, wired OR logic is implemented, corresponding to OR gate 4 in Figure 1,
The output S is obtained as shown in the rumor formula.

As described above, according to this embodiment, when the number of input signals of the multiplexer is 2 and is equal to the number of vertically stackable ECL stages, the input signal of the multiplexer is input to one side of the EC.
The voltage and gate current of the other input terminal of the L gate are
By controlling each multiplexer using control signals x and y, only two ECL gate constant current sources and one emitter follower circuit are required, resulting in a circuit with lower power consumption than the conventional example shown in Figure 2. can.

Further, since the logic can be maintained by the delay of two stages of ECL gates, a high-speed circuit configuration can be achieved and the number of elements can be reduced.

In this embodiment shown in FIG. 3, full 1o--
- Increase the number of control signals of the dithibrexa to 2. Although a circuit example has been shown in which the number of input signals is increased by 3 and the number of vertically stackable ECL gates is limited to 2, the present invention provides a circuit in which the number of multiplexer control signals is equal to the number of vertically stackable ECL gates. This is not to say that it is easy to adapt to situations with large numbers of people.

Effects of the Invention As described above, according to the present invention, an excellent logic circuit can be realized in which a multiplexer can be constructed at low power consumption, at high speed, and with a small number of elements.
゜

[Brief explanation of the drawing]

Fig. 1 is a logic gate circuit diagram of the multiplexer shown in Table 1, Fig. 2 is a detailed circuit diagram of a conventional example in which the logic gates in Fig. 1 are configured with ECL gates, and Fig. 3 is a diagram of an embodiment of the present invention. It is a logic circuit diagram concerning. E8~E1゜・・・・One-man ECL gate, Ell
, R12...Two-man ECL gate, x, y...
...Control signal, A, B, C...Input signal.

Claims (1)

[Claims] The number of control signals of the multiplexer is equal to or greater than the number of vertically stackable ECL gates, and
There are two multiplexers configured by vertically stacking L gates.
A multiplexer input signal is applied to one input terminal of the two-manpower ECL gate, and the voltage applied to one input terminal and the other input terminal of the two-manpower ECL gate is switched, and the gate of the two-manpower ECL gate is A logic circuit characterized in that current switching is controlled by an output signal of an ECL gate to which the control signal is applied to select and output the input signal.