JPS59107552A - Semiconductor device with recommended electrode terminal construction - Google Patents

Semiconductor device with recommended electrode terminal construction

Info

Publication number
JPS59107552A
JPS59107552A JP21795982A JP21795982A JPS59107552A JP S59107552 A JPS59107552 A JP S59107552A JP 21795982 A JP21795982 A JP 21795982A JP 21795982 A JP21795982 A JP 21795982A JP S59107552 A JPS59107552 A JP S59107552A
Authority
JP
Japan
Prior art keywords
electrode terminal
conductors
semiconductor device
electrode
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21795982A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamanouchi
博 山之内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP21795982A priority Critical patent/JPS59107552A/en
Publication of JPS59107552A publication Critical patent/JPS59107552A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To manufacture a compact semiconductor device with lead integration by a method wherein conductors for measurement are provided on the same main surface of electrode terminals connected to the conductors. CONSTITUTION:Bump electrodes 43-43'' are formed on an SiO2 film 41 on an Si substrate 40 with transistor etc. built in to be connected to internal wirings through metal wirings 42-42''. Conductors 46-46'' for measurement are provided between the wirings 42-42'' and the bump electrodes 43-43'' to be connected to the internal wirings and the bump electrode 43-43'' through metal conductors 42-42''. The conductors 46-46'' to be utilized for measurement only may be provided with their gaps contracted down to around 10mum while the bump electrode to be utilized for connection with leads only may be provided with their size of around 40mum. Resultantly the leads may be highly integrated with the effect increasing especially in proportion to the numbers of electrodes.

Description

【発明の詳細な説明】 本発明は半導体装置に於ける電極端子構造に関し、竹に
好寸しくけ半導体素子に多数の外部導出用リード端子を
取り付ける半導体装置の電極端子構造に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode terminal structure for a semiconductor device, and more particularly, to an electrode terminal structure for a semiconductor device in which a large number of external lead terminals are attached to a semiconductor element mounted on bamboo to a suitable size.

半導体素子の電極と容器の外側のリード線との間を電気
的に接続する方法が睡々提案されている中で、細い導線
を使用して相互に接続すべき点に接着する従来のワイヤ
ボンディング方式に代わって容器の内側のリード線を延
長し、又は可撓性の電気絶縁材料で作られたテープ面に
金属材料の連続状のリボンを付着し、金属箔から多数の
リードを形成し、かつその端部を先細として半導体装置
の電極端子に直接接着するに充分な接着端を形成し、電
極端子に同時に接続する方法が提案されている。
While many methods have been proposed for electrically connecting the electrodes of a semiconductor device and the lead wires on the outside of the container, conventional wire bonding, which uses thin conductive wires and adheres them to the points to be connected to each other, has been proposed. Alternatively, extend the lead wire inside the container, or attach a continuous ribbon of metal material to the tape surface made of flexible electrically insulating material, and form a large number of leads from metal foil. A method has been proposed in which the end portion is tapered to form an adhesive end sufficient to directly adhere to the electrode terminal of a semiconductor device, and the adhesive end is simultaneously connected to the electrode terminal.

上記接続法を実施する為、リード線の接着端に対応する
半導体素子の電極端子は通常金属で構成された突起電極
(バンプ)となっておJ、通常、バンプは半導体素子の
活性領域を配線しかつ電極部分を形成する金属により半
導体素子面の絶縁膜上に引きだした位置でAuで形成さ
れている。、前記接続法には、銅を基体とするリードに
錫を複せ金バンプとの間で熱によシ金−錫の共晶合金を
形成し接続する合金接続法と、銅を基体とするリードに
金を被せ金バンプとの間で熱と圧力により接続する熱圧
着法とがある。金−錫の合金接続法は錫の合金接続法は
錫の単結晶によるウィスカーがリード間の電気的短絡を
発生させるという欠点の為信頼性を要求される半導体装
置では金−金の熱圧着法が用いられる傾向にある。
To carry out the above connection method, the electrode terminal of the semiconductor element corresponding to the adhesive end of the lead wire is usually a protruding electrode (bump) made of metal.Usually, the bump connects the active area of the semiconductor element. Moreover, the metal forming the electrode portion is formed of Au at a position extending above the insulating film on the surface of the semiconductor element. , the above connection method includes an alloy connection method in which a copper-based lead is layered with tin and a gold bump is formed to form a heat-reduced gold-tin eutectic alloy for connection; There is a thermocompression bonding method in which a lead is coated with gold and connected to a gold bump using heat and pressure. The gold-tin alloy bonding method has the disadvantage that tin single-crystal whiskers can cause electrical shorts between leads.For semiconductor devices that require reliability, the gold-gold thermocompression bonding method is used. tends to be used.

通常、半導体装置は一枚のシリコン基板(ウェハー)上
に複数個形成され、ウエノ・−状で拡散・配線処理を行
なった後、電極端子に探針を立て電気的特性検査(以後
電気テストと称す)を行なう。
Normally, multiple semiconductor devices are formed on a single silicon substrate (wafer), and after being diffused and wired in a wafer shape, a probe is placed on the electrode terminal to conduct an electrical characteristic test (hereinafter referred to as electrical test). ).

その後レーザ光線による窪み形成又は薄いダイヤモンド
ホイールによる切断等により個々の半導体素子(半導体
チップ)に分離し、電気テストの良品を容器に組み込み
半導体素子の電極端子と容器のリードとを接続する。
Thereafter, it is separated into individual semiconductor elements (semiconductor chips) by forming a depression with a laser beam or cutting with a thin diamond wheel, and the products that pass the electrical test are placed in a container, and the electrode terminals of the semiconductor elements and the leads of the container are connected.

半導体素子の電極端子(バング)のサイズ及びびピッチ
は以下の要因によって決定される。
The size and pitch of the electrode terminals (bungs) of a semiconductor device are determined by the following factors.

(1)バンプサイズは電気テストの面からは探針のサイ
ズ及びウェハー状で複数個の半導体素子を測定する為、
連続して複数個測定した時のバンプと探針との位置合わ
せ精度によって決定される。又リードとバンクとの接続
(ホンデインク)の面からはリードの製法上の制約及び
接続強度から決定される。しかしリードとバンプの接続
の面では約40μで充分なのに対し電気テストの面から
は約100μ以下のバングサイズにすることが困難であ
る。
(1) From an electrical test perspective, the bump size is the size of a probe and the size of a wafer, as it measures multiple semiconductor devices.
It is determined by the alignment accuracy between the bump and the probe when measuring multiple bumps in succession. In addition, the connection between the lead and the bank (Honda ink) is determined based on the constraints on the manufacturing method of the lead and the connection strength. However, while about 40 μm is sufficient for connecting leads and bumps, it is difficult to reduce the bump size to about 100 μm or less from the standpoint of electrical testing.

Q)バンプ・ピッチは電気テストの面からは電気テスト
の探針の配列可能なピッチによって決定され探針の配列
ピッチよりは小さくできずその寸法によって制限されて
いる。又ボンディングの面からは隣シ合うバンプの間隔
(クリアランス)はボンディングに於ける熱と圧力によ
ってリード及びバンプが塑性変形を起こす為、このリー
ド及びバンプの塑性変形によシ隣り合うバンプ又はリー
ドが接触しない間隔が必要とされる。
Q) From the standpoint of electrical testing, the bump pitch is determined by the pitch at which electrical testing probes can be arranged, and cannot be smaller than the arrangement pitch of the probes, and is limited by its size. Also, from the bonding perspective, the distance between adjacent bumps (clearance) is determined by the fact that leads and bumps undergo plastic deformation due to heat and pressure during bonding. Non-contact spacing is required.

周知の如く半導体装置の価格は半導体チップサイズによ
って大きく影響を受けるが、従来の¥t、極端子構造で
は電気テストの探針立てとリードとの接続は同一の電極
端子に対して行なわれる構造であシ、その結果電気テス
トの面からの制約とボンデインクの面からの制約を解決
するのが困難である。すなわち探針の配列可能なピッチ
でバンプピッチを、小さくする方法として隣シ合うバン
プの間隔を小さくすることは、ボンティングに於ける熱
と圧力によるバンプの塑性変形によってバンプ間の電気
的短絡が生じてしまい適用できない。又ボンディング可
能なバンプサイズにすることはバンプと探針の位置合わ
せが困難になり電気テストが出来なくなってしまう。こ
の結果、半導体装置の大規模集積化に伴ない半導体チッ
プサイズは電極端子数によって決定される傾向にあり、
半導体装置の価格が高価になってしまう。
As is well known, the price of semiconductor devices is greatly affected by the size of the semiconductor chip, but in the conventional ¥t, electrode terminal structure, the electrical test probe stand and lead are connected to the same electrode terminal. As a result, it is difficult to overcome the constraints in terms of electrical testing and bonding. In other words, reducing the distance between adjacent bumps is a method of reducing the bump pitch to a pitch that allows the probe to be arranged, since electrical short circuits between bumps may occur due to plastic deformation of the bumps due to heat and pressure during bonding. occurs and cannot be applied. Furthermore, if the bump size is set to allow bonding, it becomes difficult to align the bump and the probe, making it impossible to conduct electrical tests. As a result, with the large-scale integration of semiconductor devices, the semiconductor chip size tends to be determined by the number of electrode terminals.
The price of semiconductor devices becomes expensive.

本発明の目的は突起電極を有する半導体素子と外部リー
ドとの接続に於いて、前記欠点を除き小型でリードの集
積密度の高い、かつ安価に製品できる半導体装置の電極
構造を提供することである。
An object of the present invention is to provide an electrode structure for a semiconductor device that is compact, has a high integration density of leads, and can be manufactured at low cost by eliminating the above-mentioned drawbacks in connection between a semiconductor element having a protruding electrode and an external lead. .

本発明の特徴は、半導体基板の一生面に設けられた電極
端子に外部導出用リードを接続する半導体装置に於いて
、該電極端子と同一主面に測定用導体を形成し7かつ該
究極端子と測定用導体とを電気的に接続したことである
A feature of the present invention is that in a semiconductor device in which an external lead is connected to an electrode terminal provided on one surface of a semiconductor substrate, a measuring conductor is formed on the same main surface as the electrode terminal, and the ultimate terminal and the measurement conductor are electrically connected.

以下、図面を用いて本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail using the drawings.

第11(ハ)及び0は従来の電棲端子摺造を示すもので
ある。第1図に於ててトランジスター、ダイオード、抵
抗等の半導体素子を内解し六牛導体基板10−Eに形成
された酸化酸等のP!紗成膜11上突起気任13が形成
これている。この突起゛寛栖は金属配#導体12によっ
て活性領域の内部配線(図中では省略)と接続されてい
る。かかるV極端子構造を有した半導体素子の電気テス
トを行なう方法について示したのが勢:2図へ及び(ハ
)であシ、外部導出用リードとの接続法について示した
のが第3図中)及び0勺である。
No. 11 (c) and 0 show conventional electrical terminal sliding construction. In FIG. 1, P! The upper projections 13 of the gauze film 11 are formed. This protrusion is connected to internal wiring (not shown in the figure) of the active region by a metal wiring conductor 12. Figures 2 and (c) show how to conduct an electrical test on a semiconductor device having such a V-pole terminal structure, and Figure 3 shows how to connect it to external leads. medium) and 0.

電気テストは探針24,24’ 、24” 、24”’
 、・・・を突起電梗23 、23’ 、 24” 、
 23”’、・・・に立てて行なうが、探針は1済性の
面で数十枚pl上のウェハーを測定する必要性がおシ、
機緘的強度が習いこと及び耐摩耗、性が高いことが要求
される為、探針サイズは数十μでその先端は先細とたっ
ている。
For electrical tests, probes 24, 24', 24", 24"'
,... with protrusions 23, 23', 24'',
23'',... However, the probe needs to measure several tens of wafers in terms of one-shot performance.
Since mechanical strength and wear resistance are required, the probe size is several tens of microns and its tip is tapered.

電気テストは複数個の半導体素子を連続して測定する為
、探針と突起電極との位置合わせ精度から突起電極のサ
イズは約100μ口である。向、電気テストに於いて突
起電極は塑性変形が生じない為隣シ合う突起電極の間隔
は約10μ前後にすることは可能である。
Since the electrical test measures a plurality of semiconductor elements in succession, the size of the protruding electrode is approximately 100 μm due to the alignment accuracy between the probe and the protruding electrode. On the other hand, since the protruding electrodes do not undergo plastic deformation during electrical tests, it is possible to set the distance between adjacent protruding electrodes to about 10 μm.

外部導出用リードと電極端子との接続ボンディングは接
続用リード35.35’を突起電極33.33’に位置
合わせし熱・圧力を加えてリード 及び突起電極に塑性
変形を起こさせて接続する。このリード及び突起電極の
塑性変形によシリード35と35′又は突起電極33と
33′ が接触することを防止する為、隣り合う電極端
子の間隔(突起電極33と33′ の間隔)は約80前
後が必要である。
Connection bonding between the external leads and the electrode terminals is performed by aligning the connection leads 35, 35' with the protruding electrodes 33, 33', and applying heat and pressure to cause plastic deformation in the leads and protruding electrodes. In order to prevent the series leads 35 and 35' or the protruding electrodes 33 and 33' from coming into contact with each other due to plastic deformation of the leads and protruding electrodes, the interval between adjacent electrode terminals (the interval between the protruding electrodes 33 and 33') is approximately 80 mm. The front and back are necessary.

従来の電極端子構造では探針と電極端子との位置合わせ
精度、及びリード又は電極端子の塑性変形の問題を有す
る為、電極端子サイズを約100μ以下に又電極端子間
の間隔を約80μ以下にすることが困難である。
Conventional electrode terminal structures have problems with alignment accuracy between the probe and electrode terminals, and plastic deformation of the leads or electrode terminals. Therefore, the electrode terminal size should be reduced to approximately 100μ or less, and the spacing between electrode terminals should be reduced to approximately 80μ or less. difficult to do.

第4図(へ)及び(ハ)は本発明の実施例を示すもので
おる。第4図に於いて、トランジスタ、タイオード、抵
抗等を内蔵する半導体基板40上に形成された酸化膜等
の絶縁M41上に突起電極43.43’。
FIGS. 4(f) and (c) show an embodiment of the present invention. In FIG. 4, protruding electrodes 43 and 43' are formed on an insulating layer M41 such as an oxide film formed on a semiconductor substrate 40 containing transistors, diodes, resistors, etc.

43″  が形成されている。この突起電析43,43
’。
43'' is formed.This protrusion electrodeposition 43,43
'.

43′は金属配線導体42,42’ 、43”  によ
って活性領域の内部配線(図中では省略)と接続され、
かつ金属配線導体42.42’ 、42″ と突起電極
との間に測定用導体46,4G’ 、46″ が形成さ
れている。この測定用導体46.46’ 、46”  
は金属配線導体42.42’ 、42″ によって活性
領域の内部配線(図中では省略)及び突起電極43,4
3’ 、43″と電気的に接続されている。
43' is connected to the internal wiring (not shown in the figure) of the active region by metal wiring conductors 42, 42', 43'';
Furthermore, measurement conductors 46, 4G', 46'' are formed between the metal wiring conductors 42, 42', 42'' and the protruding electrodes. This measuring conductor 46.46', 46"
The metal wiring conductors 42, 42' and 42'' connect the internal wiring of the active region (not shown in the figure) and the protruding electrodes 43, 4.
3' and 43''.

かかる電極端子構造を有する半導体素子の電気テストを
行なう方法について示したのが第5図四及び(ハ)であ
シ、外部導出用リードとの接続法について示しだのが第
6図(ハ)及び0でちる、電気テストは探針54 、5
4’  を測定用導体56.56’  に立てて行ない
、ボンデインクは接続用リード65.65’を突起電力
63.63’  に位置合わ七し、熱及び圧力を加えて
リード及び突起電極に塑性変形を起こされて行なう。測
定用導体に探針の斜立てにのみ利用される為、隣り合う
測定用導体の間隔(測定用導体56と56′ の間隔)
は約10μ前後にすることができ、突起電極はリードと
の接続にのみ利用される為、そのサイズは約40μにす
ることができる。その結果従来の電気テスト技術及びボ
ンディング技術をその!、ま適用しながら電極端子のサ
イズ及びピッチを小さくすることができ半導体チップの
サイズ小さくできかつ、リードの高集積化を行なうこと
ができる。
Figures 5 (4) and (c) show a method for conducting an electrical test on a semiconductor element having such an electrode terminal structure, and Figure 6 (c) shows a method for connecting to external leads. and 0, the electrical test uses the probe 54, 5
4' is placed on the measurement conductor 56.56', and bonded ink aligns the connection lead 65.65' with the protrusion power 63.63', and applies heat and pressure to plastically deform the lead and protrusion electrode. Wake up and do it. Since it is used only for tilting the probe on the measurement conductor, the distance between adjacent measurement conductors (the distance between measurement conductors 56 and 56') is
can be approximately 10μ, and since the protruding electrode is used only for connection with the lead, its size can be approximately 40μ. As a result, conventional electrical testing techniques and bonding techniques can be replaced! However, it is possible to reduce the size and pitch of the electrode terminals, reduce the size of the semiconductor chip, and increase the integration of the leads.

以上述べたように本発明によシ小型でリードの集積度が
高い、かつ安価な半導体装置が得られる。
As described above, according to the present invention, a semiconductor device that is small in size, has a high degree of lead integration, and is inexpensive can be obtained.

特にその効果は半導体素子の電極数が増大する程著しく
、その工業的測置は極めて大きい。
In particular, the effect becomes more remarkable as the number of electrodes in a semiconductor element increases, and its industrial application is extremely large.

伺、本発明の実施例に於いて測定用導体はπ(極端子に
対して半導体素子の活性領域側の隣りに形成したが、本
発明はこれに限定されることはない。
In the embodiment of the present invention, the measurement conductor was formed adjacent to the active region side of the semiconductor element with respect to the π (pole terminal), but the present invention is not limited thereto.

要はボンディング用の電極端子と電気的特性検査用の測
定用導体を分離し、かつ電極端子と測定用導体とが電気
的に接続されていれけかなわガい。
The point is that the electrode terminal for bonding and the measuring conductor for testing electrical characteristics must be separated, and the electrode terminal and the measuring conductor must be electrically connected.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(5)及び(13)は従来の電極端子構造を示す
平面図及び断面図である。第2図(ハ)は従来の電極端
子構造を有する半導体素子に電気テストの探針の斜立て
を示すもので、第2図(ハ)は第2図(2)に於いて破
線部分の断面図である。第3図(ト)及び(ハ)は従来
の電極端子を有する半導体素子のボンディングを示す平
面図及び断面図である。第4園内及び山は本発明の実施
例を示す平面図及び断面図である。 第5図い)及び0は本発明の実施例に於いて電気テスト
の探針の斜立てを示す平面図及び断面図である。第6図
(ハ)及び(ハ)は本発明の実施例に於いてボンディン
グを示す平面図及び断面図である。 伺、図中に於いて、10,20,30,40,50.6
0・・・・・・半導体基板、11,21,31,41,
51.61・・・・・・絶縁膜、12.12’ 、22
,32.32’ 、42.42’ 。 42″、52.52’ 、62.62’・・・・・・金
属配線導体、13゜13’ 、23,33.33’ 、
43.43’ 、53.53’ 、63゜63′・・・
・・・突起電極(電極端子)、24.24’ 、24″
’。 54 、54’・・・・・・探針、35.35’ 、6
5.65’・・・・・・外部導出用リードである。 z 3図 鼠 4図 <A) z 、5 (A ’) 、ヘヘ 叢 図
FIGS. 1 (5) and (13) are a plan view and a sectional view showing a conventional electrode terminal structure. Figure 2 (C) shows the inclined position of an electrical test probe on a semiconductor device having a conventional electrode terminal structure. It is a diagram. FIGS. 3(G) and 3(C) are a plan view and a sectional view showing bonding of a semiconductor element having conventional electrode terminals. The interior of the fourth park and the mountain are a plan view and a sectional view showing an embodiment of the present invention. FIGS. 5A and 5B are a plan view and a cross-sectional view showing an inclined probe for electrical testing in an embodiment of the present invention. FIGS. 6(C) and 6(C) are a plan view and a sectional view showing bonding in an embodiment of the present invention. In the figure, 10, 20, 30, 40, 50.6
0... Semiconductor substrate, 11, 21, 31, 41,
51.61...Insulating film, 12.12', 22
, 32.32', 42.42'. 42'', 52.52', 62.62'...Metal wiring conductor, 13°13', 23,33.33',
43.43', 53.53', 63°63'...
...Protruding electrode (electrode terminal), 24.24', 24''
'. 54, 54'... Probe, 35.35', 6
5.65'... Lead for external extraction. z 3 Figure Mouse 4 Figure <A) z , 5 (A'), Hehe plexus diagram

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一主面に設けらねた電極端子に外部導出用
リードを接続する半導体装置に於いて、該電極端、子と
同一主面に存在しかつ該電極端子と電り的に接続されて
いる測定用導体を有し、ていることを特徴とする好まし
い電極端子構造を有する半導体装置。
In a semiconductor device in which an external lead is connected to an electrode terminal provided on one main surface of a semiconductor substrate, the electrode end is located on the same main surface as the child and is electrically connected to the electrode terminal. What is claimed is: 1. A semiconductor device having a preferable electrode terminal structure, characterized in that the semiconductor device has a measuring conductor having a conductor for measurement;
JP21795982A 1982-12-13 1982-12-13 Semiconductor device with recommended electrode terminal construction Pending JPS59107552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21795982A JPS59107552A (en) 1982-12-13 1982-12-13 Semiconductor device with recommended electrode terminal construction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21795982A JPS59107552A (en) 1982-12-13 1982-12-13 Semiconductor device with recommended electrode terminal construction

Publications (1)

Publication Number Publication Date
JPS59107552A true JPS59107552A (en) 1984-06-21

Family

ID=16712399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21795982A Pending JPS59107552A (en) 1982-12-13 1982-12-13 Semiconductor device with recommended electrode terminal construction

Country Status (1)

Country Link
JP (1) JPS59107552A (en)

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